JPH05129932A - Semiconductor integrated circuit - Google Patents

Abstract

(57) [Summary] [Object] To improve a semiconductor integrated circuit, shorten a rise time and a fall time of an output signal without increasing power consumption, and achieve high speed operation. [Structure] The load resistors 7 and 8 are respectively replaced by minute resistors 33 and
Connected to the VCC power supply line 1 via 34.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to improvement of an output circuit incorporated in the semiconductor integrated circuit.

[0002]

2. Description of the Related Art Conventionally, as a semiconductor integrated circuit, a semiconductor integrated circuit having a built-in output circuit as shown in FIG. 9 is known.

In the figure, 1 is a power supply voltage VCC, for example, 0
A VCC power supply line for supplying [V], 2 is a power supply voltage VEE lower than the power supply voltage VCC, for example, -5.2 [V]
VEE power supply line 3 for supplying the negative phase data D, the negative phase data input terminal to which the negative phase data D bar having a negative phase relationship with the normal phase data D is inputted is there.

Further, 5 and 6 are NPN transistors which form a differential pair transistor, 7 and 8 are NPN transistors 5,
6 is a constant current source, 10 and 11 are NPN transistors for output, 12 and 13 are output terminals, X,
Y is output data.

FIG. 10 is a layout diagram of a part of such an output circuit. In the figure, 5A, 5B, 6A, and 6B are NPN.
It is a transistor. Here, NPN transistor 5
A and 5B constitute the NPN transistor 5 shown in FIG. 9, and the NPN transistors 6A and 6B are shown in FIG.
The NPN transistor 6 shown in FIG.

Incidentally, 14A and 14B are NPs, respectively.
The collectors of N transistors 5A and 5B, 15A,
15B is the collector of the NPN transistors 6A and 6B, respectively.

Further, 16 to 22 are first-layer wiring patterns, and in particular, the wiring pattern 18 constitutes the VCC power supply line 1 shown in FIG. Also, 23A to 23D, 24
A to 24D are resistors. Here, the resistors 23A to 23D
Represents the load resistor 7 shown in FIG. 9, and the resistors 24A to 24D form the load resistor 8 shown in FIG.

Further, 25A and 25B are NPN shown in FIG.
The collector of the transistor 10, 26 is the base of the NPN transistor 10, and 27A and 27B are the emitters of the NPN transistor 10.

28A and 28B are collectors of the NPN transistor 11, 29 is a base of the NPN transistor 11, and 30A and 30B are emitters of the NPN transistor 11. Further, 31 and 32 are second layer wiring patterns.

In such an output circuit, when D = L level and D bar = H level, the NPN transistor 6 =
OFF, NPN transistor 5 = ON, collector voltage of NPN transistor 6 = H level, collector voltage of NPN transistor 5 = L level, X = H level,
Y = L level.

When D = H level and D bar = L level, NPN transistor 6 = ON, NPN transistor 5 = OFF, NPN transistor 6 = L level, N
PN transistor 5 = H level, X = L level,
Y = H level.

[0012]

Here, in the case of changing from D = L level, D bar = H level to D = H level, D bar = L level, in the NPN transistor 10, the capacitance between the base and the collector is obtained. Discharge from the
In the NPN transistor 11, its base-collector capacitance is charged.

When changing from D = H level, D bar = L level to D = L level, D bar = H level, N
In the PN transistor 10, the base-collector capacitance is charged, and the NPN transistor 1
In No. 1, the base-collector capacitance is discharged.

Here, the output NPN transistor 1
In order to achieve the function, 0 and 11 are formed to have a large size, and the base-collector capacitance is large. Therefore, when changing the output data X and Y, it takes time to charge and discharge the capacitance between the base and collector, which prolongs the rise time and the fall time of the output data X and Y, which hinders the speedup. Was becoming.

The rising time and the falling time of the output data X, Y can be shortened by increasing the current of the constant current source 9, but this causes an increase in power consumption.

In view of the above points, the present invention incorporates an output circuit that can shorten the rise time and fall time of output data and increase the speed without increasing the power consumption. It is an object of the present invention to provide a semiconductor integrated circuit including the following.

[0017]

In a semiconductor integrated circuit according to the present invention, a first transistor for output which receives first data at its base and outputs first data at its emitter, and a base thereof. A second transistor for output which receives second data having a reverse phase relationship with the first data and outputs the second data to its emitter,
The first transistor is accelerated in the rise and fall of its base voltage in relation to the collector current of the second transistor, and the second transistor is related to the collector current of the first transistor. Then, the output circuit configured to accelerate the rise and fall of the base voltage is built in.

[0018]

According to the present invention, the output first and second transistors are accelerated in the rise and fall of their base voltages in relation to the collector currents of the second and first transistors, respectively. With this configuration, it is possible to shorten the rise time and fall time of the output data without increasing the current of the constant current source, that is, without increasing the power consumption.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 1 to 8, parts corresponding to those in FIGS. 9 and 10 are designated by the same reference numerals,
The duplicate description will be omitted.

FIG. 1 is a circuit diagram showing an output circuit incorporated in an embodiment of the present invention. In the present embodiment, the load resistor 7 is connected to the VCC power supply line 1 via the minute resistor 33, and the load resistor 8 is connected to the VCC power line 1 via the minute resistor 34.
It is connected to the power line 1.

The collector of the NPN transistor 10 is connected to the VCC power supply line 1 via the minute resistance 33, and the collector of the NPN transistor 11 is connected to the VCC power supply line 1 via the minute resistance 34. ing. Others are the same as those of the output circuit shown in FIG.

FIG. 2 is a layout diagram of a part of the output circuit shown in FIG. In this embodiment, the positions of the NPN transistors 10 and 11 are interchanged on the left and right sides in the drawing. Here, 35 is the first layer wiring, which is the VC shown in FIG.
It forms the C power supply line 1. Further, 36 and 37 are second layer wirings.

Further, in the present embodiment, the first layer wiring 3
5 (VCC power supply line 1), the wirings 38 and 39 are branched, and the wiring 38 is connected to the collectors 25A and 2A of the NPN transistor 10.
5B, and the wiring 39 is connected to the collectors 28A and 28B of the NPN transistor 11. That is, the branch wiring 38 is the minute resistance 33 shown in FIG. 1, and the branch wiring 39 is the minute resistance 34 shown in FIG.

In this embodiment, when D = L level and D bar = H level, the NPN transistor 6 =
OFF, NPN transistor 5 = ON, collector voltage of NPN transistor 6 = H level, collector voltage of NPN transistor 5 = L level, X = H level,
Y = L level.

When D = H level and D bar = L level, NPN transistor 6 = ON, NPN transistor 5 = OFF, collector voltage of NPN transistor 6 = L level, collector voltage of NPN transistor 5 = H
The level becomes X = L level and Y = H level.

As shown in FIG. 3, when changing from D = L level, D bar = H level to D = H level, D bar = L level, the collector voltage of the NPN transistor 6 and the NPN transistor 5 are changed. The collector voltage changes to L level and H level, respectively.

As a result, the collector current I _C10 of the NPN transistor 10 decreases and the collector current I _C11 of the NPN transistor 11 increases. Therefore, the small resistance 3
The voltage drop ΔV _{33 of} 3 is small, and the voltage drop ΔV ₃₄ of the minute resistor ₃₄ is large.

As a result, the base voltage of the NPN transistor 10 is accelerated at the falling edge and quickly drops to N.
The base voltage of the PN transistor 11 is rapidly accelerated and quickly rises, and the NPN transistor 10 becomes
The output data X is quickly changed from H level to L level, and NP
The N-transistor 11 quickly changes the output data Y from L level to H level.

Further, as shown in FIG. 4, D = H level,
When changing from D bar = L level to D = L level and D bar = H level, the collector voltage of the NPN transistor 6 and the collector voltage of the NPN transistor 5 change to H level and L level, respectively.

As a result, the collector current I _C10 of the NPN transistor 10 increases and the collector current I _C11 of the NPN transistor 11 decreases. Therefore, the small resistance 3
3 has a large voltage drop ΔV ₃₃ , and the minute resistor ₃₄ has a small voltage drop ΔV ₃₄ .

As a result, the base voltage of the NPN transistor 10 is accelerated at the rising edge and quickly rises to N.
The base voltage of the PN transistor 11 is accelerated at the fall and quickly becomes low, and the NPN transistor 10 becomes
The output data X is quickly changed from L level to H level, and NP
The N-transistor 11 quickly changes the output data Y from H level to L level.

Here, for example, when the H level of the output data X and Y is -0.90 [V] and the L level is -1.75 [V], the NPN transistors 10 and 11 output the H level. The collector current is 22 mA, the collector current when the NPN transistors 10 and 11 output the L level is 5 mA, and the minute resistors 33 and 34 are set to 1Ω.

First, as shown in FIG. 5, D = L level,
When D bar = H level, NPN transistor 6 =
When OFF and NPN transistor 5 = ON, X = H level and Y = L level, but in this case, collector current I _C10 of NPN transistor ₁₀ is 22 mA and collector current I _C11 of NPN transistor 11 is 5 mA.

Further, as shown in FIG. 6, D = H level,
When D bar = L level, NPN transistor 6 = O
N, NPN transistor 5 = OFF, X = L level,
Although Y = H level, in this case, the collector current I _C10 of the NPN transistor ₁₀ is 5 mA and the collector current I _C11 of the NPN transistor 11 is 22 mA.

As shown in FIG. 7, when changing from D = L level, D bar = H level to D = H level, D bar = L level, the collector voltage of the NPN transistor 6 and the NPN transistor 5 are changed. The collector voltage changes to L level and H level, respectively.

In this case, the collector current I _C10 of the NPN transistor 10 is reduced from 22 mA to 5 mA,
The collector current I _C11 of the transistor 11 is 5 mA to 2
Increase to 2mA.

As a result, the voltage drop ΔV _{33 of the} minute resistor _33.
Is 22 mA × 1Ω = 22 mV to 5 mA × 1Ω = 5 m
V, and the base voltage of the NPN transistor 11 becomes
It goes up by 17 mV. Therefore, the NPN transistor 11
Quickly reverses the output data Y from L level to H level.

On the other hand, the voltage drop Δ of the minute resistor 34
V ₃₄ is 5 mA x 1 Ω = 5 mV to 22 mA x 1 Ω = 2
It increases to 2 mV and the base voltage of the NPN transistor 10 drops by 17 mV. Therefore, the NPN transistor 10 quickly inverts the output data X from H level to L level.

Further, as shown in FIG. 8, D = H level,
When changing from D bar = L level to D = L level and D bar = H level, the collector voltage of the NPN transistor 6 and the collector voltage of the NPN transistor 5 become H level and L level, respectively.

In this case, the collector current I _C10 of the NPN transistor 10 increases from 5 mA to 22 mA.
The collector current I _C11 of the transistor 11 decreases from 22 mA to 5 mA.

As a result, the voltage drop ΔV _{33 of the} minute resistor _33.
Is 5mA × 1Ω = 5mV to 22mA × 1Ω = 22m
V, and the base voltage of the NPN transistor 10 becomes
17 mV down. Therefore, the NPN transistor 10
Quickly reverses the output data X from H level to L level.

On the other hand, the voltage drop Δ of the minute resistor 34
V ₃₄ is 22 mA × 1Ω = 22 mV to 5 mA × 1Ω =
It is reduced to 5 mV, and the base voltage of the NPN transistor 11 rises by 17 mV. Therefore, the NPN transistor 11 quickly inverts the output data Y from H level to L level.

As described above, according to the present embodiment, the output NPN transistors 10 and 11 are associated with the collector currents I _C11 and I _C10 of the NPN transistors 11 and 10, respectively, so that the base voltage rises and Since the fall is accelerated, the rise time and the fall time of the output data X and Y can be set without increasing the current of the constant current source 9, that is, without increasing the power consumption. The length can be shortened and the speed can be increased.

[0044]

As described above, according to the present invention, the output first and second transistors have their base voltages rising in relation to the collector currents of the second and first transistors, respectively. And, since it is configured to accelerate the fall, it is possible to shorten the rise time and fall time of the output signal without increasing the current of the constant current source, that is, without increasing the power consumption, The speed can be increased.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an output circuit incorporated in an embodiment of the present invention.

FIG. 2 is a layout diagram of a part of the output circuit shown in FIG.

FIG. 3 is a circuit diagram for explaining the operation of the embodiment of the present invention.

FIG. 4 is a circuit diagram for explaining the operation of the embodiment of the present invention.

FIG. 5 is a circuit diagram for explaining the operation of the embodiment of the present invention.

FIG. 6 is a circuit diagram for explaining the operation of the embodiment of the present invention.

FIG. 7 is a circuit diagram for explaining the operation of the embodiment of the present invention.

FIG. 8 is a circuit diagram for explaining the operation of the embodiment of the present invention.

FIG. 9 is a circuit diagram of an output circuit incorporated in a conventional semiconductor integrated circuit.

FIG. 10 is a layout diagram of a part of the output circuit shown in FIG.

[Explanation of symbols]

 7, 8 Load resistance 33, 34 Micro resistance

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical indication H03K 17/60

Claims (3)

[Claims] 1. A first transistor for output, which receives first data at its base and outputs first data at its emitter, and a first transistor having an opposite phase relation to said first data at its base. And a second transistor for output that outputs second data to its emitter, wherein the first transistor is associated with a collector current of the second transistor. An output configured to be accelerated in rising and falling of a base voltage, and the second transistor being configured to accelerate rising and falling of the base voltage in relation to a collector current of the first transistor. A semiconductor integrated circuit having a built-in circuit. 2. A series of a first minute resistor whose base is connected to a first input terminal to which first data is input and whose collector is connected to a first load resistor and a first power supply line. A first switch for a current switch, which is connected to the first power supply line through a circuit, and whose emitter is connected to a second power supply line which supplies a lower voltage than the first power supply line through a constant current source. A first transistor, a base of which is connected to a second input terminal to which second data having a reverse phase relationship with the first data is input, and a collector of which is connected to a second load resistor and the first power supply; A second transistor for a current switch, which is connected to the first power supply line through a series circuit of second minute resistors connected to the line, and whose emitter is connected to the emitter of the first transistor; The base is the second tiger A third transistor for output, which is connected to the collector of the transistor, which collector is connected to the connection point of the first load resistor and the first minute resistor, and whose emitter is connected to the first output terminal. And its base connected to the collector of the first transistor, its collector connected to the connection point of the second load resistor and the second minute resistor, and its emitter connected to the second output terminal. And a built-in output circuit configured to include the output fourth transistor. 3. The first and second minute resistors are the first resistor.
3. The semiconductor integrated circuit according to claim 2, wherein the wiring is branched from the power supply line.