JPH05129942A - Pll circuit - Google Patents

Abstract

PURPOSE:To regenerate a high speed clock signal with high quality in which a phase deviation is reduced from an input data signal. CONSTITUTION:An input data signal Si and frequency division clock signals Sca, Scb are fed respectively to phase comparators (A)11, (B)12, from which phase error signals Sa, Sb are outputted. Then an adder 13 adds the signals, and the oscillating frequency of a variable frequency oscillator 15 is controlled with a control voltage smoothed by a filter 14. Frequency division clock signals Sca, Scb resulting from frequency-dividing a recovered clock signal So of the variable frequency oscillator 15 are inputted respectively to the phase comparators (A)11, (B)12, in which closed loop control is implemented and the recovered clock signal So is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a PLL circuit which is used in a communication control device, a data storage device and the like to reproduce a clock signal from a data signal.

[0002]

2. Description of the Related Art In recent years, with the speeding up of data communication,
As the frequency of the clock signal increases, it is required to reduce the phase deviation of the clock signal reproduced by the communication control device.

This type of PLL circuit comprises a well-known phase comparator, a filter, a variable frequency oscillator and a frequency divider, and reproduces a clock signal from an input data signal.

FIG. 4 shows the configuration of a conventional PLL circuit. In FIG. 4, reference numeral 1 denotes a phase comparator that compares the phase of an input data signal with a divided clock and outputs a phase error signal, and is composed of an EX-OR gate circuit and the like. Reference numeral 2 is a filter that generates a control voltage by smoothing the phase error signal from the phase comparator 1, and is composed of an operational amplifier circuit or the like. Reference numeral 3 is a variable frequency oscillator whose oscillation frequency is controlled by the control voltage from the filter 2 and outputs a reproduction clock signal. Reference numeral 4 is a frequency divider which generates a division clock signal by dividing the reproduction clock signal from the variable frequency oscillator 3. Is.

Next, the operation of this configuration will be described.
The phase difference between the input data signal and the divided clock is detected by the phase comparator 1 as a phase error signal. The phase error signal is smoothed by the filter 2 and becomes a control voltage. The oscillation frequency of the variable frequency oscillator 3 is determined by this control voltage. The recovered clock from the variable frequency oscillator 3 is frequency-divided by the frequency divider 4 and fed back to the phase comparator 1 as a frequency-divided clock for closed-loop control.

Here, when the phase of the input data signal is behind the phase of the divided clock, the phase error signal output from the phase comparator 1 changes so that the phase of the divided clock is delayed. The filter 2 generates a control voltage for lowering the oscillation frequency of the variable frequency oscillator 3 and inputs it to the variable frequency oscillator 3. The frequency of the reproduced clock of the variable frequency oscillator 3 is lowered by this control voltage, and the phase of the divided clock divided by the divider 4 is delayed. The phase of the divided clock is delayed and the phase difference from the input data signal is reduced. The same applies when the divided clock signal is in phase advance with respect to the phase of the input data signal. In this way, the clock signal is reproduced by performing the closed loop control so that the phase of the input data signal matches the phase of the reproduced clock.

[0007]

However, in the PLL circuit of the conventional example, the VOH / VOL voltage of the phase comparator 1, the input offset voltage of the operational amplifier circuit constituting the filter, the fluctuation of the power supply voltage, and the stray capacitance Due to the influence, the phase deviation of the reproduced clock increases, which makes it difficult to reproduce a high-quality high-speed clock with little phase deviation.

The present invention is intended to solve such a problem, and an object thereof is to provide an excellent PLL circuit capable of reproducing a high-quality high-speed clock signal having a reduced phase deviation from an input data signal.

[0009]

In order to achieve this object, a PLL circuit of the present invention performs a phase comparison between an input data signal and an input divided clock signal and outputs a first phase error signal. A first phase comparator for performing a phase comparison between the input data signal and an input divided clock signal, and outputting a second phase error signal;
An adder that adds the first and second phase error signals, a filter that generates a control voltage that smoothes the added phase error signal, and a reproduction clock signal whose oscillation frequency is controlled by the control voltage are output. A variable frequency oscillator, a first frequency divider for generating a frequency-divided clock signal obtained by dividing the reproduced clock and supplying the divided clock signal to a first phase comparator, and a frequency-divided clock signal for dividing the reproduced clock. And a second frequency divider for supplying to the second phase comparator.

Further, the second phase comparator is characterized by being constituted by a buffer circuit having a high impedance output characteristic.

Further, the adder is characterized in that a resistor is connected to an operational amplifier circuit forming a filter.

Further, the input terminal of the divided clock signal input to the second frequency divider is connected to the output terminal of the reproduced clock signal of the variable frequency oscillator in the closest vicinity.

[0013]

With this structure, the PLL circuit of the present invention smoothes the phase error signal obtained by adding the two individual phase error signals from the first and second phase comparators, and uses the control voltage to change the variable frequency. Since the reproduction clock signal is generated by controlling the oscillation frequency of the oscillator, a high-quality high-speed clock signal with little phase deviation can be reproduced from the input data signal.

Furthermore, by connecting the input end of the reproduction clock signal input to the second frequency divider to the output end of the reproduction clock signal in the immediate vicinity, the residual phase deviation caused by the influence of the stray capacitance during mounting is eliminated. It is possible to obtain a high-speed recovered clock signal by reducing the frequency.

Further, since the adder is constructed by adding only a resistor to the operational amplifier used in the filter, the configuration can be facilitated.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of a PLL circuit of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of the embodiment. In FIG. 1, reference numeral 11 denotes a phase comparator (A) which compares the phases of the input data signal Si and the divided clock signal Sca and outputs a phase error signal Sa, which is composed of a 3-state buffer or the like. Reference numeral 12 is a phase comparator (B) that compares the phase of the input data signal Si and the divided clock signal Scb and outputs the phase error signal Sb.

Reference numeral 13 denotes a phase error signal Sa and a phase error signal S
b is an adder for adding and b is a filter for generating a control voltage by smoothing the addition phase error signal from the adder 13. Reference numeral 15 is a variable frequency oscillator whose oscillation frequency is controlled by the control voltage output from the filter 14.
Reference numeral 16 is a reproduced clock signal S from the variable frequency oscillator 15.
A frequency divider that divides o to generate a divided clock signal Sca
(A) and 17 are frequency dividers (B) for dividing the reproduced clock signal So from the variable frequency oscillator 15 to generate a divided clock signal Scb.

Next, the operation of this configuration will be described.
The phase difference between the input data signal Si and the divided clock signal Sca is output as a phase error signal Sa by the phase comparator (A) 11, and the input data signal Si and the divided clock signal Sc are also output.
The phase difference from b is the phase error signal S from the phase comparator (B) 12.
It is output as b. The phase error signal Sa and the phase error signal Sb are added by the adder 13 and smoothed by the filter 14 to become a control voltage. The oscillation frequency of the variable frequency oscillator 15 is determined by the control voltage. The reproduced clock signal So from the variable frequency oscillator 15 is frequency-divided by the frequency divider (A) 16 and fed back to the phase comparator (A) 11 as the frequency-divided clock signal Sca, and also by the frequency divider (B) 17. The frequency is divided and fed back to the phase comparator (B) 12 as the divided clock signal Scb.

If the phase of the input data signal Si is delayed from the phase of the divided clock signal Sca, the phase error signal Sa output from the phase comparator (A) 11 is the phase of the divided clock signal Sca. Changes to be delayed.
In the adder 13 and the filter 14, the variable frequency oscillator 1
A control voltage for decreasing the oscillation frequency of 5 is generated and input to the variable frequency oscillator 15. Variable frequency oscillator 15
The frequency of the reproduced clock signal So of the
(A) The phase of the divided clock signal Sca divided by 16 is delayed, and the phase difference from the input data signal Si is reduced.

Similarly, when the phase of the input data signal Si is delayed from the phase of the divided clock signal Scb, the phase error signal Sb output from the phase comparator (B) 12 has the phase of the divided clock signal Scb. Change to be delayed. In the adder 13 and the filter 14, the variable frequency oscillator 15
The control voltage for decreasing the oscillation frequency of is generated and input to the variable frequency oscillator 15. The frequency of the reproduced clock signal So from the variable frequency oscillator 15 decreases, and the frequency divider (B) 17
The phase of the divided clock signal Scb divided by is delayed,
The phase difference from the input data signal Si is reduced.

The same applies when the phase of the input data signal Si is ahead of the phases of the divided clock signals Sca and Scb.

By performing the closed loop control so that the phase of the input data signal Si and the phase of the reproduction clock signal So coincide with each other, the clock signal (reproduction clock signal So) can be reproduced.

FIG. 2 shows the detailed construction of the phase comparator (B) 12, the adder 13 and the filter 14.

In FIG. 2, 28 is the input data signal S.
It is a three-state buffer as a second phase comparator that compares the phase of i and the divided clock signal Scb. 29 is
It is a resistor for adding the phase error signal Sb output from the 3-state buffer to the phase error signal Sa.

Reference numerals 30, 31, and 32 are an operational amplifier circuit, a resistor, and a capacitor which constitute the filter 14.

The input data signal Si is input to the 3-state buffer 28 corresponding to the phase comparator (B) 12, and the 3-state buffer 28 receives the divided clock signal S.
When cb is input, the phase error signal Sb is output. The phase error signal Sb is passed through the resistor 29 to the operational amplifier circuit 3
It is input to 0 and added to the phase error signal Sa. The adder 13 and the filter 14 are composed of the same operational amplifier circuit 30.

FIG. 3 shows the signal waveform of each part in the phase comparator (b) 17. [A] shows the case where the phases of the input data signal Si and the divided clock signal Scb match, and [B] shows the case where the phase of the divided clock signal Scb lags the input data signal Si. Shows.
[C] shows the case where the phase of the divided clock signal Scb leads the input data signal Si. In the case of [A], the H (high) level period of the phase error signal Sb,
It is the same as the L (low) level period. In the case of [B], the H level period of the phase error signal Sb is longer than the L level period, and in the case of [C], the H level period of the phase error signal Sb is H.
Since the level period is shorter than the L level period, the input data signal Si and the divided clock signal Sc are compared by comparing the H level period and the L level period of the phase error signal Sb.
The phase with b can be compared. Thus, the phase comparator (A)
11 and the phase comparator (B) 12 are added to each of the two phase error signals Sa and Sb, the oscillation frequency of the variable frequency oscillator 15 is controlled by the control voltage that smooths the phase error signal, and the clock signal Since the (reproduced clock signal So) is generated, it is possible to reproduce a high-quality high-speed clock with little phase deviation. Furthermore, by connecting the input end of the reproduction clock signal input to the frequency divider (B) 17 to the output end of the reproduction clock signal So of the variable frequency oscillator 15 in the immediate vicinity, the stray capacitance due to mounting is reduced, and It is possible to obtain a high-speed recovered clock signal So with a reduced phase deviation.

The adder 13 can be easily constructed by adding resistors 31 and 29 to the operational amplifier circuit 30 of the filter 14.

[0030]

As is apparent from the above description, the PLL circuit of the present invention has a control voltage obtained by smoothing a phase error signal obtained by adding two individual phase error signals from the first and second phase comparators. Since the oscillating frequency of the variable frequency oscillator is controlled to generate the reproduced clock signal, there is an effect that a high-quality high-speed clock signal with little phase deviation can be reproduced.

Further, by connecting the input end of the reproduction clock signal input to the second frequency divider to the output end of the reproduction clock signal in the immediate vicinity, the residual phase deviation caused by the influence of stray capacitance due to mounting is reduced. Thus, it is possible to obtain a high-speed reproduced clock signal.

Further, since the adder is constructed by adding only a resistor to the operational amplifier used in the filter, there is an effect that the configuration can be made easy.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a PLL circuit of the present invention.

FIG. 2 is a circuit diagram showing a detailed configuration of a phase comparator, an adder and a filter shown in FIG.

FIG. 3 is a signal waveform diagram of each part in the phase comparator used to explain the operation of the embodiment.

FIG. 4 is a block diagram showing a configuration of a conventional PLL circuit.

[Explanation of symbols]

 11 Phase Comparator (A) 12 Phase Comparator (B) 13 Adder 14 Filter 15 Variable Frequency Oscillator 16 Divider (A) 17 Divider (B) Si Input Data Signal Sca Scb Divided Clock Signal Sa, Sb Phase error signal So recovered clock signal 29 31 resistor 30 operational amplifier circuit 32 capacitor

Claims (4)

[Claims] 1. A first phase comparator which compares the phases of an input data signal and an input divided clock signal and outputs a first phase error signal, and a divided clock which is input with the input data signal. A second phase comparator that performs a phase comparison with a signal and outputs a second phase error signal, an adder that adds the first and second phase error signals, and a smoothed phase error signal that has been added. A filter that generates a control voltage, a variable frequency oscillator that outputs a reproduction clock signal whose oscillation frequency is controlled by the control voltage, and a first phase comparator that generates a divided clock signal obtained by dividing the reproduction clock. And a second frequency divider for generating a frequency-divided clock signal obtained by frequency-dividing the reproduction clock and supplying the frequency-divided clock signal to the second phase comparator. PLL circuit. 2. The PLL circuit according to claim 1, wherein the second phase comparator is composed of a buffer circuit having a high impedance output characteristic. 3. The PLL circuit according to claim 1, wherein the adder has a configuration in which a resistor is connected to an operational amplifier circuit forming a filter. 4. The input terminal of the divided clock signal input to the second frequency divider is connected immediately to the output terminal of the reproduced clock signal of the variable frequency oscillator.
The described PLL circuit.