JPH05129960A - Cmi code transmission system - Google Patents

Abstract

PURPOSE:To send two series of CMI code signal strings through one transmission line without increasing the transmission speed. CONSTITUTION:A 1st NRZ code signal string 30 at a sender side is inputted to an NRZ/CMI conversion circuit 1, in which the string is converted into a CMI code signal string and it is sent through one cable 34. In this case, a code rule violation control circuit 3 receives 1st and 2nd NRZ code signal strings 30,32 and outputs a code rule violation signal based on dissidence information between both the signal strings to apply the code rule violation of '0' or '1' level to the CMI code signal string. A CMI/NRZ conversion circuit 2 at a receiver side converts a CHI code signal string 35 into an NRZ code signal string and recovers a 1st NRZ code signal string 37. Since a decoding circuit 6 inverts a value of the 1st NRZ code signal string 37 only when 1st and 2nd CHI code rule violation detection circuits 4,5 detect a code rule violation of '0' or '1', the 2nd NRZ code signal string is recovered.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMI code signal transmission system, and more particularly, to a single CM of two series of NRZ code signal sequences.
The present invention relates to a method of multiplexing an I code signal sequence.

FIG. 3 is a block diagram showing an example of a conventional CMI code transmission system. In FIG. 2, 1 is NRZ /
CMI conversion circuit, 2 CMI / NRZ conversion circuit, 7 N
RZ / CMI conversion circuit, 8 is a CMI / NRZ conversion circuit. On the transmission side, a 2-sequence NRZ code signal sequence 3
0 and 32 are NRZ / CMI code conversion circuits 1 and 7, respectively.
And is converted into CMI code signal sequences 33 and 42.

Normally, when converting an NRZ code signal to a CMI code signal, when the NRZ code signal is "0", the converted CMI code signal is "01" and the NRZ code signal is "1". In this case, the converted CMI code signal becomes "00" and "11" alternately. In this way, the code is converted from NRZ to CMI, and then the CMI code signal sequence 3
3, 42 are CMI / NR via cables 34, 43
Sent to the Z conversion circuits 2 and 8 to output the NRZ code signal sequence 37,
38 is played.

In the conversion from the CMI code signal to the NRZ code signal, the NRZ code signal is "1" if the 1-bit first half signal and the latter half signal of the CMI code signal are equal, and the NRZ code signal is "0" if they are not equal. It is implemented by determining that.

When converting the NRZ code signal sequence of two series into the CMI code signal sequence as described above and transmitting it,
NRZ / C is individually set on the transmitting side for each NRZ code signal sequence.
The MI conversion circuit is required, and the CMI / NRZ conversion circuit is required on the receiving side. Also, two physical transmission lines are required as a transmission line. On the other hand, if an attempt is made to transmit a CMI coded signal sequence through one transmission line, the conventional method is NRZ.
A method has been adopted in which multiplexing is performed on the time axis at the stage of a code signal, and as a result, the obtained multiplexed signal is converted into a CMI code signal and transmitted. In this case, as shown in FIG. 4, a double speed clock is required.

[0006]

The problem to be solved is to convert two NRZ code signal sequences into CMI code signal sequences and transmit the NRZ code signal sequences individually for each NRZ code signal sequence.
The point is that one transmission line is required, while the transmission speed of one transmission line requires a clock of double speed.

[0007]

According to the present invention, there is provided an NRZ / CMI conversion circuit and a CMI code rule violation control circuit on a transmission side, and a CMI code signal sequence corresponding to a first NRZ code signal sequence, and a first And the information regarding the mismatch between the second NRZ code signal sequences are multiplexed and sent to the receiving side through one transmission path, and at the receiving side, CMI / NRZ
A conversion circuit, first and second CMI coding rule violation detection circuits, and a decoding circuit are provided, and the above-mentioned information regarding the mismatch between the first NRZ code signal sequence and the second NRZ code signal sequence is used. And reproducing both signal sequences.

The NRZ / CMI conversion circuit inputs the first NRZ code signal sequence and converts it into a CMI code signal sequence. The CMI code rule violation control circuit compares the first NRZ code signal sequence and the second NRZ code signal sequence, and as a result, both do not match and the first NRZ code signal sequence is " In the case of 0 ", the CMI code signal sequence is violated by the CMI code rule of" 0 ", and the first NRZ code signal sequence and the second NRZ signal sequence do not match, and the first If the NRZ code signal sequence of is 1
A CMI code rule violation of "1" is applied to the code signal sequence.

The CMI / NRZ conversion circuit is a CMI on the receiving side.
The code signal sequence is input and the first NRZ code signal sequence is reproduced. The first CMI code rule violation detection circuit detects a CMI code rule violation of “0” from the CMI code signal sequence, and the second CM
The I code rule violation detection circuit detects a CMI code rule violation of "1" from the CMI code signal sequence. The decoding circuit is the first C
The first NRZ code signal sequence regenerated by the CMI / NRZ conversion circuit only when the CMI code rule violation is detected from one of the MI code rule violation detection circuit and the second CMI code rule violation detection circuit. Second by inverting
The NRZ code signal sequence of is reproduced.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a CMI code transmission system according to the present invention. In FIG. 1, 1 is NRZ
/ CMI conversion circuit, 2 CMI / NRZ conversion circuit, 3 CMI code rule violation control circuit, 4 first CMI code rule violation detection circuit, 5 second CMI code rule violation detection circuit, 6
Is a decoding circuit. Reference numeral 34 is a cable used as a transmission path for transmitting the CMI code signal sequences 33 and 35. FIG. 2 is a timing diagram showing an operation example of the CMI code transmission system shown in FIG.

The commonly used "1 code rule violation" means the above-mentioned "00" for the NRZ signal "1",
It violates the alternation rule with "11". That is, when the encoding of the previous NRZ signal “1” is “00”, the next NR
The Z signal “1” is encoded as “11”, but this is disturbed and changed to “00”, and when the encoding of the previous NRZ signal “1” is “11”, the next NRZ signal “1” is generated. The encoding of "is 0
Although it is "0", this is disturbed and changed to "11". In FIG.
10011001101 "is the NRZ / CMI conversion circuit 1
Is input to the second NRZ code signal sequence “0010
11100100 ”is input to the CMI coding rule violation control circuit 3.

As described above, the "1 code rule violation" or "0 code rule violation" is implemented by the output signal 36 of the CMI code rule violation control circuit 3. That is, in the CMI code rule violation control circuit 3, the first NRZ code signal sequence and the second NRZ code signal sequence are compared, and both do not match, and the first NRZ code signal sequence is "0"
In the case of, the CMI coded signal sequence converted by the NRZ / CMI conversion circuit 1 has “0 code rule violation (CR
V0) ”to implement the first NRZ code signal sequence and the second N
RZ code signal sequence does not match and the first NR
When the Z code signal sequence is “1”, “code rule violation of 1 (CRV1)” is performed on the CMI code signal sequence converted by the NRZ / CMI conversion circuit 1. In FIG. 2, from the comparison result of NRZ1 and NRZ2,
"Signal violation of 1" due to signal 36 at the 12th slot
Is being implemented.

As a result, for example, paying attention to the 9th slot, C for the "1" of the 6th slot of the NRZ signal
Since the MI code signal is code-converted to "11", the CMI code signal should be converted to "00" according to the alternating rule with respect to "1" in the ninth slot. But,
In this example, the "1 code rule violation" is executed and converted into "11". “A violation of the code rule of 0” means that the rule of “01” for the NRZ signal “0” is disturbed and converted into “10”. In FIG. 2, based on the result of comparison between NRZ1 and NRZ2, “the code rule violation of 0” is executed by the signal 36 in the 3rd and 7th slots. As a result,
The CMI code signals of the 3rd and 7th slots are disturbed and "1"
0 ". On the other hand, the first, fourth, eighth, and eleventh parts in FIG.
The code rule violation is not executed in the slot, and the CMI code signal is converted into “01” for “0” of the NRZ1 signal and transmitted. Also, in the fifth, sixth, and tenth slots, the code rule violation occurs. Not executed, the CMI code signal is alternately converted into "00" and "11" with respect to "1" of the NRZ1 signal.

Next, the overall structure will be described. First
The NRZ code signal sequence of is converted into a CMI code signal sequence by the NRZ / CMI conversion circuit 1. At this time, NRZ
The CMI code rule violation is implemented by the output signal 36 of the CMI code rule violation control circuit 3 having 1 and NRZ2 as inputs. The output of the NRZ / CMI conversion circuit 1 is sent to the receiving side as a CMI code signal sequence 33 via a cable 34. On the receiving side, the CMI code signal sequence 35 is CM
It is input to the I / NRZ conversion circuit 2 and the first and second CMI coding rule violation detection circuits 4 and 5, respectively. CMI
CMI code signal sequence 35 input to the / NRZ conversion circuit 2
Is converted into an NRZ code signal sequence, and the first NRZ code signal sequence 37 is reproduced.

As shown in FIG. 2, although the code violation is implemented on the transmitting side, the first NR is correctly received on the receiving side.
The Z code signal sequence can be obtained by comparing the 1-bit first half signal and the second half signal of the CMI code signal sequence 35 in the CMI / NRZ conversion circuit 3, and the result is "00" or "11" and both are equal. This is because if it is "1", it is "01" or "10" and if they are not equal, it is determined as "0". Signals 40 and 4 of FIG.
As is clear from 1, the first CMI coding rule violation detection circuit 4 (CRV1) detects whether or not the alternation rule of "00" and "11" for the NRZ signal "1" is disturbed, Second CMI coding rule violation detection circuit 5 (CRV
In 0), "01" for NRZ code signal "0"
It is detected whether the rule of is disturbed to "10".

In the decoding circuit 6, the signals 40 and 41 are
Only when a coding rule violation is detected from one of
The first NR reproduced by the CMI / NRZ conversion circuit 2
By inverting the Z code signal sequence 37, the second NRZ
The code signal sequence is being reproduced.

[0017]

As described above, according to the present invention, in the case of converting a two-series NRZ code signal sequence into a CMI code signal sequence and transmitting it, one of two sequences (first NRZ code signal sequence). However, the other sequences (second NRZ code signal sequence) are compared with each other and only when they do not match, "0" corresponding to the first NRZ code signal sequence is transmitted. CMI code rule violation of "or" 1
Since this information is obtained by performing it on the coded signal sequence and is multiplexed, there is an advantage that the number of transmission lines can be reduced from two to one without changing the transmission speed.

Further, according to the reception rule, the CMI code signal sequence is CM
At the same time that the I / NRZ conversion is performed to reproduce the first NRZ code signal sequence, a CMI code rule violation of "0" or "1" is detected, and only the time slot in which either CMI code rule violation is detected The second NRZ code signal sequence is reproduced by inverting the 1 NRZ code signal sequence. In this way, one NRZ / CMI is transmitted on the transmitting side.
An NRZ → CMI conversion part can be configured using a conversion circuit,
Further, on the receiving side, the CMI → NRZ conversion portion can be configured by using one CMI / NRZ conversion circuit, which has the advantage of simplifying the circuit configuration.

With respect to such a system, according to the present invention, it is not necessary to increase the transmission rate, and therefore, there is an advantage that the transmission distance is not shortened due to the deterioration of the transmission characteristics of the cable.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a CMI code transmission system according to the present invention.

FIG. 2 is a time chart showing an operation example of the CMI code transmission system of FIG.

FIG. 3 is a block diagram showing an example of a CMI code transmission system according to a conventional technique.

FIG. 4 is a time chart showing an operation example of the CMI code transmission system shown in FIG.

[Explanation of symbols]

 1,7 NRZ / CMI conversion circuit 2,8 CMI / NRZ conversion circuit 3 CMI code rule violation control circuit 4,5 CMI code rule violation detection circuit 6 Decoding circuit 30, 32, 37, 38 ANRZ code signal sequence 31, 39 , 45, clock 33, 35, 42, 44 CMI code signal sequence 34, 43 cable 36 code rule violation control circuit output signal 40, 41 code rule violation detection signal

Claims (3)

[Claims] 1. A transmitting side converts an NRZ code signal sequence into a CMI code signal sequence and sends it out on a transmission path, and a receiving side inputs the CMI code signal sequence, and receives the CMI code signal sequence from the NRZ code signal sequence. In the CMI code transmission system for reproducing the CM, the first NRZ code signal sequence is input to the transmission side and the CM is transmitted.
When the NRZ / CMI conversion circuit for converting into an I code signal sequence and the first NRZ code signal sequence and the second NRZ code signal sequence are compared, they are inconsistent and the first NRZ When the code signal string is "0", the CM
A CMI coding rule violation of "0" is performed on the I code signal sequence,
When the first NRZ coded signal sequence and the second NRZ coded signal sequence do not match and the first NRZ coded signal sequence is "1", the CMI coded signal sequence is "1". And a CMI code rule violation control circuit that implements a CMI code rule violation of ".
A CMI / NRZ conversion circuit that inputs a code signal sequence and reproduces the first NRZ code signal sequence, and a first CMI code rule violation that detects the CMI code rule violation of "0" from the CMI code signal sequence. A detection circuit, a second CMI code rule violation detection circuit for detecting the CMI code rule violation of "1" from the CMI code signal sequence, the first CMI code rule violation detection circuit, or the second CMI. Only when one of the code rule violation detection circuits detects the CMI code rule violation, the CMI /
A CMI code transmission system comprising: a decoding circuit for inverting the first NRZ code signal sequence reproduced by the NRZ conversion circuit to reproduce the second NRZ code signal sequence. 2. The CMI code transmission system according to claim 1, wherein said transmission line is composed of one cable. 3. The implementation of the code rule violation of "1" is NRZ.
When the CMI coded signal of the coded signal “1” is “00”, the next NRZ coded signal “1” is coded as “00”,
In the case of "11", the encoding of the next NRZ code signal "1" is set to "11", and the code rule violation of "0" is performed by the NRZ code signal "0".
2. The CMI code transmission system according to claim 1, wherein the CMI code rule violation control circuit is configured so as to be "10" when the CMI code signal of is "01".