JPH05130077A - Parity check system between integrated circuits - Google Patents

Abstract

(57) [Abstract] [Purpose] To reduce the number of signal lines between integrated circuits. [Structure] The parity generate circuit 10 of the LSI 1 is an inter-LSI signal output 10 sent from the LSI 2 to the LSI 1.
0 and inter-LSI signal output sent from LSI1 to LSI2
The parity information 102 of the inter-LSI signal outputs 100 and 101 is generated by 101. The parity check circuit 20 of the LSI 2 uses the inter-LSI signal output 100 sent from the LSI 2 to the LSI 1, the inter-LSI signal output 101 sent from the LSI 1 to the LSI 2, and the parity information 102 sent from the parity generate circuit 10. Signal output
Parity check of 100 and 101 is performed and parity error signal 103 is output.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inter-integrated circuit parity check system, and more particularly to a parity check system for signals transmitted and received between LSIs (large scale integrated circuits).

[0002]

2. Description of the Related Art Conventionally, in this type of parity check method, an LS that outputs from one LSI to the other LSI.
Parity is given to each of the inter-I signal and the inter-LSI signal input from the other LSI to the one LSI, and the parity check of the inter-LSI signal is performed in each of the one LSI and the other LSI.

In such a conventional parity check method for inter-LSI signals, inter-LSI signals output from one LSI to the other LSI and one LSI from the other LSI.
Since the parity is added to each of the inter-LSI signals input to, there is a drawback that the number of signal lines between the LSIs increases by the parity.

[0004]

SUMMARY OF THE INVENTION The present invention has been made to eliminate the above-mentioned drawbacks of the conventional ones, and an object thereof is to provide an inter-integrated-circuit parity check system capable of reducing the number of signal lines between the integrated circuits. ..

[0005]

The inter-integrated-circuit parity check system according to the present invention is provided in the first integrated circuit, and outputs the first signal output from the first integrated circuit to the second integrated circuit and the second integrated circuit. Generating means for generating parity information of the first and second signals from a second signal input from the circuit to the first integrated circuit; and a generating means provided in the second integrated circuit. And a means for performing a parity check on the first and second signals from the generated parity information and the first and second signals.

[0006]

An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, the parity generate circuit 10 of the LSI1 is the L sent from the LSI2 to the LSI1.
The inter-LSI signal output 100 is achieved by the inter-SI signal output 100 and the inter-LSI signal output 101 sent from the LSI 1 to the LSI 2.
, 101 of parity information 102 is generated.

That is, the parity generate circuit 10
Signal output 100 between LSIs is "1", signal output between LSIs
When 101 is "1", "1" is generated as the parity information 102, the inter-LSI signal output 100 is "0", and when the inter-LSI signal output 101 is "1", the parity information 102 is "0". To generate.

The parity generate circuit 10 is L
SI signal output 100 is "1", LSI signal output 101
Is "0", "0" is generated as the parity information 102, the inter-LSI signal output 100 is "0", and the inter-LSI signal output 101 is "0", the parity information 102 is "1".
To generate.

The parity check circuit 20 of the LSI 2 is L
Inter-LSI signal output 100 sent from SI2 to LSI1
And the inter-LSI signal output 100 sent from the LSI 1 to the LSI 2 and the parity information 102 sent from the parity generate circuit 10
Performs 101 parity check and returns parity error signal 10
Outputs 3.

That is, the parity check circuit 20 is L
Parity information is generated by the SI-to-SI signal output 100 and the LSI-to-LSI signal output 101, and the parity information is compared with the parity information 102 from the parity generate circuit 10 to perform the parity check of the LSI-to-LSI signal outputs 100 and 101. , A parity error signal 103 is output when the mismatches are detected.

Therefore, the inter-LSI signal output 100 is "1".
Then, the inter-LSI signal output 101 is “1” and the parity information 10
If 2 is “1”, the parity check circuit 20 outputs “0” as the parity error signal 103, and the LSI
If the inter-signal output 100 is "0", the inter-LSI signal output 101 is "1", and the parity information 102 is "0", the parity check circuit 20 outputs "0" as the parity error signal 103.

Further, the signal output 100 between LSIs is "1",
If the inter-LSI signal output 101 is “0” and the parity information 102 is “0”, the parity check circuit 20 outputs “0” as the parity error signal 103, and the inter-LSI signal output 100 is “0”, Signal output 101 between LSIs is "0"
If the parity information 102 is "1", the parity check circuit 20 outputs "0" as the parity error signal 103.
Is output.

Signal output between LSI 100 and signal output between LSI
If the combination of 101 and parity information 102 is other than the above, the parity check circuit 20 outputs the parity error signal.
"1" is output as 103, and a parity error is detected.

Here, the inter-LSI signal output 100 is "1".
Then, when the inter-LSI signal output 101 is “0”, the place where the parity generate circuit 10 should generate “0” as the parity information 102 is that a transmission error occurs between the LSI 1 and the inter-LSI signal output 100. The case where "1" is generated as the parity information 102 because "0" is input as will be described below.

In this case, "1" is output as the inter-LSI signal output 100 to the parity check circuit 20 of the LSI 2 by LS.
Since "0" is input as the I-to-I signal output 101, "0" is generated as the parity information. On the other hand, since "1" is input from the parity generate circuit 10 to the parity check circuit 20 as the parity information 102, the parity check circuit 20 detects a mismatch of the parity information and outputs "1" as the parity error signal 103. Is output. Therefore, it is possible to detect a transmission error between the LSIs 1 and 2.

Thus, the parity information 102 between the LSI signal outputs 100 and 101 in the parity generate circuit 10 is generated by the inter-LSI signal output 100 sent from the LSI2 to the LSI1 and the inter-LSI signal output 101 sent from the LSI1 to the LSI2. To generate the parity generation circuit 10
The parity check circuit 20 performs the parity check of the inter-LSI signal outputs 100 and 101 by the parity information 102 generated in step 1 and the inter-LSI signal outputs 100 and 101, so that the LSI transmitted from the LSI2 to the LSI1. It is possible to detect a transmission error between the LSIs 1 and 2 without adding parity to the inter-signal output 100. Therefore, the parity given to the inter-LSI signal output 100 sent from the LSI2 to the LSI1 becomes unnecessary, and the LSI1,
The number of signal lines between the two can be reduced.

[0018]

As described above, according to the present invention, the first signal output from the first integrated circuit to the second integrated circuit and the second signal input from the second integrated circuit to the first integrated circuit. Second
The first integrated circuit is provided with a generation circuit that generates parity information of the first and second signals from the first signal and the second information, and the first and second signals are generated from the parity information generated by the generation circuit and the first and second signals. By providing the circuit for performing the parity check of the two signals in the second integrated circuit, it is possible to reduce the number of signal lines between the first and second integrated circuits.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

[Explanation of symbols]

 1, 2 LSI 10 Parity generate circuit 20 Parity check circuit

Claims (1)

[Claims] 1. A first signal which is provided in a first integrated circuit and which is output from the first integrated circuit to a second integrated circuit and which is input from the second integrated circuit to the first integrated circuit. Generating means for generating parity information of the first and second signals from the second signal, and the parity information generated by the generating means and provided for the second integrated circuit, and the first and second signals. An inter-integrated-circuit parity check system comprising: a second signal; and means for performing a parity check on the first and second signals.