JPH05136143A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof

Info

Publication number
JPH05136143A
JPH05136143A JP4080625A JP8062592A JPH05136143A JP H05136143 A JPH05136143 A JP H05136143A JP 4080625 A JP4080625 A JP 4080625A JP 8062592 A JP8062592 A JP 8062592A JP H05136143 A JPH05136143 A JP H05136143A
Authority
JP
Japan
Prior art keywords
semiconductor element
electrode
bonding
plating
alloy layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4080625A
Other languages
Japanese (ja)
Other versions
JP3173109B2 (en
Inventor
Yasuyuki Baba
康行 馬場
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
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Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP08062592A priority Critical patent/JP3173109B2/en
Publication of JPH05136143A publication Critical patent/JPH05136143A/en
Application granted granted Critical
Publication of JP3173109B2 publication Critical patent/JP3173109B2/en
Anticipated expiration legal-status Critical
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Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/012Manufacture or treatment of bump connectors, dummy bumps or thermal bumps

Landscapes

  • Wire Bonding (AREA)

Abstract

(57)【要約】 【目的】 ファインピッチで多数の出力ピンを有する半
導体素子と、回路基板の電極とを簡単に電極間のショー
トもなく、高い信頼性で実装できる半導体素子を提供す
ることを目的とする。 【構成】 半導体素子5の電極部1にメッキによりAu
もしくはAgを主成分とする突起電極6を形成し、さら
に前記突起電極6の半導体素子と反対側に融点の低い接
合用合金層7をメッキにより設け、前記半導体素子と回
路基板の電極9の接続時には、その両者を接触させた状
態で前記接合用合金層を溶融して接合するように構成し
た。
(57) [Abstract] [Purpose] To provide a semiconductor element in which a semiconductor element having a large number of output pins at a fine pitch and an electrode of a circuit board can be easily mounted with high reliability without a short circuit between the electrodes. To aim. [Structure] The electrode portion 1 of the semiconductor element 5 is plated with Au.
Alternatively, a bump electrode 6 containing Ag as a main component is formed, and a bonding alloy layer 7 having a low melting point is provided on the opposite side of the bump electrode 6 from the semiconductor element by plating to connect the semiconductor element and the electrode 9 of the circuit board. At times, the alloy layer for bonding was melted and bonded in a state in which the both were in contact with each other.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はファインピッチな電極を
有する半導体素子と、回路基板の電極を簡単にかつ高信
頼性に接合できる半導体素子及びその製造方法に関する
ものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element having fine pitch electrodes and a semiconductor element capable of easily and reliably joining electrodes on a circuit board and a method of manufacturing the same.

【0002】[0002]

【従来の技術】近年、電子回路のデジタル化に伴い、狭
ピッチで多ピンの半導体が多く回路基板に搭載されるよ
うになってきた。このため、半導体実装技術が機器の小
型化に重要な影響をもつようになってきている。従来の
半導体実装方法としては、ワイヤーボンディング,TA
B,フリップチップ等があるが実装密度の最も高いフリ
ップチップ実装法が注目されている。一般によく知られ
ているフリップチップ実装法には、半田バンプ法とスタ
ッドバンプ法があるが、いずれの場合にも半導体素子の
電極の大きさが80μm以上必要であるのが現状であ
る。
2. Description of the Related Art In recent years, with the digitization of electronic circuits, many semiconductors having a narrow pitch and a large number of pins have been mounted on a circuit board. For this reason, the semiconductor mounting technology has come to have an important influence on the miniaturization of devices. Conventional semiconductor mounting methods include wire bonding, TA
B, flip chip, etc. are available, but the flip chip mounting method with the highest mounting density is drawing attention. Generally well-known flip chip mounting methods include a solder bump method and a stud bump method, but in any case, the size of the electrode of the semiconductor element is required to be 80 μm or more.

【0003】半田バンプ法とは図4に示す如く半導体素
子5の電極1上にCrやTi等のバリヤーメタル層2が
形成され、さらにその上に半田ボール3が配置されてい
るもので、回路基板との接続はこの半田ボール3を溶融
して接続される。次にスタッドバンプ法とは、図5に示
す如く半導体素子5の電極1の上に従来のワイヤーボン
ディングと同じ方式でAuのボールバンプ4を形成し突
起電極とする方法である。この場合回路基板との接続
は、回路基板の電極上にスクリーン印刷もしくはメタル
マスク印刷で熱硬化性のAgペーストもしくは半田クリ
ーム層を形成し、上記Auバンプ4のついた半導体素子
をマウントし、加熱することにより接続する。
The solder bump method is a method in which a barrier metal layer 2 of Cr, Ti or the like is formed on an electrode 1 of a semiconductor element 5 as shown in FIG. 4, and a solder ball 3 is arranged on the barrier metal layer 2. The connection with the substrate is made by melting the solder balls 3. Next, the stud bump method is a method in which Au ball bumps 4 are formed on the electrodes 1 of the semiconductor element 5 as shown in FIG. In this case, the connection with the circuit board is performed by forming a thermosetting Ag paste or solder cream layer on the electrodes of the circuit board by screen printing or metal mask printing, mounting the semiconductor element with the Au bumps 4, and heating. To connect.

【0004】[0004]

【発明が解決しようとする課題】しかしながら従来の構
成では、半田バンプの場合バリヤーメタル層2を形成す
るためにスパッタリング,フォトリソ,エッチング工程
を繰り返さなければならず、コストが高くつき、かつ歩
留まりも悪いという欠点も有していた。また、半田バン
プは半田ボール3を溶融して形成するが、均一な大きさ
の半田ボールの製造は不可能でバンプ高さのばらつきが
大きいという欠点を有している。スタッドバンプ方式に
ついては、低コストで簡単な方法であるが、ワイヤーボ
ンドのボールボンディングの大きさは70〜80μmφ
が最少で、今後半導体素子の電極の大きさが40μm〜
60μm角になってくるといわれており、スタッドバン
プでは対応がとれなくなってしまう。また、回路基板と
接続するため回路基板側にメタルマスクを用いてAgペ
ーストや半田を印刷しなければならないが、現状では電
極間ピッチ160μmが限界である。また、半田印刷の
場合半田ボールが電極と電極の間に付着しやすく、信頼
性を損ねてしまうという問題点も有していた。現在ビデ
オカメラ等に使用されているICのピンピッチは500
μmのものが最少であるが、それでも半田付けの歩留ま
りが悪いことを考えると、160μmピッチの困難さは
容易に推察できる。
However, in the case of the conventional structure, in the case of the solder bump, the sputtering, photolithography and etching steps must be repeated to form the barrier metal layer 2, resulting in high cost and poor yield. It also had the drawback. Further, the solder bump is formed by melting the solder ball 3, but it has a drawback that it is impossible to manufacture a solder ball having a uniform size and the bump height varies greatly. The stud bump method is a low cost and simple method, but the size of ball bonding of wire bond is 70 to 80 μmφ.
Is the smallest, and the size of the electrodes of semiconductor elements will be 40 μm ~
It is said that the size will be 60 μm square, and stud bumps will not be compatible. Further, in order to connect with the circuit board, Ag paste or solder must be printed on the circuit board side using a metal mask, but at present, the electrode pitch is 160 μm. Further, in the case of solder printing, there is a problem that solder balls are easily attached between the electrodes and the reliability is deteriorated. The pin pitch of ICs currently used in video cameras is 500
Although the thickness of μm is the smallest, the difficulty of 160 μm pitch can be easily inferred considering that the yield of soldering is still poor.

【0005】本発明は上記従来の問題点を解決するもの
で、ファインピッチな電極を有する半導体素子の電極と
回路基板の電極を、簡単にかつ高信頼性に接合できる半
導体素子及びその製造方法を提供することを目的とす
る。
The present invention solves the above-mentioned conventional problems, and provides a semiconductor element and a method of manufacturing the same, which can easily and reliably join the electrodes of a semiconductor element having fine pitch electrodes and the electrodes of a circuit board. The purpose is to provide.

【0006】[0006]

【課題を解決するための手段】この目的を達成するため
に本発明の半導体素子は、半導体素子の電極部にメッキ
されたAuもしくはAgを主成分とする突起電極を有
し、さらに前記突起電極の半導体素子と反対側の表面に
メッキにより形成された融点が前記突起電極及び回路基
板の電極より低い接合用合金層が配置されている。
In order to achieve this object, a semiconductor device of the present invention has a protruding electrode containing Au or Ag as a main component, which is plated on an electrode portion of the semiconductor device. On the surface opposite to the semiconductor element, a bonding alloy layer having a melting point lower than that of the protruding electrodes and the electrodes of the circuit board is formed by plating.

【0007】[0007]

【作用】この構成によって、半導体素子の電極部にメッ
キされた突起電極を有しているため、ファインピッチな
電極にも十分対応でき、また、回路基板と半導体素子と
の接続においても、前記電極部に予めメッキで接合剤が
形成されているため、突起電極の断面積と接合材の断面
積を等しくできるので、非常に高精度な接続が可能とな
り、信頼性も著しく向上するものである。
With this configuration, since the electrode portion of the semiconductor element has the protruding electrode plated, it is possible to sufficiently cope with fine-pitch electrodes, and also in the connection between the circuit board and the semiconductor element, the electrode Since the bonding agent is formed in advance on the portion by plating, the cross-sectional area of the protruding electrode and the cross-sectional area of the bonding material can be made equal to each other, so that highly accurate connection is possible and reliability is remarkably improved.

【0008】[0008]

【実施例】(実施例1)以下本発明の一実施例について
図面を参照しながら説明する。
Embodiment 1 An embodiment of the present invention will be described below with reference to the drawings.

【0009】先ず図2(a)に示す如く、ガラス基板8
上に導電体、たとえば透明電極ITO層9を蒸着した基
板に、乾燥後の厚みが30〜50μmとなるようにフォ
トレジスト10を塗布し、完成された半導体素子の電極
部の位置に相当する部分に約50μmφの穴11をあけ
る。次に、基板8ごとメッキ液に浸し、透明電極ITO
層9に電気を流し、図2(b)に示すように、前記穴1
1内に接合用合金層7そして突起電極6を形成する。今
回実験した接合用合金層7の金属合金組成を(表1)に
示す。
First, as shown in FIG. 2A, the glass substrate 8
A portion corresponding to the position of the electrode portion of the completed semiconductor element is obtained by applying a photoresist 10 onto a substrate on which an electric conductor, for example, a transparent electrode ITO layer 9 is vapor-deposited, so that the thickness after drying is 30 to 50 μm. Drill a hole 11 of about 50 μmφ. Next, the entire substrate 8 is immersed in a plating solution to form a transparent electrode ITO.
Electricity is applied to the layer 9 and, as shown in FIG.
An alloy layer 7 for bonding and a protruding electrode 6 are formed in 1. The metal alloy composition of the joining alloy layer 7 tested this time is shown in (Table 1).

【0010】[0010]

【表1】 [Table 1]

【0011】この接合用合金層7の融点は、前記突起電
極6の融点及び接合すべき回路基板の電極の融点より低
く、望ましくは現在のリフロー用炉が使用できる温度
(260℃)以下に設定されている。次に突起電極6に
ついては、AuもしくはAgを主成分とした電気メッキ
で形成した。この時の各突起電極のメッキ厚みは±3μ
m以内に制御できることがわかった。次にフォトレジス
ト10をエッチング液で除去した後、図3に示す如く、
ガラス基板8上にメッキで形成された突起電極6に対向
して半導体素子5を配置し、半導体素子の電極1と突起
電極6を熱圧着させる。この時、ITO層9と接合用合
金層7との接合強度に比べ、電極1と突起電極6との接
合強度を強くしておく。一般に、ITOは金属との密着
性が悪い為に、このことは容易に達成できる。しかる後
にガラス基板8から半導体素子5を引き離すと、図1に
示す如く突起電極6と接合用合金層7は半導体素子5の
方に転写される。この半導体素子を接合用合金層7を介
して、接続すべき回路基板と接触させ窒素中で230℃
ピークのリフローに通すと、接合用合金層7が溶融して
突起電極間でのショートもなく100μmの高精度なピ
ッチで回路基板に接合することができた。
The melting point of the bonding alloy layer 7 is lower than the melting points of the protruding electrodes 6 and the electrodes of the circuit board to be bonded, and is preferably set to a temperature (260 ° C.) or lower at which the current reflow furnace can be used. Has been done. Next, the bump electrode 6 was formed by electroplating containing Au or Ag as a main component. At this time, the plating thickness of each protruding electrode is ± 3μ
It turned out that it can be controlled within m. Next, after removing the photoresist 10 with an etching solution, as shown in FIG.
The semiconductor element 5 is arranged so as to face the protruding electrode 6 formed by plating on the glass substrate 8, and the electrode 1 of the semiconductor element and the protruding electrode 6 are thermocompression bonded. At this time, the bonding strength between the electrode 1 and the protruding electrode 6 is set to be stronger than the bonding strength between the ITO layer 9 and the bonding alloy layer 7. This is easily achievable because ITO generally has poor adhesion to metals. Then, when the semiconductor element 5 is separated from the glass substrate 8, the protruding electrode 6 and the bonding alloy layer 7 are transferred to the semiconductor element 5 as shown in FIG. This semiconductor element is brought into contact with the circuit board to be connected through the bonding alloy layer 7 and the temperature is set to 230 ° C. in nitrogen.
When passing through the peak reflow, the joining alloy layer 7 was melted and it was possible to join to the circuit board at a highly accurate pitch of 100 μm without a short circuit between the protruding electrodes.

【0012】(実施例2)次に本発明の第2の実施例に
ついて説明する。本実施例が上記実施例1と相違すると
ころは、図2(a)に示すようにガラス基板8上に形成
したフォトレジスト10に穴11をあけた後に、まず図
5に示す如く、基板8ごとメッキ液に浸し、透明電極I
TO層9に電気を流し、前記穴11内にAuメッキ層1
2、接合用合金層7そして突起電極6を形成することで
ある。今回実験した接合用合金層7の金属合金組成は上
記(表1)に示すものと同様であり、突起電極6につい
てもAuもしくはAgを主成分とした電気メッキで形成
した。この時の各突起電極のメッキ厚みは±3μm以内
に制御できることがわかった。
(Second Embodiment) Next, a second embodiment of the present invention will be described. The present embodiment is different from the above-described first embodiment in that after a hole 11 is formed in a photoresist 10 formed on a glass substrate 8 as shown in FIG. 2A, first, as shown in FIG. Immerse all in plating solution
Electricity is applied to the TO layer 9 and the Au plating layer 1 is placed in the hole 11.
2. Forming the bonding alloy layer 7 and the protruding electrode 6. The metal alloy composition of the joining alloy layer 7 tested this time is the same as that shown in the above (Table 1), and the bump electrode 6 was also formed by electroplating containing Au or Ag as a main component. It was found that the plating thickness of each protruding electrode at this time can be controlled within ± 3 μm.

【0013】次にフォトレジスト10をエッチング液で
除去した後、図6に示す如く、ガラス基板8上にメッキ
で形成された突起電極6に対向して半導体素子5を配置
し、半導体素子の電極1と突起電極6を熱圧着させる。
この時、ITO層9とAuメッキ層12との接合強度に
比べ、電極1と突起電極6との接合強度を強くしてお
く。一般に、ITOは金属との密着性が悪い為に、この
ことは容易に達成できる。しかる後にガラス基板8から
半導体素子5を引き離すと、図4に示す如く突起電極
6、接合用合金層7、Auメッキ層12は半導体素子5
の方に転写される。
Next, after removing the photoresist 10 with an etching solution, as shown in FIG. 6, the semiconductor element 5 is arranged so as to face the protruding electrode 6 formed by plating on the glass substrate 8, and the electrode of the semiconductor element is arranged. 1 and the protruding electrode 6 are thermocompression bonded.
At this time, the bonding strength between the electrode 1 and the bump electrode 6 is set to be stronger than the bonding strength between the ITO layer 9 and the Au plating layer 12. This is easily achievable because ITO generally has poor adhesion to metals. Then, when the semiconductor element 5 is separated from the glass substrate 8, the protruding electrode 6, the bonding alloy layer 7, and the Au plating layer 12 are removed from the semiconductor element 5 as shown in FIG.
Will be transcribed.

【0014】この半導体素子5をAuメッキ層12を介
して、接続すべき回路基板と接触させ窒素中で230℃
ピークのリフローに通すと、接合用合金層7が溶融して
Auメッキ層12は接続用合金層7に拡散するので、突
起電極6間でのショートもなく100μmの高精度なピ
ッチで回路基板に接合することができた。
The semiconductor element 5 is brought into contact with the circuit board to be connected via the Au plating layer 12 and the temperature is 230 ° C. in nitrogen.
When passing through the peak reflow, the bonding alloy layer 7 melts and the Au plating layer 12 diffuses into the connecting alloy layer 7, so that there is no short circuit between the protruding electrodes 6 and the circuit board is formed on the circuit board at a highly accurate pitch of 100 μm. I was able to join.

【0015】本実施例においては、穴11内にAuメッ
キ層12を形成した後に接合用合金層7を形成するの
で、上記実施例1のAuメッキ層12を形成しないもの
に比べて、接合用合金層7のメッキが均一に成長する。
このため回路基板と接続するときの歩留まりは、上記実
施例1のときと比べて著しく向上した。
In the present embodiment, since the bonding alloy layer 7 is formed after the Au plating layer 12 is formed in the hole 11, the bonding alloy layer 7 is formed as compared with the case where the Au plating layer 12 is not formed in the first embodiment. The plating of the alloy layer 7 grows uniformly.
Therefore, the yield when connecting to the circuit board was remarkably improved as compared with the case of the first embodiment.

【0016】[0016]

【発明の効果】以上のように本発明は、半導体素子の電
極部にメッキで形成されたAuもしくはAgを主成分と
する突起電極を有し、さらに前記突起電極の半導体素子
と反対側に、低融点の接合用合金層が配置されているた
め、ファインピッチな半導体素子の電極と回路基板の電
極を簡単にかつ高い信頼性で接合できる、優れた実装方
法を実現できるものである。
As described above, according to the present invention, the electrode portion of the semiconductor element is provided with the protruding electrode containing Au or Ag as a main component, and the protruding electrode is provided on the side opposite to the semiconductor element. Since the low melting point bonding alloy layer is arranged, an excellent mounting method can be realized in which the electrodes of the fine pitch semiconductor element and the electrodes of the circuit board can be bonded easily and with high reliability.

【0017】また半導体素子の電極部上にメッキで形成
したAuもしくはAgを主成分とする突起電極を有し、
さらにその上部に低融点の接合用合金層及びAuメッキ
層を配置しているため、ファインピッチな半導体素子の
電極と回路基板の電極とを、簡単にかつさらに高い信頼
性で接合できる、優れた実装方法を実現できるものであ
る。
In addition, there is a protruding electrode containing Au or Ag as a main component formed by plating on the electrode portion of the semiconductor element,
Further, since the low melting point bonding alloy layer and the Au plating layer are arranged on the upper portion thereof, the electrodes of the fine pitch semiconductor element and the electrodes of the circuit board can be bonded easily and with high reliability, which is excellent. The implementation method can be realized.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例に於ける半導体素子の断
面図
FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention.

【図2】(a),(b)はそれぞれ本発明の半導体素子
の製造方法の第1の実施例における異なる製造方法を示
す断面図
2A and 2B are cross-sectional views showing different manufacturing methods in the first embodiment of the method for manufacturing a semiconductor device of the present invention.

【図3】同実施例のさらに異なる工程を示す断面図FIG. 3 is a sectional view showing a further different step of the same example.

【図4】本発明の第2の実施例に於ける半導体素子の断
面図
FIG. 4 is a sectional view of a semiconductor device according to a second embodiment of the present invention.

【図5】本発明の半導体素子の製造方法の第2の実施例
における製造方法を示す断面図
FIG. 5 is a cross-sectional view showing a manufacturing method in a second embodiment of the method for manufacturing a semiconductor device of the present invention.

【図6】同実施例のさらに異なる工程を示す断面図FIG. 6 is a cross-sectional view showing still another step of the same embodiment.

【図7】半導体素子に突起電極が形成された従来の一例
を示す断面図
FIG. 7 is a cross-sectional view showing a conventional example in which a protruding electrode is formed on a semiconductor element.

【図8】半導体素子に突起電極が形成された従来の一例
を示す断面図
FIG. 8 is a cross-sectional view showing a conventional example in which a protruding electrode is formed on a semiconductor element.

【符号の説明】[Explanation of symbols]

1 半導体素子の電極 2 バリヤーメタル層 3 半田ボール 4 Auのボールバンプ 5 半導体素子 6 突起電極 7 接合用合金層 8 ガラス基板 9 ITO 10 フォトレジスト 12 Auメッキ層 DESCRIPTION OF SYMBOLS 1 Semiconductor element electrode 2 Barrier metal layer 3 Solder ball 4 Au ball bump 5 Semiconductor element 6 Projection electrode 7 Bonding alloy layer 8 Glass substrate 9 ITO 10 Photoresist 12 Au plating layer

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】半導体素子の電極部にメッキで形成された
AuもしくはAgを主成分とする突起電極を有し、前記
突起電極の半導体素子と反対側の表面にメッキにより形
成された融点が前記突起電極及び回路基板の電極より低
い接合用合金層が配置されていることを特徴とする半導
体素子。
1. A semiconductor element having a projection electrode mainly composed of Au or Ag formed by plating on an electrode portion of the semiconductor element, and a melting point formed by plating on a surface of the projection electrode opposite to the semiconductor element has the above-mentioned melting point. A semiconductor element having a bonding alloy layer disposed lower than the protruding electrodes and the electrodes of the circuit board.
【請求項2】基板上にフォトレジストを塗布し、そのフ
ォトレジストの所定の半導体素子の電極に対応する位置
に穴を設け、その穴内に接合用合金層とその接合用合金
層上にAuもしくはAgを主成分とする突起電極をそれ
ぞれメッキで形成し、しかる後に前記フォトレジストを
除去した後に前記半導体素子の電極と前記突起電極を重
ね合わせ加熱及び加圧して接合し、その接合後に前記基
板と前記接合用合金層の接合を分離することを特徴とす
る半導体素子の製造方法。
2. A photoresist is applied on a substrate, a hole is formed in the photoresist at a position corresponding to an electrode of a predetermined semiconductor element, and a bonding alloy layer and Au or Au on the bonding alloy layer are provided in the hole. Protruding electrodes containing Ag as a main component are formed by plating respectively, and then the photoresist is removed, and then the electrodes of the semiconductor element and the protruding electrodes are superposed and joined by heating and pressurizing, and after the joining, the substrate is formed. A method for manufacturing a semiconductor device, characterized in that the bonding of the bonding alloy layer is separated.
【請求項3】半導体素子の電極部にメッキで形成された
AuもしくはAgを主成分とする突起電極を有し、前記
突起電極上にメッキにより形成された融点が前記突起電
極及び回路基板の電極より低い接合用合金層が配置さ
れ、さらに前記接合用合金層の表面にはAuメッキ層が
配置されていることを特徴とする半導体素子。
3. A semiconductor element having a projection electrode formed by plating and having Au or Ag as a main component, and a melting point formed by plating on the projection electrode and an electrode of a circuit board. A semiconductor element, wherein a lower bonding alloy layer is disposed, and further, an Au plating layer is disposed on the surface of the bonding alloy layer.
【請求項4】基板上にフォトレジストを塗布し、そのフ
ォトレジストの所定の半導体素子の電極に対応する位置
に穴を設け、その穴内に先ずAuメッキ層を形成し、そ
の上に接合用合金層とその接合用合金層上にAuもしく
はAgを主成分とする突起電極をそれぞれメッキで形成
し、しかる後に前記フォトレジストを除去した後に前記
半導体素子の電極と前記突起電極を重ね合わせ加熱及び
加圧して接合し、その接合後に前記基板と前記接合用合
金層の接合を分離することを特徴とする半導体素子の製
造方法。
4. A photoresist is applied on a substrate, a hole is formed in the photoresist at a position corresponding to an electrode of a predetermined semiconductor element, an Au plating layer is first formed in the hole, and a bonding alloy is formed thereon. Protruding electrodes containing Au or Ag as a main component are respectively formed on the layer and the bonding alloy layer by plating, and after removing the photoresist, the electrodes of the semiconductor element and the protruding electrodes are superposed and heated and heated. A method of manufacturing a semiconductor element, comprising: pressing and bonding, and separating the bonding between the substrate and the bonding alloy layer after the bonding.
JP08062592A 1991-09-19 1992-04-02 Semiconductor device and manufacturing method thereof Expired - Fee Related JP3173109B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP08062592A JP3173109B2 (en) 1991-09-19 1992-04-02 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP3-239219 1991-09-19
JP23921991 1991-09-19
JP08062592A JP3173109B2 (en) 1991-09-19 1992-04-02 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPH05136143A true JPH05136143A (en) 1993-06-01
JP3173109B2 JP3173109B2 (en) 2001-06-04

Family

ID=26421621

Family Applications (1)

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Country Status (1)

Country Link
JP (1) JP3173109B2 (en)

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* Cited by examiner, † Cited by third party
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JP2008547207A (en) * 2005-06-14 2008-12-25 キュービック・ウエハ・インコーポレーテッド Electronic chip contact structure
WO2013153578A1 (en) * 2012-04-12 2013-10-17 株式会社Leap Method for manufacturing electroformed component
US8846445B2 (en) 2005-06-14 2014-09-30 Cufer Asset Ltd. L.L.C. Inverse chip connector

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008547207A (en) * 2005-06-14 2008-12-25 キュービック・ウエハ・インコーポレーテッド Electronic chip contact structure
US8846445B2 (en) 2005-06-14 2014-09-30 Cufer Asset Ltd. L.L.C. Inverse chip connector
US9147635B2 (en) 2005-06-14 2015-09-29 Cufer Asset Ltd. L.L.C. Contact-based encapsulation
US9324629B2 (en) 2005-06-14 2016-04-26 Cufer Asset Ltd. L.L.C. Tooling for coupling multiple electronic chips
US9754907B2 (en) 2005-06-14 2017-09-05 Cufer Asset Ltd. L.L.C. Tooling for coupling multiple electronic chips
US10340239B2 (en) 2005-06-14 2019-07-02 Cufer Asset Ltd. L.L.C Tooling for coupling multiple electronic chips
WO2013153578A1 (en) * 2012-04-12 2013-10-17 株式会社Leap Method for manufacturing electroformed component

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