JPH05136830A - Linear transmission circuit - Google Patents

Abstract

(57) [Summary] [Object] The present invention relates to a linear transmission circuit that makes a drain voltage applied to an output stage FET amplifier circuit variable according to voltage control data, and is accurate for any FET amplifier circuit of any characteristics. It is an object of the present invention to provide a linear transmission circuit which can provide various voltage control data, can perform temperature compensation of the data, and can be easily integrated into an LSI as a whole. A pseudo envelope data SE proportional to the envelope of the quadrature amplitude modulation output is generated based on the transmission signals I (t) and Q (t), and the voltage control data RD of the RAM 500 is read with this data SE. FE with this data RD
The drain voltage V _DD applied to the T amplifier circuit 200 is controlled. On the other hand, the pseudo envelope data SE and the output signal O
The difference from the envelope data detected from (t) is obtained, and the voltage control data R of the RAM 500 is calculated according to the difference.
Data WD in which D is corrected is obtained, and this is written in the address indicated by the pseudo envelope data SE of the RAM 500.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a linear transmission circuit, and more particularly to a linear transmission circuit which makes a drain voltage applied to an FET amplifier circuit at an output stage variable according to envelope fluctuation of a transmission signal.

In mobile radio devices such as mobile phones, it is nowadays necessary to carry out power amplification with high efficiency at the output stage because they must be operated by batteries.

[0003]

2. Description of the Related Art FIG. 6 is a circuit diagram of a conventional linear transmission circuit.
In the figure, 1 is a transmission baseband signal I whose cutoff frequency is roll-off shaped or root-rolled-off shaped.
(T) and Q (t) by quadrature amplitude modulation of the carrier signal cos .omega _c t and sinω _c t (QAM) is Quadrature Amplitude Modulation circuit, 2 is the output modulated signal of the quadrature amplitude modulation circuit 1 M
Variable attenuator for attenuating (t) according to an error signal DE described later, 3 is an FET amplifier circuit for amplifying the output signal M (t) 'of the variable attenuator 2, and 4 is a drain voltage V applied to the FET amplifier circuit 3. A variable voltage circuit 5 for changing _{DD according} to voltage control data RD described later is used for the baseband signal I.
An envelope generating circuit for generating pseudo envelope data SE proportional to the envelope of the quadrature amplitude modulation output based on (t) and Q (t), and 6 filtering an impulse signal based on the pseudo envelope data SE. And a detector 7 for forming a pseudo envelope signal SE ′, and 7 is an output signal O (t) of the FET amplifier circuit 3.
Is detected by diode to output an envelope signal OE ', 8 is an operational amplifier which outputs an error signal DE obtained by amplifying a difference between both outputs of the detectors 6 and 7, and 9 is a pseudo envelope data S.
The ROM is a ROM for reading the corresponding voltage control data RD using E as an address input.

The quadrature amplitude modulation circuit 1 is specifically, {I
(T) cosω_c t-Q (t) sinω_c orthogonal vibration of t}
The output modulation signal M (t) is a circuit that performs width modulation.
{(I ² (T) + Q² (T))^1/2 cos (ω_c t + φ
(T))}, where φ (t) is tan^-1(Q
(T) / I (t)), of which (I² (T) + Q² 
(T))^1/2 Is the combined vector of the signals I (t) and Q (t)
And the envelope of the output modulation signal M (t).
It corresponds to the amplitude of the signal.

FIG. 7 is a diagram for explaining the transition of the modulation signal vector of FIG. 6 when the π / 4 shift QPSK is used. Here, QPSK having I and Q as coordinate axes (each signal point is “◯”).
) And QPSK (representing each signal point by “x”) having I ′ and Q ′ as coordinate axes are alternately performed for each bit. For example, when a signal point of (1,1) having I and Q as coordinate axes transits to a signal point of (-1,0) having I ′ and Q ′ as coordinate axes, the modulation signal vector thereof is as shown in FIG. And the amplitude of the envelope signal changes accordingly.

FIG. 8 is a diagram showing an example of the quadrature amplitude modulation signal of FIG. 7, and it can be seen that the amplitude of the envelope of this quadrature amplitude modulation signal changes with the transition of the modulation signal vector of FIG.
The difference between the maximum amplitude and the minimum amplitude of this envelope is, for example, about 14 dB at the output.

FIG. 9 is a circuit diagram of a conventional FET amplifier circuit.
C is the coupling capacitor, R represents the gate bias resistor, Q is a depletion type N-channel MOSFET made of gallium arsenide (G _{a A s),} etc., L is a choke.

In the figure, if the FET amplifier circuit 3 is operated in class AB or class B, and the drain voltage V _DD applied to the FET amplifier circuit 3 is made variable according to the envelope variation of the transmission signal O (t). The required output signal power P ₀ can be obtained from the FET amplifier circuit 3 with extremely high efficiency. Therefore, this drain voltage V _DD is usually the quadrature amplitude modulation signal M.
It is controlled so as to be proportional to the envelope of (t).
As shown in the drain characteristic of the FET element of
In the operating region where the drain voltage V _DD applied to the ET element is large, the drain current I _D (output power P _O ) and the drain voltage V _DD are not in a proportional relationship, so it is necessary to correct this in a proportional relationship.

Conventionally, the ROM 9 shown in FIG. 6 obtains the voltage control data RD that makes the drain voltage V _DD and the output power P _O proportional. However, since the drain voltage-output power characteristics of the FET amplifier circuit 3 are different for each FET element used, a different ROM is conventionally required for each FET element, and the man-hours at the time of manufacturing and testing are large.

Although the characteristics of the FET element change depending on the temperature, the voltage control data RD is fixed because the ROM is conventionally used, and the temperature compensation of the voltage control data RD cannot be performed.

Further, even if an attempt is made to miniaturize the device by making such a linear transmission circuit into an LSI, it is difficult to mount a different ROM for each chip because a ROM is conventionally used. Since the packaging density cannot be increased so much, it has been difficult to make the device compact.

[0012]

As described above, in the conventional linear transmission circuit, since the voltage control data RD is obtained from the ROM 9, a different ROM is required for each FET element, and it is not possible to cope with temperature changes. Further, it was difficult to make an LSI.

The object of the present invention is to obtain a FET having any characteristics.
It can provide accurate voltage control data to the amplifier circuit,
Another object of the present invention is to provide a linear transmission circuit that can perform temperature compensation of the data and can be easily integrated into an LSI.

[0014]

The above problems can be solved by the structure shown in FIG. That is, the linear transmission circuit of the present invention includes a quadrature amplitude modulation circuit 100 that performs quadrature amplitude modulation on quadrature carrier signals i (t) and q (t) with transmission baseband signals I (t) and Q (t). FET amplifier circuit 200 for amplifying the output modulation signal M (t) of the quadrature amplitude modulation circuit 100.
And the drain voltage V _DD applied to the FET amplification circuit 200
The variable voltage circuit 3 that changes according to the voltage control data RD.
In the linear transmission circuit including 00, an envelope generation circuit 400 that generates pseudo envelope data SE proportional to the envelope of the quadrature amplitude modulation output based on the transmission baseband signals I (t) and Q (t). A RAM 500 for reading the voltage control data RD of the address using the pseudo envelope data SE as an address input; the pseudo envelope data SE and the output signal O (t) of the FET amplifier circuit 200;
The difference from the envelope data proportional to the envelope of the detected output signal O (t) is obtained, and the R
The RAM update circuit 600 is provided for writing the data WD obtained by correcting the voltage control data RD read from the AM 500 into the RAM 500.

[0015]

In the linear transmission circuit of the present invention, the pseudo envelope data SE proportional to the envelope of the quadrature amplitude modulation output is generated based on the transmission baseband signals I (t) and Q (t), and the generation is performed. The pseudo envelope data SE that was created is stored in the RAM 50.
As the address input of 0, the voltage control data R of the address
D is read out and the generated pseudo envelope data S is generated.
The difference between E and the envelope data proportional to the envelope of the output signal O (t) detected from the output signal O (t) of the FET amplifier circuit 200 is obtained, and the RAM 500 is calculated according to the difference.
Data W obtained by correcting the voltage control data RD read from
By obtaining D, the correction data WD is stored in the RAM 5
00 to update the voltage control data RD.

Preferably, the updating process of the voltage control data RD is concentrated when the power of the linear transmission circuit is turned on until the difference between the generated pseudo envelope data SE and the envelope data detected from the output becomes substantially zero. By performing the update process intermittently during the operation of the linear transmission circuit, the content of the voltage control data RD of the RAM 500 always converges to the content according to the usage environment of the linear transmission circuit. As a result, the drain voltage-output power characteristic of the FET amplifier circuit 200 is always kept in a compensated state.

[0017]

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 2 is a circuit diagram of a linear transmission circuit of the embodiment, in which the same reference numerals denote the same or corresponding parts throughout the drawings, 1 is a quadrature amplitude modulation circuit (100 in FIG. 1), 2 is a variable attenuator, and 3 is FET amplification. Circuit (same as 200), 4 variable voltage circuit (same 300), 5 envelope generation circuit (same 40)
0), 6 are detectors, 7 is detector, 8 is operational amplifier, 10
Is a switch circuit for switching between the output of the operational amplifier 8 and the predetermined voltage V _r according to a control signal S1 from a write control circuit, which will be described later, and 11 is a voltage control data RD of the address using the pseudo envelope data SE as an address input. RAM to read
(Same as 500), 12 obtains the difference ΔE between the pseudo envelope data SE and the envelope data OE detected from the output, and
The difference ΔE and the voltage control data R read from the RAM 11
It is a RAM updating circuit (600 of the same) for writing the sum WD of D to the RAM 11.

In the RAM updating circuit 12, 13 is an A / D converter (A / D), 14 is a subtractor, 15 is an adder, and 16 is a write control circuit. FIG. 3 shows the RAM of the embodiment
In the operation timing chart of the update circuit, first, the envelope generation circuit 5 samples the signals I (t) and Q (t) at a predetermined cycle, and at the same time, generates a pseudo proportional to the envelope of these quadrature amplitude modulation outputs. Envelope data SE _n is obtained by an arithmetic circuit that performs, for example, {K × (I ² (t) + Q ² (t)) ^1/2 } and outputs it together with the timing signal TS.
Here, the constant K is, for example, the voltage amplification degree of the FET amplifier circuit 3.

As a result, from the RAM 11 the address S
E_n Control data RD stored in_n Read out
The variable voltage circuit 4 controls the voltage control data RD._n Corresponds to
Drain voltage V_DDn And the FET amplifier circuit 3 outputs
Drain voltage V_DDn The modulated signal M (t) 'under
The output signal O (t) from the detector 7 at this time
A detection signal OE 'is obtained. And A / D converter
Reference numeral 13 denotes A / D conversion of this detection signal OE ′ and conversion output O
E_n And the subtractor 14 outputs the pseudo envelope data SE_n When
The conversion output OE_n Difference with ΔE_n (= SE_n -OE_n )
Output. Then, the voltage control data RD at this point_n But
Drain voltage-output voltage characteristics in the FET amplifier circuit 3
If the above cannot be compensated, the above difference ΔE_n Is not zero,
The adder 15 has this difference ΔE._n And current voltage control data R
D_n Sum WD_n (= RD_n + △ E _n ) And then
And this sum WD_n Is a write pulse from the write control circuit 16
Signal WP_n By the address SE of RAM11_n Write on
Get caught. As a result, the address SE of the RAM 11_n of
The voltage control data RD is the previous RD_n To RD_n ´
(= RD_n + △ E_n ) Is updated.

In this way, when the voltage control data RD of the address SE _n is updated, the variable voltage circuit 4 changes the drain voltage V _DD applied to the FET amplifier circuit 3 from the previous V _DDn to V _{DD n} ′. Accordingly, the detection signal OE 'of the output signal O (t) also changes as shown in the figure. Then, the A / D converter 13 outputs the A / D conversion output OE of the changed detection signal OE ′.
_n'is output, but in this example, the pseudo envelope data SE
_{Since n} is equal to the converted output OE _n ′, the subtractor 14 outputs the difference ΔE _n ′ = 0. Then, the adder 15 receives the difference 0 and the voltage control data RD _n at this time.
'Sum WD _n and' (= RD _n '+ 0) to determine, but the write control circuit 16 △ E _n' does not output the write pulse signal WP _n 'by detecting the = 0, the address S
No further updates in E _n will be made.

In this way, if the envelope generation circuit 5
The sampling periods of the signals I (t) and Q (t) are R above.
When it can be taken sufficiently longer than one update cycle of AM11
Update processing of 3 cycles or more during 1 sampling period
It is also possible to do. In this way, one sampling period
Most of the voltage control data RD converges to its compensation value during the period.
Will be. Also, one cycle during one sampling period
Even if only the update process of
During the operation of the road, the same pseudo envelope data SE _n How many times
Will also occur, so the update process above for a certain period
If you do, address SE_n The voltage control data RD of
It converges to the compensation value.

Further, the envelope generating circuit 5 outputs the following signal I
When (t) and Q (t) are sampled and the pseudo envelope data SE _{n + 1} is output, the RAM is processed in the same manner as described above.
The voltage control data RD _{n + 1} of the address SE _{n + 1} of 11 is updated, and thus the voltage control data RD of the address SE of the RAM 11 corresponding to all the pseudo envelope data SE generated during the operation of the linear transmission circuit. Will be updated.

At the time of starting the RAM updating operation, the write control circuit 16 causes the external control signal CS1.
When it is energized by the write control circuit 16, the write control circuit 16 first outputs the control signal S1 to connect the contact c of the switch circuit 10 to the contact b, thereby applying a predetermined voltage V _r to the variable attenuator 2 and The amount of attenuation is made constant so that the variable attenuator 2 does not affect the updating process of the voltage control data RD. Then, the updating process of the voltage control data RD ends, and the write control circuit 16 receives the control signal C from the outside.
When the write control circuit 16 is turned off by S1, the write control circuit 16 outputs the control signal S1 to connect the contact c of the switch circuit 10 to the contact a, and thereafter operates in the same operation mode as the circuit of FIG.

FIG. 4 is a circuit diagram of a RAM updating circuit according to another embodiment, in which the same reference numerals as those in FIG.
Is a RAM update circuit, 18 is a switch circuit for switching between the output of the adder 15 and the pseudo envelope data SE according to a control signal S2 from a write control circuit described later, and 19 is a write control circuit.

When the write control circuit 19 is energized by the control signal CS1 by turning on the power supply to the linear transmission circuit, for example, the write control circuit 19 first outputs the control signal S2 to contact the switch circuit 18. By connecting c and the contact b, the pseudo envelope data SE is input to the address input terminal ADD and the data input terminal DI of the RAM 11.

Therefore, when the pseudo envelope data SE is subsequently generated from the envelope generating circuit 5, the pseudo envelope data SE is written to the address indicated by the pseudo envelope data SE in the RAM 11. RAM1
In the meantime, 1 stores the voltage control data RD having the same value as the pseudo envelope data SE.

At this time, all the pseudo-envelope data SE generated in the actual communication are intensively generated within a predetermined period, that is, all the codes (I, Q) are generated within the predetermined period. It is preferable to generate the code sequence externally so that the combination of As a result, the entire use area of the RAM 11 is initialized when the power is turned on, so that the subsequent update time of the RAM 11 described with reference to FIG. 3 is significantly shortened.

When the write control circuit 19 is deenergized by the control signal CS1 from the outside, it outputs the control signal S2 to connect the contact c of the switch circuit 18 to the contact a, and thereafter, the same as the circuit of FIG. It operates in the operation mode of.

FIG. 5 is a circuit diagram of a RAM updating circuit of another embodiment, in which 20 is a RAM according to a control signal CS2 from the outside.
It is a switch circuit that opens and closes the power supply V _CC applied to the update circuit 12 or 17.

[0030] In view, if the control signal CS2 by manual operation or a timer or the like and intermittently ON, the RAM update circuit 12 or 17 can be supplied only power V _CC when updating the voltage control data RD, which RAM update circuit 1
Power consumption by 2 or 17 is saved.

[0031]

As described above, according to the present invention, the RAM 500 for reading the voltage control data RD of the pseudo envelope data SE as an address input, the pseudo envelope data SE and the output signal of the FET amplifier circuit 200. O
The difference from the envelope data proportional to the envelope of the output signal O (t) detected from (t) is obtained, and the data WD obtained by correcting the voltage control data RD read from the RAM 500 according to the difference is obtained. RAM to write to RAM500
Since the update circuit 600 is provided, the FET amplifier circuit 200
Even if the drain voltage-output power characteristic of the FET is different for each FET element, or changes due to temperature, aging, etc., the drain voltage-output power characteristic is automatically compensated.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a circuit diagram of a linear transmission circuit according to an embodiment.

FIG. 3 is an operation timing chart of the RAM updating circuit according to the embodiment.

FIG. 4 is a circuit diagram of a RAM updating circuit according to another embodiment.

FIG. 5 is a circuit diagram of a RAM updating circuit according to another embodiment.

FIG. 6 is a circuit diagram of a conventional linear transmission circuit.

FIG. 7 is a diagram for explaining transition of the modulation signal vector of FIG. 6 when using π / 4 shift QPSK.

FIG. 8 is a diagram showing an example of the quadrature amplitude modulation signal of FIG. 7.

FIG. 9 is a circuit diagram of a conventional FET amplifier circuit.

FIG. 10 is a diagram showing drain characteristics of an example FET element.

[Explanation of symbols]

 100 quadrature amplitude modulation circuit 200 FET amplification circuit 300 variable voltage circuit 400 envelope generation circuit 500 RAM 600 RAM update circuit

Claims (3)

[Claims] 1. Orthogonal carrier signals i (t) and q
A quadrature amplitude modulation circuit (100) that quadrature amplitude modulates (t) with transmission baseband signals I (t) and Q (t), and an output modulation signal M (t) of the quadrature amplitude modulation circuit (100) is amplified. A linear transmission circuit comprising a FET amplification circuit (200) and a variable voltage circuit (300) that changes a drain voltage V _DD applied to the FET amplification circuit (200) according to voltage control data RD, wherein the transmission baseband signal An envelope generation circuit (400) for generating pseudo envelope data SE proportional to the envelope of the quadrature amplitude modulation output based on I (t) and Q (t), and the pseudo envelope data SE as an address input. RAM (500) for reading the voltage control data RD of the address
And the pseudo envelope data SE and the FET amplifier circuit (20
0) output signal O (t) detected from the output signal O (t)
The difference from the envelope data proportional to the envelope of (t) is obtained, and the data WD obtained by correcting the voltage control data RD read from the RAM (500) according to the difference is used as the RA.
A linear transmission circuit comprising a RAM update circuit (600) for writing to M (500). 2. The RAM update circuit (600), wherein the RAM receives the pseudo envelope data SE as an address input.
RAM for writing the pseudo envelope data SE in (500)
Linear transmission circuit according to claim 1, characterized in that it comprises an initialization circuit (18, 19). 3. A power supply control circuit (20, CS2) for intermittently supplying power to the RAM update circuit (600).
The linear transmission circuit according to claim 1, further comprising: