JPH0513700A - Semiconductor integrated circuit device and method of forming the same - Google Patents

Abstract

(57) [Summary] [Object] To improve the electrical reliability of a MISFET in a semiconductor integrated circuit device in which a MISFET is disposed above a step on a base. [Structure] A lower layer protrusion (7, 13, 8, 15 etc.) is arranged on a first region of a base insulator (4, 8 etc.), and on the lower layer protrusion and the first region of the base insulator. A semiconductor layer (polycrystalline silicon film) used as the channel forming region 26N of the MISFET Q over the adjacent and different second regions.
In the semiconductor integrated circuit device in which the
The difference between the height in the first region and the height in the second region of the semiconductor layer used as the channel formation region 26N of the FETQ is made smaller than the height of the lower layer protrusion.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effective when applied to a semiconductor integrated circuit device having a semiconductor layer of a semiconductor element formed on a substrate. In particular, the present invention is SRAM (S tatic R andom A cce
when applied to a semiconductor integrated circuit device having a ss M emory) a technique effectively.

[0002]

2. Description of the Related Art The SRAM described in each of Japanese Patent Application No. 2-30451 to Japanese Patent Application No. 2-30454 previously filed, which is not a known technique, has a large capacity of 4 [Mbit]. A memory cell for storing 1-bit information of the SRAM is arranged at each intersection of a complementary data line and a word line, and has a flip-flop circuit and two transfer MOSFs.
Composed of ET.

The transfer MOSFET of this memory cell is
One semiconductor region is connected to the input / output terminal of the flip-flop circuit, the other semiconductor region is connected to the complementary data line, and the gate electrode is connected to the word line.

The flip-flop circuit is configured as an information storage unit, and is composed of two driving MOSFETs and two load elements.

The driving MOSFET is one of the transfer MOs.
The drain region is connected to one semiconductor region of the SFET,
The source region is connected to the reference power supply (ground potential). The gate electrode of the driving MOSFET is the other transfer MOSFET
Connected to one of the semiconductor regions. Driving MOSFET
Are of n-channel conductivity type.

As the load element, a p-channel MOSFET is used mainly for the purpose of reducing power consumption. That is, the memory cell is composed of full CMOS. This p-channel MOSFET has one transfer MO
The drain region is connected to one semiconductor region of the SFET,
The source region is connected to the operating power supply (power supply potential). The gate electrode of the p-channel MOSFET is the other transfer MOSF
It is connected to one semiconductor region of ET.

The SRAM is constructed by including four layers of gate material and two layers of wiring material, and six conductive layers in total.

Both the transfer MOSFET and the drive MOSFET of the memory cell are formed on the main surface of the semiconductor substrate (actually, the main surface of the well region), and one semiconductor region of the transfer MOSFET and the drain region of the drive MOSFET are formed. Each is shared. The gate electrode of the driving MOSFET is formed in the first layer gate material forming step in the manufacturing process. The gate electrode and word line of the transfer MOSFET are formed in the second layer gate material forming step.

P-channel MOSFET as load element
Is disposed on the driving MOSFET, the gate electrode is formed in the third layer gate material forming step,
The source region and the drain region are formed in the fourth layer gate material forming step. A gate insulating film is formed between the gate electrode (third layer gate material) of the p-channel MOSFET and the channel formation region, the source region and the drain region (fourth layer gate material).

In the SRAM thus constructed, a part of each of the transfer MOSFET and the drive MOSFET of the memory cell is shared, and the p-channel MOSFET as a load element is arranged above the drive MOSFET. The area occupied by the memory cells is reduced, and high integration can be achieved.

[0011]

The inventor of the present invention found the following problems prior to the development of the SRAM having the above-mentioned large capacity.

(1) In the p-channel MOSFET as a load element of the memory cell of the SRAM, the channel forming region is made thin for the main purpose of reducing the leak current amount between the source region and the drain region, for example, the gate of the transfer MOSFET. It is thinner than the electrodes. That is, the fourth-layer gate material itself for forming the channel forming region, the source region and the drain region in the manufacturing process is thinned.
A polycrystalline silicon film deposited by the CVD method is used for the fourth layer gate material.

The channel forming region of the p-channel MOSFET has an underlying step shape, particularly the gate electrode (second-layer gate material) of the driving MOSFET, the p-channel MOSFE.
Step shape (top surface and side surface of lower layer protrusion) corresponding to the film thickness of the lower layer protrusion such as the gate electrode of T (third layer gate material)
Formed along. The aforementioned SRAM memory cell is
The gate electrode of the driving MOSFET is used as one electrode and p
The gate electrode of the channel MOSFET is the other electrode,
A capacitive element is formed with a dielectric film interposed therebetween. This capacitive element is constructed mainly for the purpose of increasing the amount of information stored charges in the information storage section, and the dielectric film of this capacitive element is thinned for the purpose of increasing the amount of charge storage. As a result, the shape of the lower layer protrusion is faithfully transferred to the upper layer, and the step shape of the base of the channel forming region, that is, the p-channel MOSFET is formed.
The step difference on the surface of the gate insulating film becomes large.

Therefore, when the channel forming region of the p-channel MOSFET is formed over the stepped region of the stepped shape of the base, the height of the stepped portion is multiplied by the number of steps crossed,
The length of the channel formation region (channel length) varies.

In the p-channel MOSFET, an offset structure is adopted on the drain region side mainly for the purpose of improving the punch-through breakdown voltage between the source region and the drain region and reducing the occupied area of the memory cell. P channel M as described above
The variation in the length of the channel formation region of the OSFET is caused by the p-channel MOSFET adopting the offset structure.
The offset length changes.

When the offset length of the p-channel MOSFET becomes long due to fluctuations, the supply of power to the information storage portion of the memory cell is insufficient, the stored information is inverted, and a defective data retention characteristic occurs. SRAM
Operation reliability is reduced. Also, p-channel MOS
When the offset length of the FET is shortened due to the fluctuation, an excessive current flows to the information storage portion of the memory cell, and the standby current amount increases, so that the power consumption of the SRAM increases.

(2) As described above, in the p-channel MOSFET as the load element of the memory cell, the channel forming region is thinned, but at the same time, the electric field effect from the gate electrode is enhanced and the conduction characteristic ( The gate insulating film is also thinned for the purpose of improving ON characteristics). p-channel MOSF
The polycrystalline silicon film forming the ET channel forming region, the source region and the drain region is formed with a substantially uniform film thickness along the step shape of the base. However, as a result, the polycrystalline silicon film is formed with a thin film thickness in the flat region, that is, in both the upper and lower regions of the step shape of the underlayer, but the height of the lower-layer projection is increased in the step region. Corresponding to the above, the film thickness is apparently increased.

Since the polycrystalline silicon film is patterned by the anisotropic etching technique such as RIE mainly for the photolithography technique and the miniaturization, the variation of the film thickness due to the step shape of the underlying layer of the polycrystalline silicon film is prevented. However, over-etching is necessary for the purpose of completely removing unnecessary areas.
Therefore, in the patterning process of the polycrystalline silicon film, after removing an unnecessary region of the flat region of the polycrystalline silicon film, overetching is performed on the thinned gate insulating film exposed in the removed region. In addition, the underlying insulating film is also over-etched.

According to the result of the trial manufacture conducted by the present inventor, the patterning of the polycrystalline silicon film is about 350 to 450 [%].
It was confirmed that the gate insulating film and the insulating film below the gate insulating film cannot secure the function as the etching stopper layer.

When the gate insulating film is over-etched, the gate electrode of the p-channel MOSFET is exposed, and when the underlying insulating film is over-etched, the gate electrode of the transfer MOSFET or the driving MOSFET is exposed. Exposed. As a result, a defect such as a short circuit occurs between any of these exposed gate electrodes and any of the channel formation region, the source region, and the drain region of the p-channel MOSFET.

(3) As described above, in the p-channel MOSFET as the load element of the memory cell, a polycrystalline layer forming any of the channel forming region, the source region and the drain region in the step region of the underlying step shape. The film thickness of the silicon film is apparently thick. A p-channel MOSFET is used for the polycrystalline silicon film used as the channel formation region.
N-type impurities that set the threshold voltage of the device to the enhancement type are introduced. A p-type impurity that reduces the resistance value is introduced into the polycrystalline silicon film used in each of the source region (source wiring) and the drain region. Both impurities are introduced by ion implantation with high controllability of the impurity concentration.

Therefore, the n-type impurity is not introduced into the polycrystalline silicon film used as the channel formation region in the thick film thickness portion of the stepped region of the stepped shape of the base of the polycrystalline silicon film, so that the p-channel MOSFET is formed. It becomes difficult to control the threshold voltage. Similarly, p is added to the polycrystalline silicon film used as either the source region or the drain region.
Since the type impurities are not introduced, the resistance becomes high partially,
The disconnection is apparently defective.

The objects of the present invention are as follows.

(1) In a semiconductor integrated circuit device in which a MISFET is arranged above a step of a base, the MISFET
Improve the electrical reliability of.

(2) In a semiconductor integrated circuit device provided with an SRAM in which a MISFET as a load element of a memory cell is arranged above a step of a base, at least one of reduction of power consumption and improvement of operation reliability of the SRAM is required. Try.

(3) In addition to the purpose (2), the SRA
The degree of integration of M is improved.

(4) To improve electrical reliability in a semiconductor integrated circuit device having a semiconductor layer as a resistance element above a step of a base.

(5) In a semiconductor integrated circuit device in which a MISFET is arranged above a step of a base, the MISFET
Optimization is performed at the time of patterning the channel forming region, the source region and the drain region.

(6) In the semiconductor integrated circuit device in which the MISFET is arranged above the step of the base, the MISFET
Optimization is performed when introducing impurities into any of the channel formation region, the source region and the drain region.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0031]

Among the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

(1) A lower layer protrusion is arranged on the first region of the base insulator, and the MI is extended over the lower layer protrusion and the second region adjacent to and different from the first region of the base insulator.
In a semiconductor integrated circuit device in which a semiconductor layer used as a channel formation region of an SFET is arranged, the MIS
The difference between the height in the first region and the height in the second region of the semiconductor layer used as the channel formation region of the FET is smaller than the height of the lower layer protrusion.

(2) The MISFET of the above-mentioned means (1) is
It is a load element of the flip-flop circuit of the SRAM memory cell.

(3) The MISFET of the above-mentioned means (2) is
The gate electrode has an offset structure in which the end of the drain region on the side of the gate electrode is separated from the end face of the gate electrode on the side of the drain region.

(4) M of the means (2) or the means (3)
The semiconductor layer used as the channel formation region of the ISFET has a film thickness smaller than the height of the lower layer protrusion.

(5) The semiconductor layer used as the channel formation region of the MISFET of the above-mentioned means (4) is 30 to 5
The film thickness is set within the range of 0 [nm].

(6) Between the second region of the underlying insulator according to any one of the means (1) to (5) and the semiconductor layer used as the channel formation region of the MISFET, the lower layer protrusion is formed. An insulator having a film thickness substantially equal to or slightly lower than the height is formed.

(7) Between the underlying insulator of any one of the above means (1) to (5) and the semiconductor layer used as the channel formation region of the MISFET, the lower layer protrusion of the first region and the above An insulator having a small thickness between the semiconductor layer and the base layer and the semiconductor layer in the second region is formed.

(8) A lower layer protrusion is disposed on the first region of the base insulator, and the resistance is provided on the lower layer protrusion and the second region adjacent to and different from the first region of the base insulator. In a semiconductor integrated circuit device in which a semiconductor layer used as a layer is arranged, a difference between a height of the semiconductor layer used as the resistance layer in the first region and a height of the semiconductor layer in the second region is It is smaller than the height.

(9) A lower layer protrusion is arranged on the first region of the base insulator, and the lower layer protrusion and the first portion of the base insulator are arranged.
MISF over a second area adjacent to and different from the area
A method of forming a semiconductor integrated circuit device in which a semiconductor layer used as a channel formation region of this MISFET is disposed with a gate insulating film of ET interposed, and includes the following steps (A) to (E).

(A) a step of forming a lower layer projection on the first region of the base insulator, (B) almost equal to or higher than the height of the lower layer projection on the second region of the base insulator. An insulator having a slightly lower film thickness, or the second region of the base insulator and MISFE
A step of forming an insulator with a semiconductor layer used as a channel formation region of T, the thickness of which is thicker than the thickness between the lower layer protrusion of the first region and the semiconductor layer; ) Forming a gate insulating film of the MISFET on the entire surface of the insulator including the first region and the second region, (D) Semiconductor used as a channel forming region of the MISFET on the entire surface of the gate insulating film A step of forming a layer, (E) at least the semiconductor layer is subjected to residual patterning over the first region and the second region, and MISFET is formed.
Forming a channel formation region of.

(10) A lower layer protrusion is disposed on the first region of the base insulator, and the MIS is extended over the lower layer protrusion and the second region adjacent to and different from the first region of the base insulator.
In the method of forming a semiconductor integrated circuit device in which a semiconductor layer used as any of a channel formation region, a source region, and a drain region of an FET is arranged, the following step (A)
To (D).

(A) a step of forming a lower layer protrusion on the first region of the base insulator, (B) a height substantially equal to or higher than the height of the lower layer protrusion on the second region of the base insulator. An insulator having a slightly lower film thickness, or the second region of the base insulator and MISFE
A step of forming an insulator with a semiconductor layer used as a channel formation region of T, the thickness of which is thicker than the thickness between the lower layer protrusion of the first region and the semiconductor layer; ) A channel forming region of the MISFET is formed on the entire surface of the insulator including the first region and the second region,
A step of forming a semiconductor layer used as either a source region or a drain region, (D) a channel forming region of the semiconductor layer, a source region,
A step of ion-implanting an impurity forming any one of the drain regions.

[0044]

According to the above-mentioned means (1), the MISFE is
Since it is possible to reduce the amount of variation in length based on the height of the lower-layer protrusion of the channel formation region (semiconductor layer) of T and reduce the amount of current flowing between the source region and the drain region, Characteristics and electrical reliability of the semiconductor integrated circuit device can be improved.

According to the above-mentioned means (2), since the load element of the flip-flop circuit of the memory cell can reduce the variation in the amount of current supplied from the power supply to the information storage node area, excessive supply of current in the SRAM can be achieved. Can be reduced and the amount of standby current can be reduced, or insufficient supply of current can be reduced and data retention failure can be reduced. The reduction of the standby current amount can reduce the power consumption of the SRAM, and the reduction of the data retention failure can be reduced by the SRA.
The operational reliability of M can be improved.

According to the above-mentioned means (3), the punch-through breakdown voltage between the source region and the drain region of the MISFET as the load element can be improved, and this MISFET can be improved.
Since the planar size can be reduced, the area occupied by the memory cells can be reduced, and the degree of integration of SRAM can be improved.

According to the above-mentioned means (4) or means (5), the leak current between the source region and the drain region of the MISFET as the load element can be reduced, so that the standby current amount can be reduced and the SRAM can be reduced. Low power consumption can be achieved.

According to the above-described means (6) or means (7), in the second region of the base insulator, a portion corresponding to the height of the lower layer protrusion of the first region is used as a channel formation region of the MISFET. Since the height of the semiconductor layer used can be increased (becomes equal to or close to the height of the semiconductor layer in the first region, that is, the base can be flattened), any one of the means (1) to (5) The effect of is obtained.

According to the above-mentioned means (8), it is possible to reduce the amount of variation in the length of the lower layer protrusion of the resistance layer (semiconductor layer) based on the height thereof and to reduce the variation in the resistance value of the resistance layer. It is possible to stabilize the amount of current flowing through the resistance layer and improve the electrical reliability of the semiconductor integrated circuit device.

According to the above-mentioned means (9), the step due to the lower layer protrusion is reduced in the insulator formed in the step (B), and the surface of the gate insulating film formed in the step (C) is reduced. Since the flattened portion of the semiconductor layer formed in the step (D) and having an apparently thick film thickness along the step due to the lower layer protrusion disappears, the first region of the semiconductor layer, the second region of the semiconductor layer
Patterning of the semiconductor layer in the step (E) can be performed under etching conditions according to the film thickness of any flat region of the region, and the amount of overetching of the semiconductor layer can be reduced.
The reduction of the over-etching amount of the semiconductor layer can prevent both the etching of the gate insulating film below the semiconductor layer and the etching reaching the conductor layer (for example, the lower layer protrusion). It is possible to prevent a short-circuit defect between and.

According to the above-mentioned means (10), the step due to the lower layer protrusion is reduced in the insulator formed in the step (B), and the base of the semiconductor layer formed in the step (C) is flat. Since there is no portion having a thick apparent thickness along the step due to the lower layer protrusion of this semiconductor layer,
The film thickness of the first region, the second region, and any region between the first region and the second region of the semiconductor layer can be formed to be substantially uniform, and any one of the semiconductor layers can be formed in the step (D). Impurities can be uniformly introduced into the region. The fact that impurities can be uniformly introduced into this semiconductor layer means that, when impurities are introduced into the channel formation region, there is no thick region based on the lower-layer projections of the semiconductor layer, and there is no region where impurities are not introduced. MISFE, such as stable voltage control
The electrical reliability of T can be improved. Further, the ability to uniformly introduce impurities into the semiconductor layer means that when the impurities are introduced into either the source region or the drain region, there is no thick region based on the lower-layer protrusions of the semiconductor layer, and the impurities are not introduced. Since the area is eliminated, disconnection failure can be prevented and the electrical reliability of the MISFET can be improved.

With respect to the configuration of the present invention, the flip-flop circuit as the information storage unit of the memory cell is completely CM.
An example in which the present invention is applied to an SRAM configured by an OS will be described together with an embodiment.

In all the drawings for explaining the embodiments, those having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

[0054]

[Example] (Example 1) S which is Example 1 of the present invention
The structure of the RAM memory cell is shown in FIG. 5 (equivalent circuit diagram).

As shown in FIG. 5, the memory cell of the SRAM is arranged at the intersection of the first word line WL1 and the second word line WL2 and the first data line DL1 and the second data line DL2. The memory cell is composed of a flip-flop circuit and two transfer MISFETs Qt1 and Qt2. The flip-flop circuit is configured as an information storage unit, and this memory cell stores 1 information or 0 information of 1 [bit].

Two transfer MISFE of the memory cell
Each of TQt1 and Qt2 connects one semiconductor region to each of a pair of input / output terminals of the flip-flop circuit. The other semiconductor region of the transfer MISFET Qt1 is connected to the first data line DL1, and the gate electrode is the first word line WL.
Connected to 1. The other semiconductor region of the transfer MISFET Qt2 is connected to the second data line DL2, and the gate electrode is connected to the second word line WL2. Each of the two transfer MISFEETs Qt1 and Qt2 is of n-channel conductivity type.

The flip-flop circuit includes two drive MISFETs Qd1 and Qd2 and two load MISSFs.
ETQp1 and Qp2. MISF for drive
Each of ETQd1 and ETQd2 is of n-channel conductivity type. Each of the load MISFETs Qp1 and Qp2 is of p-channel conductivity type. That is, the SRA of this embodiment
The M memory cells have a complete CMOS (full CMOS) structure.

The driving MISFET Qd1 and the load M
Each of the ISFETs Qp1 connects their drain regions and their gate electrodes to each other to form a CMOS. Similarly, drive MISFET Qd2 and load MIS
Each of the FETs Qp2 connects their drain regions and their gate electrodes to each other to form a CMOS. The drain regions (input / output terminals) of the drive MISFET Qd1 and the load MISFET Qp1 are respectively transferred to the transfer MISF.
While being connected to one semiconductor region of ETQt1,
Driving MISFET Qd2, load MISFET Qp2
Of the respective gate electrodes. MISFET for drive
The drain regions (input / output terminals) of the Qd2 and the load MISFET Qp2 are connected to one semiconductor region of the transfer MISFET Qt2, and the drive MISFE is used.
The gate electrodes of the TQd1 and the load MISFET Qp1 are connected.

A reference voltage Vss (for example, 0 [V]) is supplied to the source regions of the driving MISFETs Qd1 and Qd2. The SRAM of this embodiment is not limited to this method.
Includes a step-down power supply circuit, supplies a high power supply voltage Vcc to a part of peripheral circuits (for example, an input / output circuit), and supplies a low power supply voltage Vcc which is stepped down mainly for the memory cell array. In other words, the source regions of the load MISFETs Qp1 and Qp2 are lowered in the low power supply voltage Vcc (for example, 3 to 4).
[V]) is supplied.

The divided word line method is adopted for the SRAM of this embodiment. In the divided word line method, one word decoder circuit among a plurality of memory blocks arranged in each memory block is selected by an X decoder circuit via a main word line (MWL), and the selected word decoder circuit is used to select a memory. A first word line WL1 and a second word line WL2 extending to a predetermined number of memory cell arrays among a plurality of arranged in a block are selected. A first decoder extending to the word decoder circuit and the memory cell array
Each of the word line WL1 and the second word line WL2 is connected via a sub word line (SWL).

Next, a specific structure of the SRAM memory cell will be described. FIG. 2 (plan view) shows the planar structure of the completed state of the memory cell, and FIG. 3 and FIG. 4 (plan view) show the planar structure of each manufacturing step in the manufacturing process. The cross-sectional structure of the completed state of the memory cell is shown in FIG. 1 (a cross-sectional view taken along the line II of FIG. 2).

As shown in FIGS. 1 and 2, the SRAM mainly comprises a p--type semiconductor substrate 1 made of single crystal silicon. A p-type well region 2 is formed on the main surface of a part of the p-type semiconductor substrate 1. An n-type well region (not shown) is formed in the main surface portion of the other region of p-type semiconductor substrate 1. The p-type well region 2 is an n-channel MISFE
It is formed in the formation region of TQn, that is, the formation region of the memory cell array and a part of the peripheral circuit. The n-type well region is formed in the formation region of the p-channel MISFET Qp, that is, in another region of the peripheral circuit.

Since the SRAM of this embodiment has the step-down power supply circuit built-in as described above and supplies the stepped-down low power supply voltage Vcc to the memory cell array, the region of the memory cell array in the p-type well region 2 is the other region. Is electrically isolated from the area of and is electrically independent. This p-type well region 2 is separated by a buried n-type semiconductor region 1 formed between the p-type semiconductor substrate 1 and the p-type well region 2.
A (bottom of p-type well region 2) and n-type well region (p
(On the side of the mold well region 2).

The memory cell of the SRAM is formed on the main surface of the active region of the p-type well region 2. Of the memory cells, each of the two driving MISFETs Qd1 and Qd2 is in a region defined by the element isolation insulating film 4 and the p-type channel stopper region 5 as shown in FIGS. 1, 2 and 3. In, the main surface of the p-type well region 2 is formed. Each of the driving MISFETs Qd1 and Qd2 is mainly composed of a p-type well region 2, a gate insulating film 6, a gate electrode 7, a source region and a drain region.

The p-type well region 2 is a driving MISFE.
The respective channel forming regions of TQd1 and Qd2 are formed. The gate insulating film 6 is formed of, for example, a silicon oxide film formed by a thermal oxidation method and has a film thickness of about 10 to 15 [nm].

The gate electrode 7 is formed in the first layer gate material forming step, and is formed of, for example, a single-layer polycrystalline silicon film deposited by the CVD method. An n-type impurity such as P (or As) that reduces the resistance value is introduced into this polycrystalline silicon film. The polycrystalline silicon film is formed with a film thickness of, for example, about 80 to 120 [nm] mainly for the purpose of flattening the surface of the interlayer insulating film which is the base of the upper conductive layer by reducing the film thickness. .

Each of the source region and the drain region is composed of an n type semiconductor region 10 having a low impurity concentration and an n + type semiconductor region 11 having a high impurity concentration provided on the main surface thereof. Two types of n-type semiconductor regions 1 having different impurity concentrations
Each of the 0 and n + type semiconductor regions 11 has the gate electrode 7
And the side wall spacers 9 formed on the side walls thereof are self-aligned. That is, the drive MISF
ETQd1, source and drain regions of each of Qd2 so-called double drain (DDD: D ouble D iffused D
rain) structure. Since each of the driving MISFETs Qd1 and Qd2 adopting the double drain structure can reduce the parasitic capacitance added to the pn junction of each of the source region and the drain region, the drivability can be increased.

A side wall spacer 9 is formed on the side wall of the gate electrode 7 in the gate length direction, and an insulating film 8 is formed on the upper side. Both the sidewall spacers 9 and the insulating film 8 are formed of, for example, a silicon oxide film deposited by the CVD method and have a film thickness of about 120 to 160 [nm].

Of the memory cells, two transfer MISFs
As shown in FIGS. 1, 2 and 3, each of ETQt1 and ETQt2 has a main surface of the p-type well region 2 in a region defined by the element isolation insulating film 4 and the p-type channel stopper region 5. Is composed of. Transfer MISFET Qt
1 and Qt2 are a p-type well region 2 and a gate insulating film 1, respectively.
2, the gate electrode 13, the source region and the drain region are mainly configured.

The p-type well region 2 is a transfer MISFE.
Channel forming regions of TQt1 and Qt2 are formed. The gate insulating film 12 is formed of, for example, a silicon oxide film formed by a thermal oxidation method, and has a film thickness of about 10 to 15 [nm].

The gate electrode 13 is formed in the second-layer gate material forming step, and is formed of, for example, a polycrystalline silicon film 13A and a refractory metal silicide film 13B laminated thereon (polycide structure). Composed of. The lower polycrystalline silicon film 13A is deposited by the CVD method, and an n-type impurity such as P (or As) that reduces the resistance value is introduced. The lower polycrystalline silicon film 13A is formed with a thin film thickness of, for example, about 60 to 80 [nm] mainly for the purpose of flattening the surface of the interlayer insulating film serving as the base of the upper conductive layer. . The upper refractory metal silicide film 13B is formed of, for example, a WSi ₂ film deposited by a sputtering method or a CVD method. Since the upper refractory metal silicide film 13B has a smaller specific resistance value than the lower polycrystalline silicon film 13A, the signal transmission speed can be increased. The upper refractory metal silicide film 13B is, for example, 70-
It is formed with a film thickness of about 90 [nm]. As the refractory metal silicide film 13B above the gate electrode 13, MoSi is used.
_It may be changed to any of _two films, a TiSi ₂ film and a TaSi ₂ film.

Each of the source region and the drain region is composed of an n + type semiconductor region 18 having a high impurity concentration and an n type semiconductor region 17 having a low impurity concentration provided between the n + type semiconductor region 18 and the channel forming region. Of the two types having different impurity concentrations, the n-type semiconductor region 17 is formed on the side portion of the gate electrode 13 in the gate length direction in self-alignment with the gate electrode 13. The n + type semiconductor region 18 is formed on the side portion of the gate electrode 13 in the gate length direction by self-alignment with the sidewall spacer 16 (see FIG. 9).
That is, each of the transfer MISFETs Qt1 and Qt2 is L
DD consisting of (L ightly D oped D rain) structure. L
Transfer MISFETs Qt1 and Qt2 adopting the DD structure
In each of the above, since the electric field strength can be relaxed in the vicinity of the drain region, the amount of hot carriers generated can be reduced and the change in the threshold voltage over time can be reduced.

An insulating film 8 is formed on the upper surface of the gate electrode 13, and sidewall spacers 16 are formed on the side walls. Both the insulating film 8 and the sidewall spacers 13 are formed of, for example, a silicon oxide film deposited by the CVD method and have a film thickness of about 180 to 270 [nm].

Each of the gate electrodes 13 of the transfer MISFETs Qt1 and Qt2 has a word line (W) in the gate width direction, as shown in FIGS. 1, 2 and 3.
L) 13 is connected. The word line 13 is the gate electrode 1
3 and the same conductive layer. In the memory cell MC, the first word line (WL1) 13 is connected to the gate electrode 13 of the transfer MISFET Qt1, and the second word line (WL2) 13 is connected to the gate electrode 13 of the transfer MISFET Qt2.

The first word line 13 and the second word line 13
A reference voltage line (Vss) 13 connected to the respective source regions (n + type semiconductor regions 11) of the driving MISFETs Qd1 and Qd2 is arranged between the two. The reference voltage line 13 is formed of the same conductive layer as the word line 13. The connection between the reference voltage line 13 and the source region of the driving MISFET Qd is made by connecting holes 14 formed in the lower polycrystalline silicon film 13A and the insulating film 12 in the same layer as the gate insulating film 12.
This is performed by directly connecting the upper refractory metal silicide film 13B to the source region through each of the connection holes 14 formed in.

MISFE for two loads of the memory cell
Each of TQp1 and Qp2 is formed on the region of the driving MISFET Qd, as shown in FIGS. 1, 2, and 4. The load MISFET Qp1 is a drive MISFET Q.
The load MISFET Qp2 is formed on the region of d2, and the load MISFET Qp2 is formed on the drive MISFET Qd1. MI for load
Each of the SFETs Qp1 and Qp2 is a driving MISFETQ
The gate length direction is arranged substantially orthogonal to the gate length direction of each of d1 and Qd2. This load MISFET Qp
Each of 1 and Qp2 is mainly composed of an n-type channel forming region 26N, a gate insulating film 24, a gate electrode 23, a source region 26P and a drain region 26P.

The gate electrode 23 is formed in the third layer gate material forming step, and is formed of, for example, a polycrystalline silicon film deposited by the CVD method. This polycrystalline silicon film is introduced with an n-type impurity, such as P (or As), for reducing the resistance value, and is mainly composed of, for example, 60 to 60 for the purpose of flattening the surface of the interlayer insulating film which is the base of the upper conductive layer. It is formed with a thin film thickness of about 80 [nm]. A part of the gate electrode 23 is formed as an intermediate conductive layer 23, and the intermediate conductive layer 23 passes through a connection hole 22 formed in the insulating film 21 thereunder, and one of the n + type semiconductor regions 18 of the transfer MISFET Qt, It is connected to the n + type semiconductor region 11 corresponding to the drain region of the driving MISFET Qd and the gate electrode 7.

The gate insulating film 24 is the gate electrode 2
3 on top. The gate insulating film 24 is formed, for example, by CVD using inorganic silane (SiH ₄ ) and N ₂ O as source gases.
It is formed of a silicon oxide film deposited by the method. This silicon oxide film is formed with a thin film thickness of, for example, about 35 to 45 [nm] mainly for the purpose of enhancing the electric field effect from the gate electrode 23 of the load MISFET Qp and improving the conduction characteristic (ON characteristic). It

The surface of the gate insulating film 24 is flattened because the step shape generated by the lower-layer protrusions is alleviated by the insulating film 21. The lower layer protrusion is the lower layer transfer MIS.
It is formed of at least one of the gate electrode 13 of the FET Qt and the insulating film 15 formed on the upper surface thereof, and the gate electrode 7 of the driving MISFET Qd and the insulating film 8 formed on the upper surface thereof.

The n-type channel forming region 26N is formed on the gate electrode 23 with a gate insulating film 24 interposed therebetween. n
The type channel forming region 26N is arranged so that its gate length direction is substantially aligned with the gate width direction of the driving MISFET Qd. The n-type channel forming region 26N is formed in the gate material forming step of the fourth layer and is composed of, for example, a polycrystalline silicon film deposited by the CVD method. For polycrystalline silicon film, load M
An n-type impurity (for example, P) that sets the threshold voltage of the ISFET Qp to the enhancement type is introduced. Since the load MISFET Qp is in a conductive state between the source region 26P and the drain region 26P during operation (ON operation), the low power supply voltage V lowered to the information storage node region is obtained.
Sufficient cc can be supplied and information can be held stably. In addition, since the load MISFET Qp is in a non-conducting state between the source region 26P and the drain region 26P when it is not operating (OFF operation), the stepped-down low power supply voltage Vcc can be supplied to the information storage node region. Almost surely cut off, and the amount of standby current can be reduced. This point, MISF for load
ETQp is different from the high resistance element for load.

The source region 26P is integrally formed on one end side (source region side) of the n-type channel forming region 26N and is formed of the same conductive layer. That is, the source region 26P is formed of the polycrystalline silicon film formed in the fourth layer gate material forming step, and p-type impurities (for example, BF ₂ ) are introduced into this polycrystalline silicon film. The source region 26P is
In each of FIGS. 2 and 4, reference numeral 26P is attached and the region is surrounded by the one-dot chain line (a part is configured as the power supply voltage line 26P). The drain region 26P
Is integrally formed on the other end side (drain side) of the n-type channel forming region 26N, is formed of the same conductive layer as the source region 26P, and has p-type impurities introduced therein. That is, the n-type channel forming region 26N is the source region 26.
The source region 26 is formed in the region 26P formed of the same conductive layer as the P and drain regions 26P and surrounded by the alternate long and short dash line.
The P and drain regions 26P are formed, and the n-type channel formation region 26N is formed around the other region 26P surrounded by the alternate long and short dash line.

The drain region 26P of the load MISFET Qp1 is the n + side of the transfer MISFET Qt1.
Type semiconductor region 18 (or 11), driving MISFE
N + type semiconductor region 1 corresponding to the drain region of TQd1
1 and the gate electrode 7 of the driving MISFET Qd2. Similarly, the drain region 26P of the load MISFET Qp2 is one of n + of the transfer MISFET Qt2.
The semiconductor region 18, the n + type semiconductor region 11 corresponding to the drain region of the driving MISFET Qd2, and the driving MIS.
It is connected to the gate electrode 7 of the FET Qd1. These connections are made via the intermediate conductive layer 23 integrally formed with the gate electrode 23 of the load MISFET Qp.

The end of the drain region 26P of the load MISFET Qp on the n-type channel forming region 26N side is separated from the end of the gate electrode 23 on the drain region 26P side. In other words, in the load MISFET Qp, the gate electrode 23 and the drain region 26P are separated without overlapping. That is, the drain region 26P side of the load MISFET Qp has an offset structure. The load MISFET Qp adopting this offset structure can improve the breakdown withstand voltage between the n-type channel forming region 26N and the drain region 26P. That is, this offset structure separates the drain region 26P from the n-type channel formation region 26N in which the charge is induced by the gate electrode 23, so that the pn junction between the drain region 26P and the n-type channel formation region 26N is broken. Down breakdown voltage can be improved. In the SRAM memory cell of the present embodiment, the offset length (offset dimension) of the load MISFET Qp is set to about 0.4 [μm].

As shown in FIGS. 1, 2 and 4, the source region 26P of the load MISFET Qp is integrally connected to the power supply voltage line (Vcc) 26P and is formed of the same conductive layer. The power supply voltage line 26P is formed of a polycrystalline silicon film formed in the fourth layer gate material forming step, and p-type impurities are introduced into this polycrystalline silicon film as in the source region 26P and the drain region 26P. To be done.

The polycrystalline silicon film forming the n-type channel forming region 26N, the source region 26P and the drain region 26P of the load MISFET Qp is mainly intended to reduce the amount of leak current between the source region 26P and the drain region 26P. As a thin film, specifically, a film having a thickness of about 30 to 50 [nm] is formed. The polycrystalline silicon film has a film thickness of about 50.
When the film thickness is smaller than [nm], the amount of leak current is extremely reduced. Further, the polycrystalline silicon film is about 30 [n
The film is not formed unless the film thickness is more than m]. This reduction in the amount of leakage current can suppress the wasteful supply of power and reduce the amount of standby current when the load MISFET Qp is not operating.

A load MISFET having such a configuration
The n-type channel forming region 26N of Qp is shown in FIGS.
As shown in (enlarged cross-sectional view modeling a main part), the surface of the underlying gate insulating film 24 is flattened by the underlying insulating film 21 and is not affected by the step shape due to the lower layer protrusions. To be done. In FIG. 6, in order to facilitate understanding of the principle of the present invention, the step shape of the base of the n-type channel formation region 26N of the load MISFET Qp is the transfer MI.
Gate electrode 13 of SFET Qt and insulating film 1 on its upper surface
The case where it is generated in 5 is shown. In FIG. 7 (enlarged cross-sectional view modeling a main part in a non-planarized state), the state in which the insulating film 21 is not flattened, that is, the step shape of the base is the load M
Transferred to the surface of the gate insulating film 24 of ISFET Qp,
An n-type channel forming region 26N is formed on the gate insulating film 24.
Shows the state in which the is formed.

As shown in FIG. 7, the load MISFET Q
The p-type n-channel forming region 26N is formed along the step shape of the base, that is, the surface of the insulating film 15 on the upper surface of the gate electrode 13 of the lower transfer MISFET Qt and the gate electrode 13.
Are arranged over a region in which the gate electrode 13 is not arranged, and are arranged along the surface of the sidewall spacer 16 on the side surface of the gate electrode 13 between them (in the step). The length (channel length) L of the n-type channel formation region 26N shown in FIG.
g ′ is a plan view of the n-type channel forming region 26 shown in FIG.
It is equivalent to the length Lg of N (the patterning dimension does not change). However, the effective length Lg 'of the n-type channel forming region 26N shown in FIG. 7 is the height of the step, that is, the height of the lower layer protrusion (the total thickness of the gate electrode 13 and the insulating film 15). The film thickness) Lh is multiplied by the number across the step, and becomes longer than the length Lg of the n-type channel formation region 26N shown in FIG. In other words, the length Lg of the n-type channel forming region 26N shown in FIG.
Since it is relaxed by, the dimensional fluctuation due to the influence of the step shape of the base is reduced.

Since the load MISFET Qp of this embodiment has the offset structure on the drain region 26P side, the fluctuation of the effective length Lg 'of the n-type channel forming region 26N shown in FIG. It becomes a long fluctuation. FIG. 8 (relationship diagram between source-drain current and offset length) shows the source region 26 of the load MISFET Qp.
Amount of current flowing between P and drain region 26P (I _DS )
And the offset length. In FIG. 8, the horizontal axis represents the gate voltage [V], and the vertical axis represents the source-drain current (lo).
g _IDS ) [A], respectively.

As shown in FIG. 8, the load MISFET Q
When the offset length of p (processing dimension using photolithography technology) is set to 400 [nm], the effective offset length is 600 [nm] due to the influence of the step shape of the base.
The amount of current between the source and the drain decreases as the value increases.
This reduction in the amount of current between the source and drain causes insufficient supply of the lowered low power supply voltage Vcc to the information storage node region of the memory cell, resulting in defective data retention characteristics. Further, when the effective offset length is reduced to 100 [nm] due to the influence of the step shape of the base, the amount of current between the source and drain increases. This increase in the source-drain current amount increases the standby current amount because the excessively reduced low power supply voltage Vcc is supplied to the information storage node region of the memory cell.

As described above, in the load MISFET Qp of the present embodiment, since the step shape of the base is relaxed, the effective fluctuation of the offset length is reduced and the preset offset length can be secured. In addition, neither the data retention characteristic defect nor the standby current amount increase occurs.

The specific material and forming method of the insulating film 21 for alleviating the stepped shape of the underlayer of the load MISFET Qp in this manner will be described later in the forming method.

Transfer MISFET Qt of the memory cell
As shown in FIGS. 1 and 2, the other n + type semiconductor region 18 of the intermediate conductive layers 23 and 29, the buried conductive layer 3 is formed.
2 are sequentially interposed and connected to the data line (DL) 33.

The intermediate conductive layer 29 is formed on the interlayer insulating film 27, and one end of the intermediate conductive layer 29 is connected to the intermediate conductive layer 23 through a connection hole 28 formed in the interlayer insulating film 27. This intermediate conductive layer 23 is a transfer MISFETQ.
It is directly connected to the other n + type semiconductor region 18 of t. The other end side of the intermediate conductive layer 29 is drawn out in the extending direction of the word line 13 and is connected to the embedded conductive layer 32 embedded in the connection hole 31 formed in the interlayer insulating film 30. The buried conductive layer 32 is directly connected to the data line 33.

The intermediate conductive layer 29 is formed in the first-layer metal wiring material forming step in the manufacturing process, and is formed of, for example, a refractory metal film. The refractory metal film is formed of, for example, a W film deposited by a sputtering method or a CVD method and has a film thickness of about 250 to 350 [nm].

The interlayer insulating film 27, which is a base of the intermediate conductive layer 29, is formed of, for example, a composite film in which a silicon oxide film 27A and a BPSG film 27B are sequentially laminated. The lower silicon oxide film 27A is formed mainly for the purpose of preventing leakage of P or B added to the upper BPSG film 27B. The upper BPSG film 27B is subjected to reflow and is formed mainly for flattening the surface.

The buried conductive layer 32 is the interlayer insulating film 30.
Is selectively formed on the intermediate conductive layer 29 in the connection hole 31 formed in. The embedded conductive layer 32 absorbs the steep step shape generated in the connection hole 31, and can prevent the disconnection defect at the step portion of the upper data line 33. The buried conductive layer 32 is formed of, for example, a W film deposited by the selective CVD method.

The interlayer insulating film 30, as shown in FIG. 1, is a deposition type silicon oxide film 30A, a coating type silicon oxide film 30B,
The stacked silicon oxide film 30C has a three-layer stacked structure in which the stacked silicon oxide films 30C are sequentially stacked. The lower silicon oxide film 30A, Each of the upper layer of the silicon oxide film 30C, for example, tetra-lizard silane: a (TEOS T etra E thoxy S ilane ) gas is deposited by plasma CVD method with source gas. Silicon oxide film 30B of the intermediate layer is spin-on-glass (S pin O n G
After being applied by the lass) method and baked, the entire surface is etched (etch back). The intermediate silicon oxide film 30B can even the surface of the interlayer insulating film 30. The intermediate silicon oxide film 30B is basically formed on the stepped portion on the surface of the lower silicon oxide film 30A except for the region of the connection hole 31 which connects the intermediate conductive layer 29 and the data line 33 described above. .

The data line (DL) 33 is formed on the interlayer insulating film 30, as shown in FIG. Data line 33
Is formed in the second-layer metal wiring material forming step and has a two-layer laminated structure in which, for example, a barrier metal film 33A and an aluminum alloy film 33B are sequentially laminated. The barrier metal film 33A is basically a transfer MISFET.
It is formed mainly for the purpose of preventing mutual diffusion of the other n + type semiconductor region 18 of Qt, Si of the intermediate conductive layer 23, and Al of the aluminum alloy film 33B. Barrier metal film 3
3A is formed of, for example, a TiW film deposited by a sputtering method and has a film thickness of about 150 to 250 [nm].
The aluminum alloy film 33B is formed of, for example, aluminum to which at least one of Cu and Si is added,
It is formed with a film thickness of about 700 to 900 [nm]. The data line 33 may be formed of a single layer aluminum alloy film or aluminum film.

On the memory cell, as shown in FIG. 1 and FIG.
As shown in, the main word line (MWL) 29 and the sub word line (SWL1) 29 are arranged. Each of the main word line 29 and the sub word line 29 is formed of the same conductive layer and the same conductive layer as the intermediate conductive layer 29 described above (formed in the metal wiring material forming step of the first layer).

As shown in FIG. 1, a final protective film 34 is formed on the entire surface of the substrate including the data lines 33 of the memory cells (excluding regions for external terminals). This final protective film 34
Although its structure is not shown in detail, it has a three-layer structure in which a silicon oxide film, a silicon nitride film, and a resin film are sequentially stacked. The silicon oxide film below the final protective film 34 is deposited by a CVD method using tetraethoxysilane gas as a source gas. The intermediate silicon nitride film is deposited by the plasma CVD method. The upper resin film is formed of, for example, a polyimide resin.

Next, a part of the method of forming the SRAM described above,
Specifically, a method of forming the load MISFET of the memory cell and the underlying layer will be briefly described with reference to FIGS. 9 to 11 (cross-sectional views of essential parts shown in each manufacturing process).

First, the driving MISFET Qd and the transfer MISFET Qt of the memory cell are formed on the main surface of the p-type well region 2 of the p-type semiconductor substrate 1. MISF for drive
An insulating film 8 is formed on the upper surface of the gate electrode 7 of ETQd, and a sidewall spacer 9 is formed on the side surface thereof. Also,
The gate electrode 13 (word line 1 of the transfer MISFET Qt
An insulating film 15 is formed on the upper surface and side wall spacers 16 are formed on the side surfaces.

Next, as shown in FIG. 9, the gate electrode 7 of the driving MISFET Qd and the transfer MI are formed on the entire surface of the substrate.
The insulating film 21 is formed mainly for the purpose of relaxing the step shape based on the lower layer protrusions such as the gate electrode 13 of the SFET Qt. The insulating film 21 is formed of, for example, a silicon oxide film formed by spin-on-glass method, then cured by baking, and anisotropically etched (etchback processed) on the entire surface. This silicon oxide film is
For example, after coating with a film thickness of about 200 [nm], reactive sputter etching (RIE) is used to etch the surface by an amount corresponding to the deposited film thickness.

As shown in FIG. 9, the surface of the insulating film 21 thus formed is formed to have a height substantially equal to the surface of the insulating film 15 on the upper surface of the gate electrode 13 of the transfer MISFET Qt. As a result, the insulating film 21 has a load MI.
It is embedded between the lower layer protrusions that form the step shape of the base of the SFET Qp. In other words, the insulating film 21 is formed between the lower layer protrusions with a film thickness corresponding to the height of the lower layer protrusions or with a film thickness slightly lower than the height of the lower layer protrusions.

The insulating film 21 may be formed only on the memory cell array in which the stepped shape of the underlying layer grows, or may be formed not only on the memory cell array but on the entire surface of the substrate including the peripheral circuit region.

Next, after forming the connection hole 22 in the insulating film 21, as shown in FIG. 10, the load MISFET Qp is formed.
The gate electrode 23 and the intermediate conductive layer 23 are formed.

Next, the load MISF is formed on the insulating film 21 including both the gate electrode 23 and the intermediate conductive layer 23.
A gate insulating film 24 of ETQp is formed. The surface of the gate insulating film 24 is flattened because the step shape of the underlying layer due to the lower layer protrusions is relaxed.

Next, as shown in FIG. 11, the n-type channel forming region 26N, the source region 26P, the drain region 26P and the power supply voltage line 26P of the load MISFET Qp are formed on the gate insulating film 23. In these regions, first, an n-type impurity that adjusts the threshold voltage of the n-type channel forming region 26N is introduced over the entire surface of the polycrystalline silicon film deposited by the CVD method, and then a predetermined amount of the polycrystalline silicon film is formed. A p-type impurity that forms the source region 26P and the like is introduced into the region of 1) and is patterned into a predetermined shape. The introduction of the n-type impurities is performed by ion implantation. The p-type impurity is introduced by a mask formed by a photolithography technique (enclosed by a dashed line 26P in FIGS. 2 and 4 respectively).
A mask having an opening in the marked area) is used, and similarly, ion implantation is performed. The patterning of the polycrystalline silicon film is performed by anisotropic etching using a mask formed by a photolithography technique to achieve miniaturization.

In this patterning process of the polycrystalline silicon film, since the step shape of the underlayer is relaxed, the etching corresponding to the film thickness in the flat region of the polycrystalline silicon film is slightly overetched. Can be done with. Further, in the step of introducing impurities into the polycrystalline silicon film, since the step shape of the base is similarly relaxed, the impurities are surely introduced into almost the entire area.

After that, the interlayer insulating film 27, the first-layer metal wiring material (29), the interlayer insulating film 30, the second-layer metal wiring material (33), etc. are formed, so that the structure shown in FIG. Figure 2
The SRAM of this embodiment shown in FIG.

The SRAM of the first embodiment has the following operational effects.

(1) Lower layer protrusions (gate electrode 7, gate electrode 7, etc.) are formed on the first region of the base insulator (element isolation insulating film 4, insulating film 8 etc.).
13, the insulating films 8 and 15) are arranged, and the n-type channel forming region 26N of the load MISFET Qp is formed over the lower protrusion and the second region adjacent to and different from the first region of the base insulator. In an SRAM including a memory cell in which a semiconductor layer (polycrystalline silicon film) used as a memory cell is arranged, in a first region of the semiconductor layer used as the n-type channel formation region 26N of the load MISFET Qp of the memory cell. The difference between the height and the height in the second region is smaller than the height of the lower layer protrusion. With this configuration, it is possible to reduce the variation in the amount of current supplied from the power supply voltage Vcc of the flip-flop circuit of the memory cell to the information storage node region. Therefore, in the SRAM, excessive supply of current can be reduced and the amount of standby current can be reduced. Alternatively, it is possible to reduce insufficient supply of current and reduce defects in data retention characteristics. Reduction of the standby current amount is performed by SRA.
The power consumption of M can be reduced, and the reduction in the data retention failure can improve the operational reliability of the SRAM.

(2) Load MISFE having the above configuration (1)
The TQp has an offset structure in which the end of the drain region 26P on the gate electrode 23 side is separated from the end face of the gate electrode 23 on the drain region 26P side. With this configuration, the source region 26P of the load MISFET Qp is formed.
Since the punch-through breakdown voltage between the drain region 26P and the drain region 26P can be improved and the plane size of the load MISFET Qp can be reduced, the area occupied by the memory cell can be reduced and the SRAM can be reduced.
The degree of integration of can be improved.

(3) The semiconductor layer used as the n-type channel forming region 26N of the load MISFET Qp of the above structure (1) or structure (2) has a film thickness smaller than the height of the lower layer protrusion. To be done. With this configuration, the leak current between the source region 26P and the drain region 26P of the load MISFET Qp can be reduced, so that the standby current amount can be reduced and the power consumption of the SRAM can be reduced.

(4) MISFE for load of the above configuration (3)
The film thickness of the semiconductor layer used as the n-type channel forming region 26N of TQp is set within the range of 30 to 50 [nm]. With this configuration, the same action and effect as those of the configuration (3) can be obtained.

(5) The second region of the base insulator and the load MISFET Q according to any one of the configurations (1) to (4).
An insulator 21 is formed between the semiconductor layer used as the p-type n-type channel forming region 26N and the height of the lower-layer projections or slightly lower than that. With this configuration, in the second region of the base insulator, the n-type channel forming region 2 of the load MISFET Qp corresponding to the height of the lower layer protrusion of the first region is formed.
Since the height of the semiconductor layer used as 6N can be increased (becomes equal to or close to the height of the semiconductor layer in the first region, that is, the underlying layer can be flattened), the configurations (1) to (4) Any one of the above effects can be obtained.

(6) A lower layer protrusion is arranged on the first region of the base insulator, and the lower layer protrusion and the first portion of the base insulator are arranged.
Load M over the second area adjacent to and different from the area
In the method of forming an SRAM having a memory cell in which a semiconductor layer used as the n-type channel forming region 26N of the load MISFET Qp is disposed with the gate insulating film 24 of the ISFET Qp interposed, the following steps (A) to (A) (E) is provided. (A) A step of forming a lower layer protrusion on the first region of the base insulator, (B) A height substantially equal to or slightly lower than the height of the lower layer protrusion on the second region of the base insulator. Forming an insulator 21 having a film thickness, (C) forming a gate insulating film 24 of the load MISFET Qp on the entire surface of the insulator 21 including the first region and the second region, (D) the gate Insulating film 24
Forming a semiconductor layer used as the n-type channel forming region 26N of the load MISFET Qp on the entire upper surface, (E) first and second regions at least in the semiconductor layer
Applying residual patterning over the area, load M
A step of forming the n-type channel formation region 26N of the ISFET Qp. With this configuration, the step due to the lower layer protrusion is reduced in the insulator 21 formed in the step (B), the surface of the gate insulating film 24 formed in the step (C) is flattened, and the step is formed. Since a portion having an apparently thick film thickness along the step due to the lower layer protrusion of the semiconductor layer formed in (D) is eliminated, the flat region of either the first region or the second region of the semiconductor layer is eliminated. The patterning of the semiconductor layer in the step (E) can be performed under the etching condition according to the film thickness, and the overetching amount of the semiconductor layer can be reduced. This reduction in the over-etching amount of the semiconductor layer can prevent both the etching of the gate insulating film 24 below the semiconductor layer and the etching reaching the conductor layer (for example, the gate electrode 13 or 7 of the lower layer protrusion). A short circuit failure between the lower conductor layer and the semiconductor layer can be prevented.

(7) A lower layer protrusion is arranged on the first region of the base insulator, and the lower layer protrusion and the first portion of the base insulator are arranged.
Load M over the second area adjacent to and different from the area
SRA including a memory cell in which a semiconductor layer used as any one of the n-type channel forming region 26N, the source region 26P, and the drain region 26P of the ISFET Qp is arranged.
The method of forming M includes the following steps (A) to (D). (A) A step of forming a lower layer protrusion on the first region of the base insulator, (B) A height substantially equal to or slightly lower than the height of the lower layer protrusion on the second region of the base insulator. A step of forming an insulator 21 having a film thickness, (C) an n-type channel forming region 26N and a source region 26P of the load MISFET Qp on the insulator 21 over the entire surface including the first region and the second region. A step of forming a semiconductor layer used as one of the drain regions 26P, (D) forming any one of the n-type channel formation region 26N, the source region 26P, and the drain region 26P of the semiconductor layer. The step of introducing impurities by ion implantation. With this configuration, the step due to the lower layer protrusion is reduced in the insulator 21 formed in the step (B), the base of the semiconductor layer formed in the step (C) is flattened, and the semiconductor layer of the semiconductor layer is formed. Since a portion having an apparently thick film thickness along the step due to the lower layer protrusion disappears, it is possible to reduce the area of any one of the first area, the second area, and the area between the first area and the second area of the semiconductor layer. The film thickness can be formed substantially evenly, and impurities can be uniformly introduced into any region of the semiconductor layer in the step (D). The fact that impurities can be uniformly introduced into this semiconductor layer means that the n-type channel formation region 26N
In the case of introducing impurities into the semiconductor layer, since there is no region where the film thickness is thick due to the lower-layer projections of the semiconductor layer and no region where impurities are not introduced, the threshold voltage can be controlled in a stable manner. The reliability can be improved. Further, the fact that the impurities can be uniformly introduced into the semiconductor layer means that when the impurities are introduced into any one of the source region 26P and the drain region 26P, the thick region based on the lower-layer projection of the semiconductor layer disappears, and the impurities are removed. Since there is no region which is not introduced, disconnection defects can be prevented and the electrical reliability of the load MISFET Qp can be improved.

(Embodiment 2) The present embodiment 2 is similar to the memory cell of the SRAM of the above-described embodiment 1 in that the load MIS is used.
It is a second embodiment of the present invention, which describes another method for flattening the base of the FET Qp.

FIG. 12 (enlarged modeled sectional view) shows an essential part of the memory cell of the SRAM according to the second embodiment of the present invention.

The memory cell of the SRAM shown in FIG. 12A has an insulating film in which the lower-layer protrusions (gate electrode 13 and insulating film 15) have a small thickness and the lower-layer protrusions do not have a large thickness. 21C alleviates the step shape of the base of the load MISFET Qp. The insulating film 21C is deposited by the CVD method, and thereafter, the silicon oxide film (or the silicon nitride film) 21A is formed by anisotropic etching by an amount corresponding to the deposited film thickness, and the silicon oxide film deposited by the CVD method. Membrane 21
It consists of B.

The lower silicon oxide film 21A is formed as a so-called sidewall spacer on the side wall of the lower layer protrusion. This lower layer silicon oxide film 21A reduces the distance between adjacent lower layer protrusions and partially relaxes the stepped shape of the base.

The upper silicon oxide film 21B is formed to have a substantially uniform film thickness, but the lower silicon oxide film 21A partially relaxes the shape of the step of the base, and the distance between adjacent lower layer protrusions is small. Since it is reduced, the surface is flattened. The upper silicon oxide film 21B is preferably formed with a film thickness that is about ½ of the distance between the adjacent lower layer protrusions.

In the memory cell of the SRAM shown in FIG. 12B, the film thickness difference is different depending on the stepped shape of the base, and the surface is flat like the insulating film 21C shown in FIG. 12A. MISFET Q for load by the insulating film 21D to be formed
The stepped shape of the underlying layer of p is relaxed. Insulating film 21D is CV
It is formed of a BPSG film or a PSG film deposited by the D method, and the BPSG film or the PSG film is reflowed so that the surface is flattened.

The insulating film 21D has the same structure as that of the interlayer insulating film 27 of the SRAM of the first embodiment, so as to prevent leakage of either B or P of the BPSG film or P of the PSG film. A two-layer structure in which a silicon oxide film having a dense film quality is used as an underlayer may be used.

In the memory cell of the SRAM shown in FIG. 12C, dummy lower layer protrusions (13D and 15D) for the purpose of flattening are arranged between the lower layer protrusions, and these are arranged in the insulating film 21E. MISFE for load by coating with
The step shape of the base of TQp is relaxed. As the insulating film 21E, for example, a silicon oxide film deposited by a CVD method or a sputtering method is used.

Although not shown, S in the first embodiment described above is not shown.
Similar to the structure of the interlayer insulating film 30 of the RAM, a load MISFE is formed by a three-layer insulating film in which a deposition type silicon oxide film, a coating type silicon oxide film, and a deposition type silicon oxide film are sequentially stacked.
The step shape of the base of TQp may be relaxed. in this case,
The coating type silicon oxide film of the intermediate layer may or may not be subjected to an etch back process. The lower-layer and upper-layer deposition-type silicon oxide films are not limited to tetraethoxysilane gas, but may be deposited by a CVD method using an inorganic silane gas as a source gas.

The SRAM of the second embodiment is the same as that of the first embodiment.
Substantially the same operation and effect as the SRAM can be obtained.

The inventions made by the present inventor are as follows.
Although the present invention has been specifically described based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.

[0130] For example, the present invention is not limited to the above SRAM, DRAM (D ynamic R andom A ccess M emory),
ROM (R ead O nly M emory ) , etc., so-called SOI (S ili
con O n I nsulator) semiconductor memory using the technology, the logic LSI, microprocessor, MOSIC, CMOS
-Applicable to bipolar transistor mixed type semiconductor integrated circuit devices (Bi-CMOS) and the like.

The present invention also provides a p-channel MISFET.
However, the present invention can be applied to not only the n-channel MISFET but also the p-channel MISFET and the n-channel MISFET at the same time.

Further, according to the present invention, the MISFE in which the gate electrode, the gate insulating film, and the channel forming region are sequentially laminated is provided.
Not only T but also a gate insulating film and a gate on the channel formation region.
It may be applied to a MISFET in which the respective gate electrodes are sequentially laminated.

The present invention is not limited to MISFETs,
For example, in an SRAM composed of a high resistance load type memory cell, it can be applied to the high resistance load element. The high resistance load element is formed of, for example, a semiconductor layer of any one of a polycrystalline silicon film, an amorphous silicon film, and a single crystal silicon film.
It is formed on the lower layer protrusion such as the upper portion of the SFET. In this case, as in the above-described embodiments, the high resistance load element arranged on the region where the step shape of the base is relaxed can reduce the amount of standby current or prevent the data retention characteristic from being defective.

[0134]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) In a semiconductor integrated circuit device in which a MISFET is arranged above a step of a base, the MISFET
The electrical reliability of can be improved.

(2) In a semiconductor integrated circuit device having an SRAM in which a MISFET as a load element of a memory cell is arranged above a step of a base, at least one of reduction of power consumption and improvement of operation reliability of the SRAM is required. Can be achieved.

(3) In addition to the effect (2), the SRA
The degree of integration of M can be improved.

(4) Electrical reliability can be improved in a semiconductor integrated circuit device having a semiconductor layer as a resistance element above a step of a base.

(5) In the semiconductor integrated circuit device in which the MISFET is arranged above the step of the base, the MISFET
Optimization can be achieved when patterning any of the channel forming region, the source region, and the drain region.

(6) In the semiconductor integrated circuit device in which the MISFET is arranged above the step of the base, the MISFET
Optimization can be achieved when introducing impurities into any of the channel forming region, the source region, and the drain region.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a SRAM memory cell according to a first embodiment of the present invention.

FIG. 2 is a plan view of the memory cell.

FIG. 3 is a plan view of the memory cell in a predetermined manufacturing process.

FIG. 4 is a plan view of the memory cell in a predetermined manufacturing process.

FIG. 5 is an equivalent circuit diagram of the memory cell.

FIG. 6 is an enlarged cross-sectional view modeling a main part of the memory cell.

FIG. 7 is an enlarged cross-sectional view modeling a main part of the memory cell.

FIG. 8 is a characteristic diagram illustrating the effect of the first embodiment of the present invention.

FIG. 9 is a sectional view in a first step illustrating a method for forming the SRAM.

FIG. 10 is a sectional view of a second step.

FIG. 11 is a sectional view in a third step.

FIG. 12 is an enlarged cross-sectional view modeling a main part of an SRAM memory cell according to a second embodiment of the present invention.

[Explanation of symbols]

1 ... Semiconductor substrate, 2 ... Well region, 4 ... Element isolation insulating film, 6, 12, 24 ... Gate insulating film, 7, 13, 23 ...
Gate electrodes, 8, 15, 21, 21A to 21E ... Insulating film, 9, 16 ... Sidewall spacers 10, 11,
17, 18 ... Semiconductor region, 26N ... Channel formation region,
26P ... Source region or drain region, 13D, 15D
… Dummy protrusion, Q… MISFET.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Eri Fujita             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Date             Tachicho LSI Engineering             Within the corporation (72) Inventor Yu Hoshino             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony company Hitachi Ltd. Musashi factory (72) Inventor Kazushige Sato             4026 Kujimachi, Hitachi City, Ibaraki Japan             Tachi Works Hitachi Research Laboratory (72) Inventor Masato Takahashi             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony company Hitachi Ltd. Musashi factory (72) Inventor Ryuichi Izawa             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony company Hitachi Ltd. Musashi factory (72) Inventor Keiichi Yoshizumi             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony company Hitachi Ltd. Musashi factory (72) Inventor Norio Suzuki             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony company Hitachi Ltd. Musashi factory (72) Inventor Takayuki Kanda             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony company Hitachi Ltd. Musashi factory (72) Inventor Isamu Kuramoto             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony company Hitachi Ltd. Musashi factory (72) Inventor Yasuko Yoshida             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony company Hitachi Ltd. Musashi factory (72) Inventor Soichiro Hashiba             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony company Hitachi Ltd. Musashi factory (72) Inventor Chiemi Mori             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Date             Tachicho LSI Engineering             Within the corporation (72) Inventor Hiroshi Matsuki             Hitachi 3-10-2 Bentencho, Hitachi City, Ibaraki Prefecture             Haramachi Electronics Co., Ltd. (72) Inventor Seiichi Ariga             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Date             Tachicho LSI Engineering             Within the corporation (72) Inventor Shuji Ikeda             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony company Hitachi Ltd. Musashi factory

Claims (10)

[Claims] 1. A lower layer protrusion is disposed on the first region of the base insulator, and the lower layer protrusion and the first of the base insulator are provided.
MISF over a second area adjacent to and different from the area
In a semiconductor integrated circuit device in which a semiconductor layer used as a channel formation region of ET is arranged, the MISFE
First semiconductor layer used as T channel formation region
A semiconductor integrated circuit device, wherein a difference between a height in the area and a height in the second area is smaller than a height of the lower layer protrusion. 2. The MISFET according to claim 1,
A semiconductor integrated circuit device, which is a load element of a flip-flop circuit of an SRAM memory cell. 3. The MISFET according to claim 2,
A semiconductor integrated circuit device comprising an offset structure in which an end of the drain region on the side of the gate electrode is separated from an end face of the gate electrode on the side of the drain region. 4. The MI according to claim 2 or claim 3.
The semiconductor integrated circuit device according to claim 1, wherein the semiconductor layer used as the channel formation region of the SFET has a film thickness smaller than the height of the lower layer protrusion. 5. The semiconductor layer used as a channel formation region of the MISFET according to claim 4, is 5 to 50.
A semiconductor integrated circuit device, wherein the film thickness is set within a range of [nm]. 6. The height of the lower layer protrusion is between the second region of the base insulator according to claim 1 and the semiconductor layer used as the channel formation region of the MISFET. The semiconductor integrated circuit device is characterized in that an insulator having a film thickness that is substantially equal to or slightly lower than that is formed. 7. Between the underlying insulator according to claim 1 and a semiconductor layer used as a channel formation region of a MISFET, the lower layer protrusions of the first region and the semiconductor layer used as the channel formation region of the MISFET are formed. A thin film between the semiconductor layer and the second
A semiconductor integrated circuit device comprising an insulator having a large film thickness between a base insulator in a region and the semiconductor layer. 8. A lower-layer protrusion is disposed on the first region of the base insulator, and the lower-layer protrusion and the first portion of the base insulator are disposed.
In a semiconductor integrated circuit device in which a semiconductor layer used as a resistance layer is arranged adjacent to a region and over a different second region, the height of the semiconductor layer used as the resistance layer in the first region and A semiconductor integrated circuit device characterized in that the difference between the heights of the two regions is smaller than the height of the lower layer protrusions. 9. A lower layer protrusion is disposed on the first region of the base insulator, and the lower layer protrusion and the first region of the base insulator are arranged.
MISF over a second area adjacent to and different from the area
In a method of forming a semiconductor integrated circuit device in which a semiconductor layer used as a channel formation region of this MISFET is arranged with a gate insulating film of ET interposed, the following step (A)
To (E) are provided. (A) a step of forming a lower layer protrusion on the first region of the base insulator, (B) a height substantially equal to or slightly lower than the height of the lower layer protrusion on the second region of the base insulator Thickness insulator or second region of the underlying insulator and MISFE
A step of forming an insulator with a semiconductor layer used as a channel formation region of T, the thickness of which is thicker than the thickness between the lower layer protrusion of the first region and the semiconductor layer; ) Forming a gate insulating film of the MISFET on the entire surface of the insulator including the first region and the second region, (D) Semiconductor used as a channel forming region of the MISFET on the entire surface of the gate insulating film A step of forming a layer, (E) at least the semiconductor layer is subjected to residual patterning over the first region and the second region, and MISFET is formed.
Forming a channel formation region of. 10. A lower layer protrusion is disposed on the first region of the base insulator, and the MIS is formed on the lower layer protrusion and a second region adjacent to and different from the first region of the base insulator.
A method of forming a semiconductor integrated circuit device in which a semiconductor layer used as any one of a channel formation region, a source region, and a drain region of an FET is arranged, comprising the following steps (A) to (D): To do. (A) a step of forming a lower layer protrusion on the first region of the base insulator, (B) a height substantially equal to or slightly lower than the height of the lower layer protrusion on the second region of the base insulator Thickness insulator or second region of the underlying insulator and MISFE
A step of forming an insulator with a semiconductor layer used as a channel formation region of T, the thickness of which is thicker than the thickness between the lower layer protrusion of the first region and the semiconductor layer; ) A channel forming region of the MISFET is formed on the entire surface of the insulator including the first region and the second region,
A step of forming a semiconductor layer used as either a source region or a drain region, (D) a channel forming region of the semiconductor layer, a source region,
A step of ion-implanting an impurity forming any one of the drain regions.