JPH0514326A - Phase correction circuit between clock and data - Google Patents

Abstract

(57) [Abstract] [Purpose] To reduce data transmission failure in serial data transmission line using discontinuous clock. A serial data transmission line that uses a discontinuous clock is used between the transmission device 1 and the transmission relay device 2 and between the transmission relay device 2 and the reception device 3. Misalignment may occur. Therefore, a method is provided in which a phase correction circuit between clock and data is provided in the transmission relay device 2 and the phase difference when the transmission relay device 2 receives is corrected and transmitted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer system on a transmission line.

[0002]

2. Description of the Related Art A conventional phase correction technique between clock and data is disclosed in Japanese Patent Laid-Open No. 58-101595. However, this method only considers the transfer of continuous clocks.

[0003]

The above-mentioned prior art has not taken into consideration the case of transmitting serial data with a discontinuous clock.

An object of the present invention is to solve the above problems and to operate regardless of the number of transmission words.

[0005]

In order to achieve the above object, the present invention detects the end of a received discontinuous clock,
In addition, during that time, the data to be received is accumulated, and the data is transmitted in the same cycle as the reception clock but in phase with the transmission clock having a different phase.

[0006]

The clock received by the transmission repeater is an arbitrary discontinuous clock, and the data attached to it is synchronized with the falling edge of the clock. The present invention detects the start and end of the clock received by the transmission repeater. Then, hold the reception data in the data register for the time to detect the end and the time to synchronize with the transmission clock with the same cycle as the reception clock but a different phase, and after the above time, match the phase with the transmission clock
It operates to transmit sequentially.

For this reason, even if the number of data transmission words is variable, if the received data can be latched in the data register, the transmission clock is generated in this circuit, and therefore no malfunction occurs.

[0008]

Embodiments of the present invention will be described below with reference to FIGS.

FIG. 1 shows a system block diagram. This system includes a transmission device 1, a transmission relay device 2, and a reception device 3. Cables are connected between the respective devices.

FIG. 2 shows a block diagram of the transmission relay device.
This includes a clock number detection circuit 21, a data acquisition clock generation circuit 22, a 4-bit data register 23, 4-
1 selector 24, a clock buffer 25, and a data buffer 26.

In FIG. 1, a transmitter 1 and a transmission repeater 2
And the transmission relay device 2 and the reception device 3 are serial data transmission interfaces, and the transmission clock and data are shown in FIG.
, RCK and RDAT, the clock is discontinuous, the duty is 50%, and the data is synchronized with the falling edge of the clock. Next, the operation of each part in FIG. 2 will be described.

The clock number detection circuit 21 receives the received clock R
The number of CK clocks is transmitted to the transmission repeater internal clock SCK0
The number of clocks of the reception clock RCK is detected by performing a count comparison with and the transmission clock SCK1 and the transmission data SDAT are controlled based on the detected number of clocks. The data acquisition clock generation circuit 22 uses the reception clock RC
The data latch timing of the 4-bit data register 23 is created from K. The 4-bit data register 23 is a data register that latches the reception data RDAT in 4-bit parallel at each data latch timing created by the data fetch clock creation circuit 22, and holds the received data until the transmission timing. 4-1 Selector 2
A register selection signal 4 selects data by a register selection signal created by the clock number detection circuit 21. The clock buffer 25 and the data buffer 26 are the clock number detection circuit 2
By the transmission control signal created in 1, the transmission clock SCK
1. A gate for controlling transmission of the transmission data SDAT.

A data acquisition clock generation circuit 22,
The operation of the clock number detection circuit 21 will be described in detail.

FIG. 3 shows a block diagram of a data fetch clock generation circuit. Further, FIG. 4 shows an operation timing chart when the number of transmission data is eight. In the initial state of this circuit, DF. F. The Qn output of 222 is 1. When the reception clock RCK is received, DCK0 changes from 0 → 1 at the rising of the first clock, and DCK changes from 0 → 1 at the second clock. At this time, DF. F. 222
1 is set to the D input of the receiving clock RCK and the Qn is changed from 1 to 0 at the second clock of the receiving clock RCK, and the receiving clock RC
At the 3rd clock of K, DCK2 goes from 0 to 1 and DCK0 goes to 1
→ Change to 0. DCK3 is 0 at the 4th clock →
1, DCK1 changes from 1 to 0, and at this time, DF. F. Two
The D input of 22 becomes 0, and Qn changes from 0 to 1 at the fourth clock of the reception clock RCK. The same operation is performed after the fifth clock.

DCK0 to DCK3 are latch timings of the 4-bit data register shown in FIG. 2, and the 4-bit data register takes in data at the rising edge of each DCK. Therefore, since one cycle of operation is performed with the reception clock RCK4 clocks, even if the number of clocks is an arbitrary value, it is possible to capture it in the data register.

FIG. 5 shows a block diagram of the clock number detection circuit. This circuit includes SR-FF 210, DF. F. 21
0-213,217-219, CNT214,215,
It is composed of a CMP 216 and AND gates 21a to 21e. Further, FIG. 6 shows an operation timing chart of clock number detection when the number of transmission data is five. The transmission relay device internal clock SCK0 and the reception clock RCK have the same cycle and the same duty, but SCK0 is a continuous clock and RCK is a discontinuous clock, and the phase difference is not guaranteed. F.
F. 210 to 213 hold the synchronization of the reception clock RCK with the internal clock SCK0 and the clock length. RC
When receiving K. F. 210 changes from 0 to 1,
F. F. 211 to 213 are F.I. F. 210 output and SC
SCK0n, which is 180 ° out of phase with K0 and SCK0, causes a sequential change from 0 to 1. The CNT 214 counts the number of clocks of the reception clock RCK, and the CNT 215 sets the F.
The number of clocks of the internal clock SCK0 is counted from the output timing of F.212. The CNT 214 is always enabled, that is, always in the RCK receivable state.
It changes in the order of 0 → 1 → 2 → 3 → 4 → 5 by K, and holds that value after receiving the last clock. CNT
215 is F.I. F. The output of 212 (@) is enabled, that is, it is delayed by 1 to 2 clocks from CNT 214, and changes from 0 → 1 → 2 → 3 → 4 → 5 by SCK0.
The values of CNT 214 and CNT 215 coincide with each other one or two clocks after the end of RCK reception. CNT214 and CNT2
The value of 15 is compared by CMP216, and when it becomes the same value, R
Detect clock end of CK. Here, both sides'
When it becomes 5 ', it will be detected. AND gate 4
The condition in the output of FF.213 of 1d indicates that RCK is being received, and FF217-219 and AND gate 21e are outputting the clock end detection pulse by the leading edge differential.
As a result, the F. F. 210 is reset and F. F.
211 to 213 also change from 1 to 0, and the F.D. F. 211 and F.I. F. The transmission enable is created from 213, and the transmission clock SCK1 is created from SCK0n by the AND gate 21c. Further, SEL0, 1 which is the lower 2 bits of the output of the CNT 215 is the 4-1 selector 2 of FIG.
4 is used as a control signal. It should be noted that this circuit is initialized after the completion of one operation and is in a state of waiting for RCK reception.

Next, the transmission data will be described. FIG. 7 shows a block diagram of the 4-bit data register and the 4-1 selector. This circuit is a DF. F. 4 consisting of 231-234
It is composed of a bit data register and a 4-1 selector for selecting a register. Further, FIG. 8 shows an operation timing chart of the data transfer circuit when the number of transmission data is five. The DCK0 to 3 generated by the data acquisition clock generation circuit of FIG. F. 231 to 234 are sequentially fetched, but since there are five data, the data D4 is D-
F. F. 231 is taken in. Each DF. F. While holding data for four clocks, the data register selection signals SEL0, SEL0, generated by the clock number detection circuit of FIG.
DF. F. 231-234 is selected and transmission data SDAT is created. The selection signals SEL0 and SEL1 are sent with a delay of 1 to 2 clocks from the received data RDAT, and each data is held for 4 clocks, so that it can be selected without fail. Further, since the selection signals SEL0 and SEL1 are synchronized with SCK0, the transmission data SDAT has the transmission clock SC.
It is transmitted in synchronization with the falling edge of K1.

[0018]

According to the present invention, the erroneous reception of data is reduced by correcting the phase between the clock and the data during data transmission, and the transmission path is extended if the probability of erroneous reception is the same. Is possible.

Further, even if the number of data transmission words is variable, it is possible to perform phase correction before transmission.

[Brief description of drawings]

FIG. 1 is a system block diagram of an embodiment of the present invention,

2 is a block diagram of the transmission relay device shown in FIG. 1;

FIG. 3 is a circuit diagram of a data acquisition clock generation circuit of FIG. 2;

FIG. 4 is an operation timing chart of FIG.

FIG. 5 is a clock number detection circuit diagram of FIG. 2;

6 is an operation timing chart of FIG.

7 is an explanatory diagram of a 4-bit data register and a 4-1 selector of FIG. 2,

8 is an operation timing chart of FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Transmitting device, 2 ... Transmission relay device, 3 ... Receiving device, 21
... Clock number detection circuit 22 ... Data acquisition clock generation circuit, 23 ... 4-bit data register, 24 ... 4-1 selector.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Yuji Izumida             Stock number 5-22-1, Kamimizuhonmachi, Kodaira-shi, Tokyo             Hitachi Microcomputer System Co., Ltd. (72) Inventor Hisaki Mie             216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa             Hitachi, Ltd. Totsuka factory

Claims (2)

[Claims] 1. A transmission relay device between two devices having a serial data transmission path in which a clock having a clock falling edge synchronizing with data and a duty of 50% is provided only during transfer of valid data, and receiving the end of the reception clock. Independent of the clock, means for detecting by counting and comparing with a continuous internal clock, means for accumulating received data in a data register by the clock created by the receive clock, and internal according to the order in which the accumulated data is received A clock characterized by having means for correcting the phase between the data and the clock with the clock and transmitting the data.
Phase correction circuit between data. 2. A phase correction circuit between clock and data according to claim 1, wherein even if the number of data transmission words is an arbitrary value, it is possible to perform phase correction before sending.