JPH05143449A - Main memory data write control method - Google Patents

Abstract

(57) [Summary] [Object] The present invention relates to a main memory data write control method executed at the time of issuing a store instruction, and an object thereof is to realize speeding up of subsequent access request processing. A central processing unit searches whether or not data to be written is held in a cache according to a preceding pipeline processing, and writes the write data to a main storage device according to a succeeding pipeline processing. In the main memory data write control method of issuing the request and writing the write data to the cache when it is determined that the data to be written is held, the data is written to the cache according to the preceding pipeline processing. When it is determined that the data to be embedded is held, the access request to the subsequent cache is prohibited and the subsequent pipeline processing is executed. On the other hand, when it is determined that the data is not held , While permitting subsequent access requests, processing is performed so as to start execution of the subsequent pipeline processing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention, when a store instruction is issued,
The present invention relates to a main memory data write control method executed when writing main memory data to a cache memory and a main memory device, and more particularly to a main memory data write control method capable of realizing speeding up of subsequent access request processing. Is.

In the data processing device, the central processing device is provided with a cache memory for temporarily holding a copy of the main memory data so that the main memory data can be obtained without accessing the main memory device. The configuration is set to. On the other hand, the program running on the central processing unit rewrites the main memory data of the main memory device by issuing the store instruction. When this store instruction is issued and the data to be stored is held in the cache memory, the configuration is such that the store data is also written to the cache memory. , It is necessary to prevent other access request processing from being wasted.

[0003]

2. Description of the Related Art FIG. 5 shows a system configuration of a data processing device. As shown in this figure, the data processor
Central processing unit 1, main memory control unit 2, main memory unit 3
It is composed of and.

The central processing unit 1 includes an I unit and an E unit.
The I unit issues a main memory data reference request or a store data write store request to the S unit. The E unit issues its store data to the S unit,
The unit receives the main memory data reference request issued by the I unit, reads the data with the reference request from the cache memory 4, and notifies the I unit and the E unit of the data.
Further, in response to the store request issued by the I unit and the E unit, the store data is written in the cache memory 4 and the store request is issued to the main storage controller 2.

Here, the "ST The REQ ”signal is
The store request issued by the I unit, "REQ ADR
The "S" signal is the address information "REQ" issued by the I unit that specifies the access destination of the store request or reference request.
The "VLD" signal is validity information issued by the I unit indicating the validity of the store request or the reference request.

In the S unit of the central processing unit 1, the cache memory 4 is controlled in accordance with the pipeline configuration, and the store instruction is stored in the cache memory 4 in accordance with the two processing flows of the first flow and the second flow. It adopts a control structure. That is, when a store instruction is issued, it is searched in the first first flow whether or not the data to be stored is held in the cache memory 4, and in the next second flow, the main storage control device 2 is searched.
A store request is issued by specifying store data and a store address, and the store data is written in the cache memory 4.

Next, according to FIG. 6, this store instruction is issued.
Control of conventional cache memory 4 when executed
The processing will be described in detail. In FIG. 6, 4a is a cache
Cache data array forming the memory 4 and 4b
Is the cache directory that constitutes the cache memory 4.
3 and 5 are store request generation circuits, which are main memory control devices.
Generating a store request for the device 2, 6 is the first
A selector, which is the above-mentioned requester issued by the I unit.
Dress (REQ ADRS signal) and the first store process
One of the store addresses returned by the flow
It is selected and put into the pipeline.

Reference numeral 7 denotes a comparator, which compares the tag information from the cache directory 4b read by the index address of the address selected by the first selector 6 with the corresponding portion of the selected address. In this way, it is determined whether or not the data to be accessed is held in the cache data array 4a. Reference numeral 8 is a second selector, which is determined by the index address of the address selected by the first selector 6. The cache data to be accessed included in the cache data read from the cache data array 4a is selected.

Reference numeral 9 denotes a first AND circuit, which stores the above-mentioned store request (ST) from the I unit when the execution of the first state of the second flow of the store processing is not started.
REQ signal) and valid information (REQ VLD signal) and outputs a high level value when
Is a second AND circuit, and when I is not in execution of the first state of the second flow of the store processing, I
From the unit, the above valid information (REQ VLD signal)
That outputs a high level value when is sent, 11
Is an inverter circuit, and when the execution of the first state of the second flow of the store processing is not started,
And a high level value is output to the second AND circuits 9 and 10.

“W · S / DR” is a register for latching store data issued by the E unit in each pipeline state, and “T · B · R / AR” is an address selected by the first secreter 6. It is a register that latches in each pipeline state. The address output from this final stage "R / AR" is returned to the first selector 6 as a store address. “B / MR” is a register for latching the comparison result of the comparator 7 in the B state of pipeline processing, and “CDR” is a register for latching the cache data selected by the second selector 8.

"T / B / R / ST" is a register for indicating the first flow of the store processing by latching the store request information output from the first AND circuit 9 in each pipeline state. Is. The final stage "R / S"
The output value of T "(used as an input to the inverter circuit 11; (Called REQ signal)
The execution end of the first flow of the store processing, that is, the execution start of the second flow is displayed. "T / B / R / V
LD "is a register that indicates the validity of each request processing sent from the I unit by latching the valid information output from the second AND circuit 10 in each pipeline state," WS-VLD ". Is the HI output by "R / ST" It is a register that indicates the validity of the second flow of the store processing by latching the REQ signal in each pipeline state.

In the conventional structure having such a structure,
When the I unit issues a store request by designating the request address (which becomes the store address) and the valid information, the first flow of the store process is executed. That is, the cache directory 4b is indexed by the request address output from the first selector 6 while turning on the valid flags of "T.B.R / ST" and "T.B.R / VLD" of each state. The comparator 7 determines whether or not the data to be stored is held in the cache data array 4a, and at the end of this first flow, the HI output by "R / ST" is output. RE
The store address is notified to the store request generation circuit 5 according to the synchronization signal of the Q signal.

End of execution of the first flow of this store processing,
That is, the E unit issues store data in synchronization with the start of execution of the second flow. That is, the first selector 6 outputs the HI output by "R / ST". The store address output by "R / AR" is selected according to the REQ signal, and the valid flag of "WS / VLD" in each state is set to O.
While setting to N, the store data is written in the cache data array 4a in accordance with the store address output from the first selector 6, and the store request generation circuit 5 is notified of this store data.

In this way, the end of execution of the first flow,
That is, when the store address and the store data are notified at the start of execution of the second flow, the store request generation circuit 5
Will issue a store request to the main storage controller 2 by designating the store data and store address.

Here, when the data to be stored is not held in the cache data array 4a in the first flow, there is no need to rewrite the data in the cache data array 4a in the second flow, so in practice, The write processing of the store data to be executed in the S cycle of the second flow is suppressed.

[0016]

As described above, in the prior art, the HI which outputs the selection processing of the first selector 6 by "R / ST" is output. The control is performed according to the REQ signal. That is, regardless of whether the data to be stored is held in the cache data array 4a,
When the execution of the first flow of the store process is completed, that is, when the execution of the second flow is started, the input of the request address of the subsequent access request is uniformly eliminated.

From now on, as shown in the time chart of FIG. 7, for example, when there is a fetch request such as fetch 1, fetch 2, and fetch 3 following the store request from the I unit, the [α] part in the figure As shown in the drawing, even if the data to be stored is not held in the cache data array 4a, the processing of fetch 3 overlapping with the first state of the second flow of the store request is waited for one state. There was a problem. That is, when the data to be stored is not held in the cache data array 4a, the cache data array 4
Since it is not necessary to write the store data in a, there is a problem that the subsequent access request can be immediately accepted, but the access request is made to wait.

The present invention has been made in view of the above circumstances, and when the store data is written to the cache memory and the main storage device at the time of issuing the store instruction, the subsequent access request processing is speeded up. It is an object of the present invention to provide a new main memory data write control method that can be realized.

[0019]

FIG. 1 illustrates the principle configuration of the present invention. In the figure, 1 is a central processing unit, 2 is a main memory control unit, and 3 is a main memory unit.

An access request unit 20 provided in the central processing unit 1 issues a reference request for main memory data or a store request for writing store data. Reference numeral 21 denotes a cache control unit included in the central processing unit 1, which is composed of a pipeline and is used when the access request unit 20 issues a reference request for main storage data.
The access request unit 20 reads out data for which a reference request has been made from the cache memory configured by the cache data array 22a and cache directory 22b.
Will be notified to.

When the access request unit 20 issues a store request, the cache control unit 21 searches for whether or not the data to be stored is held in the cache memory according to the preceding pipeline process, and executes the subsequent process. A store data write request is issued to the main storage controller 2 according to the pipeline processing, and it is determined that the data to be stored is held in the cache memory based on the search result of the preceding pipeline processing. When writing, store data is written in the cache memory.

In order to execute this control process, the cache control unit 21 selects one of the request address issued by the access request unit 20 and the store address returned from the preceding pipeline process, and puts it in the pipeline. The input selection unit 23, the store request issuing unit 24 that issues a store request to the main storage controller 2 in response to the store request issued by the access request unit 20, and the store address and store data in the store request issuing unit 24. And a control unit 25 for controlling the selection processing of the selection unit 23 according to the search information as to whether the store address is managed by the cache directory 22b.

[0023]

In the present invention, when issuing a store request, the access request unit 20 first issues a store address as a request address, and then this store address is the R state of the pipeline of the cache control unit 21. The store data to be written is issued in synchronism with the time when it is returned to the selection unit 23 from. On the other hand, the control unit 25
Is a request address issued by the access requesting unit 20 by the selecting unit 23 when a store request that causes a cache hit (holds data to be stored in the cache data array 22a) in the R state of the pipeline has not been input. Control to select.

From now on, when the access request unit 20 issues a store address as a request address, the selection unit 23
Receives the issued store address into the pipeline, and in response to this input process, searches the cache directory 22b for whether or not the data to be stored is held in the cache data array 22a and controls it. The section 25 receives this search result, and when the store address flows into the R state of the pipeline,
The store request issuing unit 24 is instructed to read the store address.

The store address sent to the R state of this pipeline is returned to the selection unit 23, but the control unit 25 controls the cache directory 22b.
Is holding the data to be stored, the selection unit 2
3 controls so that the request address of the subsequent access request issued by the access request unit 20 is kept waiting and selects this store address, and when it is not held, this store address is eliminated and the subsequent request address is immediately selected. Control to continue.

Upon receiving the instruction to select the store address, the selecting unit 23 inputs the returned store address into the pipeline, and in response to this input processing, the cache data array 22a specifies the store address. By writing the store data issued by the access requesting unit 20 in the management area, the data to be stored is updated. On the other hand, when receiving the selection instruction of the request address of the subsequent access request, the selection unit 23 immediately inputs the subsequent request address issued by the access request unit 20 into the pipeline. When the store request issuing unit 24 receives the store data issued by the access requesting unit 20 and the store address at the same time, the store request issuing unit 24 issues a store request to the main storage controller 2 by designating the store address and the store data. I will issue it.

As described above, according to the present invention, when the data to be stored is not held in the cache data array 22a, the processing of the subsequent access request issued by the access request unit 20 is immediately executed without waiting. I will do it.

[0028]

EXAMPLES The present invention will be described in detail below with reference to examples. FIG. 2 illustrates one embodiment of the present invention. In the figure, FIG.
The same components as those described in 1 are indicated by the same symbols, and the signals indicated by or have the same signal contents.

"R / MR" means "B / M" described in FIG.
A register for latching the latched data of "R" in the R state of the pipeline processing, 12 is an inverter circuit for inverting the output value of "R / MR", and 13 is an output value of "R / MR" and described in FIG. A third AND circuit which outputs a logical product value signal with the output value of “R / ST”
/ MR "and" R / ST "both output a high level value when they output a high level value, that is, the third AND circuit 13 is an access target of the cache data array 4a. A high level value is output at the end of execution of the first flow of the store process when data is held. It is called a REQ signal.

Reference numeral 14 indicates the output value of the inverter circuit 12 and "R".
4th which outputs a logical product value signal with the output value of / ST "
It is an AND circuit, and the inverter circuit 12 and "R / S
High level when both T ”output high level value
It outputs a value. That is, this fourth AND
Circuit 14 accesses cache data array 4a
The number of store processing when the target data is not retained
Outputs a high level value at the end of execution of one flow
It is something. Below, this logical product value signal is REQ
It is called a signal.

Reference numeral 15 is an OR circuit which outputs a logical sum value signal'of the output value of the third AND circuit 13 and the output value of the fourth AND circuit 14, and HA REQ signal or HB R
A high level value is output when either one of the EQ signals outputs a high level value. That is, the OR circuit 15 outputs a high level value at the end of execution of the first flow of the store processing. This logical sum signal 'is the HI signal described in FIG. Since it has the same meaning as the REQ signal, HI It will be referred to as the REQ signal.

In the present invention, the output of the third AND circuit 13
HA to do Selection of the first selector 6 by the REQ signal
HA has a configuration that controls processing. REQ signal
When the high level value is displayed on the
The store address returned from the row is selected and T / A
The configuration output to R is adopted. Therefore, in the first flow
Cache data array 4 even at the end of execution
If the data to be accessed is not stored in a
Is the request address issued by the I unit described in FIG.
(REQ ADRS signal) is selected and output to T / AR
It will be empowered. Then, according to this configuration, the book
In the invention, HI This HA instead of the REQ signal R
A configuration in which the EQ signal is input to the inverter circuit 11
It is taken. For the store request generation circuit 5,
Ends the execution of the first flow of the store process, that is, the second flow
Store address and store data at the start of flow execution
Since there is no change in the notification of
HI REQ signal 'is input as a synchronization signal
It will be.

Next, the operation processing of the embodiment configured as described above will be described. When the I unit described in FIG. 5 issues a store request by designating the request address (which becomes the store address) and the valid information, the first flow of the store process is executed. That is, "T ・ B ・ R / ST" and "T ・ B ・ R" of each state
Whether the cache directory 4b is indexed by the request address output from the first selector 6 while the valid flag of "/ VLD" is turned on, and the comparator 7 holds the data to be stored in the cache data array 4a. Whether or not the HI output from the OR circuit 15 is output at the end of this first flow. The store address is notified to the store request generation circuit 5 in accordance with the synchronization signal of the REQ signal '.

At the end of execution of the first flow of the store processing, that is, at the start of execution of the second flow, E described in FIG.
When the unit issues store data and the data to be stored is held in the cache data array 4a, HA Since the first selector 6 selects the store address output by “R / AR” according to the high level value display of the REQ signal, the “W · S / V” of each state is selected.
Since the store data is written to the cache data array 4a in accordance with the store address output from the first selector 6 while the LD "valid flag is turned on, the store data is notified to the store request generation circuit 5. is there.

On the other hand, when the data to be stored is not held in the cache data array 4a, HA
According to the low level value display of the REQ signal, the first selector 6 requests the request address (REQ) of the subsequent access request issued by the I unit. Since the ADRS signal) is selected, the data held in the cache data array 4a can be stored with the request address output from the first selector 6 while turning on the "T / B / R / VLD" valid flag of each state. Subsequent access request processing is executed by reading and the store data issued by the E unit is sent to the store request generation circuit 5 at the end of execution of the first flow of the store processing, that is, at the start of execution of the second flow. I will notify you.

In this way, the execution of the first flow is completed,
That is, when the store address and the store data are notified at the start of execution of the second flow, the store request generation circuit 5
Will issue a store request to the main storage controller 2 by designating the store data and store address.

As described above, according to the present invention, for example, when there is a fetch request such as fetch 1, fetch 2, and fetch 3 subsequent to the store request from the I unit, and a cache hit occurs, the case of FIG. As shown in the time chart, as in the conventional technique, as indicated by the part [α] in the figure, the cache 3 waits for the fetch 3 processing overlapping with the first state of the second flow of the store request. In the case of a mishit, as shown in the time chart of FIG. 4, the fetch 3 process is controlled so as not to wait.

[0038]

As described above, according to the present invention,
When the store data is written to the cache memory and the main storage device when the store instruction is issued, if the data to be stored is not held in the cache memory,
Since the configuration is such that the subsequent access request process is executed immediately without waiting, the subsequent access request process can be executed at high speed.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is an example of the present invention.

FIG. 3 is a time chart in the case of a cache hit.

FIG. 4 is a time chart in the case of a cache miss hit.

FIG. 5 is a system configuration diagram of a data processing device.

FIG. 6 is a configuration diagram of a conventional technique.

FIG. 7 is a time chart of a conventional technique.

[Explanation of symbols]

 1 central processing unit 2 main memory control unit 3 main memory unit 20 access request unit 21 cache control unit 22a cache data array 22b cache directory 23 selection unit 24 store request issuing unit 25 control unit

Claims (1)

[Claims] 1. The central processing unit (1) searches whether or not data to be written is held in a cache memory (22) in the central processing unit (1) according to the preceding pipeline processing, According to the subsequent pipeline processing, a write data write request is issued to the main storage device (3) and at the same time, the cache memory (22) is targeted for writing according to the search result of the preceding pipeline processing. When it is determined that the data is held, in the main memory data write control method of writing the write data into the cache memory (22), the cache memory is processed according to the preceding pipeline process.
When it is determined that the data to be written is held in (22), the subsequent access request to the cache memory (22) is prohibited, and the subsequent pipeline processing is executed. Cache memory according to the preceding pipeline processing
When it is determined that the data to be written is not held in (22), it is necessary to allow the subsequent access request to the cache memory (22) and execute the subsequent pipeline processing. , A method for controlling main memory data writing.