JPH0514455B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data transmission method used in an independent synchronous loop data transmission system.

Conventionally, in the data transmission method used for this type of independently synchronous loop data transmission system,
When each frame in the transmission signal passes through the pass-through circuit in the data transmission equipment, consideration is given to prevent synchronization of the frame bits from occurring, but the time fill (special bit pattern) inserted between frames is Bit synchronization is not taken into account, and synchronization occurs. Even if synchronization is achieved using frame synchronization, bit synchronization may occur near the delimiter between the time file and delimiter (synchronization flag pattern in the frame), making it difficult to distinguish the frame delimiter, and the frame The disadvantage is that detection is complicated.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data transmission system that eliminates the above-mentioned drawbacks.

The method of the present invention is a data transmission method for transmitting data between a plurality of stations connected via a loop-shaped transmission path through which a transmission signal including a plurality of frames propagates. When the frame is given via the loop-shaped transmission line, the frame is synchronized with the clock of the own station and sent to the subsequent station via the loop-shaped transmission line,
When the frame is not provided from the preceding station via the loop-shaped transmission line, a predetermined pattern generated by the own station is synchronized with the clock of the own station and sent to the subsequent station via the loop-shaped transmission line. Send.

Next, the present invention will be explained in detail with reference to the drawings.

Referring to FIG. 1, the system to which the present invention is applied is comprised of data transmission devices 1-4 and optical fiber transmission lines 11-14.

Referring to FIG. 2, one embodiment of the present invention includes an optical/electrical conversion circuit 30 that converts an optical signal and an electrical signal, a clock signal line 51 that transmits a clock signal after optical/electrical conversion, A data signal line 52 that transmits data after electrical conversion, and a transmission line control circuit 3
2. It is composed of a clock signal line 54 for sending a clock to the transmission line and a data signal line 55 for sending data to the transmission line.

Referring to FIG. 3, the transmission line control circuit 32 of FIG. 2 includes a frame detection circuit 101 that detects each frame of a serially received signal given from the transmission line;
A shift register 102 that converts the serial reception frame detected by the detection circuit 101 into a parallel reception frame (parallel signal), a register 103, a reception circuit 104, a transmission circuit 105, and a data transmission device of another station that converts the parallel reception frame. FIFO to send to
(first-in first-out) circuit 106 and a frequency divider circuit 1 that counts the clock obtained from the received signal and generates a pulse (byte transmission clock) for each byte.
07, FIFO-enabled flip-flops 108 and 116 that are set when transmitting the frame that has passed through the FIFO circuit 106 to the transmission path,
A register 115 that temporarily holds the output data of the FIFO circuit 106, a crystal oscillator 109 that generates a transmission clock, and a pattern generation circuit 110 that generates a special pattern inserted between frames, that is, a time fill. , a shift register 111 for converting a parallel signal into a serial signal, a flip-flop 112 for temporarily holding a transmission signal, and a frequency dividing circuit 1 for counting pulses from an oscillator 109 and generating a pulse for each byte.
13, selectors 121 and 122, receiver 201, driver 202, and logical product (AND)
A circuit 211, an input clock signal line 301, an input data line 302, a byte reception clock signal line 303, a signal line 305 to which a frame reception signal that becomes high level during frame reception is applied, and a reception signal output from the register 103. in bytes
The circuit 10 sends a signal for writing to the FIFO circuit 106.
6, a clock signal line 304 for supplying the signal to
A signal line 306 for resetting the FIFO circuit 106 and the frequency dividing circuit 107, and a signal line 306 for resetting the FIFO circuit 106 and the frequency dividing circuit 107.
A signal line 307 to which a signal is applied when the output of the FIFO circuit 106 becomes valid, and a clock line 316 to which a clock is applied when reading from the FIFO circuit 106.
, a signal line 308 to which a select signal for setting the contents of the FIFO circuit 106 is applied to the register 111, a data signal line 310 to which a serial transmission signal from the transmission circuit 105 is applied, and a transmission signal from the data signal line 310. A signal line 309 to which a select signal is applied to select the frequency divider circuit 1
Clock signal lines 313 and 321 to which a byte transmission clock is applied from 13, clock signal line 311 which sends out a transmission clock, and data signal line 3 to which a signal from shift register 111 is applied.
12, a data signal line group 314 on which the contents of the FIFO circuit 106 are carried, and a data signal line group 315 which is the output of the register 115.

Referring to FIG. 4, the frame applied to the present invention has a flag pattern F of '01111110', a destination address DA, a source address SA, control information C, data information, and a frame check sequence. It consists of a cyclic redundancy check bit FCS to check whether the data has been transferred. Data information may be omitted.

Next, the operation of this embodiment will be explained.

First, from the data transmission device 4 to the data transmission device 3
Data transmission device 1 when transferring frames to
The first operation will be explained. The optical signal applied from the optical fiber transmission line 14 is converted from an optical signal to an electrical signal by an optical-to-electrical conversion circuit 30, and a reception clock and a reception frame are outputted to a clock line 51 and a data line 52, respectively. The received frame is transferred to shift register 1 based on the receive clock.
At the same time, when the frame detection circuit 101 detects a flag pattern, it sends a frame reception signal to the signal line 305, and at the rising edge of the frame reception signal, the 1/8 frequency divider circuit 107 is set. A pulse sufficient to reset is output on signal line 306. After this, the received frame is sent to the FIFO circuit 1 in bytes based on the clock output from the frequency divider circuit 107.
Written to 06. The FIFO circuit 106 is in a data sending enabled state (the flag pattern F is
4), a high level signal is sent to the signal line 307. When a byte transmission clock pulse is applied from frequency divider circuit 113, flip-flop 108 is set by a high level signal on signal line 307, and flag pattern F is stored in register 115. Furthermore, when the next byte transmit clock pulse is sent out, the output of flip-flop 108 causes flip-flop 11
6 is set, and a byte transmission clock pulse is applied to the FIFO circuit 106 via the signal line 316. In response, the destination address DA in the received frame is placed on the signal line group 314.
A flag pattern F is placed on the data line group 315. When the flip-flop 116 is set and outputs a high level signal to the signal line 308, the selector 121 selects the data line group 315,
Flag pattern F is stored in register 111 in synchronization with the byte transmission clock applied from signal line 321. At this time, signal lines 313 and 31
A byte transmit clock pulse is applied to the FIFO circuit via 6, and the destination address DA and source address SA are placed on data line groups 315 and 314, respectively. On the other hand, the contents stored in the register 111 are shifted out one bit at a time in synchronization with the transmission clock from the oscillator 109 to the selector 1.
22 to the flip-flop 112, and further sent to the transmission line 11 via the driver 202 and the optical/electrical conversion circuit 31.

When the frame detection circuit 101 detects the flag pattern on the rear side of each frame, it waits for the flag pattern on the rear side to be stored in the FIFO circuit 106, outputs a low level signal to the signal line 305, and then outputs a low level signal to the signal line 305, and then starts the next frame. Maintain this until it propagates.
When all received frames are read out from the FIFO circuit 106, a low level signal is output to the signal line 307, and the flip-flop 108 is reset.
When the latter flag pattern is stored in the register 111, the selector 121 selects the pattern data generated by the pattern generation circuit 110 as the output. Also, when it is desired to send a frame from the own station to the transmission path, the transmission circuit 105 sends a frame to the signal line 3.
When a select signal is sent to the selector 122 via the selector 09, the data line 310 is selected. Normally, data line 312 is selected. Therefore, when frame transmission/reception operations are not performed, the pattern generation circuit 11 in the data transmission device 1
From 0 onwards, the time fill pattern data is transmitted to the transmission line 11 in synchronization with the transmission clock from the crystal oscillator 109.
FIFO circuit 106 is operated only when a frame is sent from transmission line 14.

Note that the time fill pattern of the pattern generation circuit 110 is, for example, '11111111'.
A repetition of 00000000' is used.

Next, a second operation of the data transmission device 1 when transferring a frame from the data transmission device 4 to the data transmission device 1 will be described. The difference from the operation described above is that when a flag pattern is detected by the frame detection circuit 101, a high-level frame reception signal is generated on the signal line 305, but the frame reception signal is generated because the destination address DA is not addressed to the local station. When detected by the detection circuit 101, the signal line 305
Immediately lower the signal of signal line 3 to a low level and
06 to reset the FIFO circuit 106. As a result, the signal line 308
does not reach a high level, pattern generation circuit 1
10, a time fill pattern is sent to the transmission line 11 in synchronization with the clock from the crystal oscillator 109.

In addition, in a method in which the sender erases the frame addressed to itself from the transmission path rather than the sender's destination, the destination data transmission device has the destination address DA in the frame addressed to its own station. Instead of performing the second operation described above, the first operation may be performed to pass this frame and send it to the source data transmission device. The source data transmission device performs the second operation described above if the source address SA in the frame is addressed to its own station.

In this embodiment, the capacity of the FIFO circuit is 1 byte, but it may be divided into units of 4 bits, 10 bits, or 16 bits. Furthermore, although the transmission path is considered to be in units of 8 bits per octet, it is also possible to insert a code conversion circuit in the middle to make the transmission path 10 bits, 16 bits, etc. Furthermore, although an optical fiber and an optical-to-electrical conversion circuit are used in this embodiment, the optical-to-electrical conversion circuit is not required when a coaxial cable or the like is used as a transmission path.

When designing an independently synchronous loop transmission line using this embodiment, it is sufficient to consider the maximum frame length and the phase error of the crystal oscillator used in each data transmission device. For example, if the phase error is 10 ^-4 and the maximum frame length is 4KB (kilobytes), the bit shift while passing through the FIFO circuit is approximately ±4 bits (4 x 1024 x 8 x 10 ^-4 ).
Therefore, the FIFO circuit should have a capacity that can absorb this bit shift.

As described above, the present invention has the advantage that frames and time fills without bit synchronization can be transmitted on a loop-shaped transmission path, and there is no need to consider synchronization in the transmitter/receiver section of the data transmission device.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a loop-shaped transmission system to which the present invention is applied, FIG. 2 is a diagram showing the basic configuration used in the present invention, FIG. 3 is a diagram showing the configuration of the transmission control circuit in FIG. FIG. 4 is a diagram showing a general frame format used in the present invention. 1 to 3, 1 to 4...data transmission device, 11 to 14...transmission line, 30...photoelectric conversion circuit, 32...transmission line control circuit, 101...
...Frame detection circuit, 102, 103, 111,
115...Register, 104...Receiving circuit, 10
5... Transmission circuit, 106... FIFO circuit, 107,
113... Frequency dividing circuit, 108, 112, 116...
...Flip-flop, 109...Crystal oscillator, 1
10... Pattern generation circuit, 121, 122...
Selector, 201... Receiver, 202... Driver, 211... AND circuit, 301, 303,
304, 311, 313, 51, 54...Clock signal line, 302, 310, 312, 314, 3
15, 52, 55...data signal line, 305-3
09,321...Signal line.

Claims (1)

[Claims] 1. In a data transmission system for transmitting data between a plurality of stations connected via a loop-shaped transmission path through which a transmission signal including a plurality of frames propagates, each station transmits data to a previous station. When the frame is given from the station via the loop-shaped transmission line, the frame is synchronized with the clock of the own station and sent to the subsequent station via the loop-shaped transmission line, and the loop-shaped transmission is performed from the previous station. data characterized in that when the frame is not given through the loop-shaped transmission path, a predetermined pattern generated by the local station is synchronized with the clock of the local station and sent to the subsequent station through the loop-shaped transmission path. Transmission method. 2. When the frame from the previous station is addressed to its own station, each station synchronizes the predetermined pattern with its own clock without transmitting the frame to the subsequent station. 2. The data transmission method according to claim 1, wherein the data transmission method is transmitted to 3. When the frame from the previous station is a frame transmitted by the own station, each station synchronizes the predetermined pattern with its own clock without transmitting the frame to the subsequent station. 2. The data transmission method according to claim 1, wherein the data transmission method is transmitted to a subsequent station.