JPH0514548Y2 - - Google Patents
Info
- Publication number
- JPH0514548Y2 JPH0514548Y2 JP1987200460U JP20046087U JPH0514548Y2 JP H0514548 Y2 JPH0514548 Y2 JP H0514548Y2 JP 1987200460 U JP1987200460 U JP 1987200460U JP 20046087 U JP20046087 U JP 20046087U JP H0514548 Y2 JPH0514548 Y2 JP H0514548Y2
- Authority
- JP
- Japan
- Prior art keywords
- insulating substrate
- film resistor
- circuit board
- integrated circuit
- hybrid integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Parts Printed On Printed Circuit Boards (AREA)
- Details Of Resistors (AREA)
- Non-Adjustable Resistors (AREA)
Description
【考案の詳細な説明】
[産業上の利用分野]
本考案は、混成集積回路基板に関し、特に、絶
縁基板上に膜状抵抗体を形成して成る混成集積回
路基板に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a hybrid integrated circuit board, and particularly to a hybrid integrated circuit board in which a film resistor is formed on an insulating substrate.
[従来の技術]
従来、絶縁基板上に回路パターン及び膜状抵抗
体を形成して成る混成集積回路基板においては、
前記絶縁回路基板上にスクリーン印刷等により回
路パターンや膜状抵抗体を形成し、レーザトリミ
ング法等の手段により、この膜状抵抗体の抵抗値
を調整した後、コンデンサやトランジスタ等の部
品やリード線を半田付けし、最後に、外的影響か
ら回路を保護するため、その表面に樹脂等を塗布
して、覆つている。[Prior Art] Conventionally, in a hybrid integrated circuit board in which a circuit pattern and a film resistor are formed on an insulating substrate,
A circuit pattern and a film resistor are formed on the insulated circuit board by screen printing, etc., and the resistance value of the film resistor is adjusted by means such as laser trimming, and then components such as capacitors and transistors and leads are formed. The wires are soldered, and finally, to protect the circuit from external influences, the surface is coated with resin or the like to cover it.
また、この様に樹脂等を塗布するほか、膜状抵
抗体を覆うように絶縁基板上に保護キヤツプを取
り付け、膜状抵抗体を保護する手段も既に知られ
ている。 In addition to applying a resin or the like as described above, there is already known a method for protecting the film resistor by attaching a protective cap to the insulating substrate so as to cover the film resistor.
[考案が解決しようとする問題点]
しかしながら、前者の従来技術においては、膜
状抵抗体の抵抗値を調整した後、その表面に樹脂
等を塗布するため、この樹脂が硬化するときに起
こる収縮により、前記膜状抵抗体に応力が発生し
て、平面上の歪が生じ、このためその抵抗値が変
化してしまう。また、その後の温度変化に伴い、
樹脂と膜状抵抗体との熱膨張係数の違いから、膜
状抵抗体に熱応力が生じ、やはり平面上の歪が生
じ、このためその抵抗値が変化してしまう。[Problems to be solved by the invention] However, in the former conventional technology, after adjusting the resistance value of the film resistor, a resin etc. is applied to the surface of the film resistor, so the shrinkage that occurs when the resin hardens. As a result, stress is generated in the film resistor, resulting in distortion in the plane, and as a result, its resistance value changes. In addition, with subsequent temperature changes,
Due to the difference in coefficient of thermal expansion between the resin and the film resistor, thermal stress is generated in the film resistor, which also causes distortion in the plane, resulting in a change in its resistance value.
そのため、折角調整した前記膜状抵抗体の抵抗
値がその後に変動し、十分高い精度を得ることが
できない。このため、前記従来技術では、抵抗値
を±0.5%以下の精度に調整することが困難であ
つた。 Therefore, the resistance value of the film resistor that has been painstakingly adjusted varies thereafter, making it impossible to obtain sufficiently high accuracy. Therefore, in the prior art, it is difficult to adjust the resistance value to an accuracy of ±0.5% or less.
また、保護キヤツプを用いる後者の従来技術の
場合、保護キヤツプを絶縁基板上に取り付ける工
程が別途必要となる。そのため、回路基板の製造
工程が増加し、工数増大による回路基板の製造原
価の増大を招く。また、膜状抵抗体の周りに保護
キヤツプを設置するスペースをとらなければなら
ないため、膜状抵抗体の周囲に回路パターンを形
成することができないエリアが生じる。このた
め、絶縁回路基板上に高密度で回路を形成するこ
とができず、回路パターンの高密度化の障害とな
る。 Furthermore, in the case of the latter conventional technique using a protective cap, a separate step is required to attach the protective cap onto the insulating substrate. Therefore, the number of manufacturing steps for the circuit board increases, leading to an increase in the manufacturing cost of the circuit board due to the increase in the number of man-hours. Furthermore, since a space must be provided for installing a protective cap around the film resistor, there is an area around the film resistor where a circuit pattern cannot be formed. For this reason, circuits cannot be formed at high density on the insulated circuit board, which becomes an obstacle to increasing the density of circuit patterns.
そこで、本考案は、前記の従来技術における問
題点に鑑み、回路基板の製造工程の増大を招か
ず、回路の高密度化の障害とならずに、なおかつ
膜状抵抗体を保護することができる構造の混成集
積回路基板を提供することを目的とする。 Therefore, in view of the problems in the prior art described above, the present invention is capable of protecting the film resistor without increasing the manufacturing process of the circuit board and without becoming an obstacle to increasing the density of the circuit. The present invention aims to provide a hybrid integrated circuit board with a structure.
[問題を解決するための手段]
すなわち、前記の本考案の目的は、第一の絶縁
基板上に形成された前記膜状抵抗体の周囲に導体
パターンを形成し、該導体パターンに対応して下
面に半田付け用の導体パターンを形成した第二の
絶縁基板を、前記膜状抵抗体から離すと共に、同
膜状抵抗体を跨いで前記第一の絶縁基板上に搭載
すると共に、第二の絶縁基板の導体パターンを第
一の絶縁基板上の導体パターンに半田付けしてな
ることを特徴とする混成集積回路基板によつて達
成される。[Means for solving the problem] That is, the object of the present invention is to form a conductive pattern around the film resistor formed on a first insulating substrate, and to form a conductor pattern corresponding to the conductive pattern. A second insulating substrate on which a conductor pattern for soldering is formed on the lower surface is separated from the film resistor, and is mounted on the first insulating substrate straddling the film resistor. This is achieved by a hybrid integrated circuit board characterized in that a conductive pattern on an insulating substrate is soldered to a conductive pattern on a first insulating substrate.
[作用]
前記の混成集積回路基板によれば、保護を必要
とする前記膜状抵抗体は、第二の絶縁基板によつ
て外的影響から保護される一方、この第二の絶縁
基板は膜状抵抗体から離れているため、熱応力等
による歪を受けることがない。よつて、その抵抗
値の変化が起こらず、一旦調整した抵抗値を、そ
の後も安定して保持することが出来る。[Function] According to the hybrid integrated circuit board, the film resistor that requires protection is protected from external influences by the second insulating substrate, and the second insulating substrate is Because it is separated from the shaped resistor, it is not subject to distortion due to thermal stress or the like. Therefore, the resistance value does not change, and the resistance value once adjusted can be stably maintained thereafter.
そして、第二の絶縁基板は、第一の絶縁基板上
に搭載され、同第一の絶縁基板の上に形成された
導体パターン上に半田付けされるため、他の電子
部品を搭載し、半田付けする工程において、それ
と同時に第一の絶縁基板上に搭載し、半田付けす
ることができる。従つて、第二の絶縁基板を第一
の絶縁基板上に搭載する工程を特別に必要としな
い。 The second insulating board is mounted on the first insulating board and soldered onto the conductor pattern formed on the first insulating board, so other electronic components can be mounted and soldered. In the attaching process, it can be simultaneously mounted on the first insulating substrate and soldered. Therefore, a special step of mounting the second insulating substrate on the first insulating substrate is not required.
さらに、第二の絶縁基板は、第一の絶縁基板上
で或る範囲のエリアを占有するが、この第二の絶
縁基板は、第一の絶縁基板と同様の絶縁基板であ
るから、それを利用して回路を形成することがで
きる。従つて、膜状抵抗体の上に二重に回路を形
成することができ、回路の密度を高めることがで
きる。 Furthermore, the second insulating substrate occupies a certain range of area on the first insulating substrate, but since this second insulating substrate is the same insulating substrate as the first insulating substrate, It can be used to form circuits. Therefore, a double circuit can be formed on the film resistor, and the density of the circuit can be increased.
[実施例]
以下、本考案の実施例について、図面を参照し
ながら説明する。[Examples] Examples of the present invention will be described below with reference to the drawings.
第1図、第2図に示すように、アルミナ(AI2
O3)等から成る第一の絶縁基板1の表面に、導
体パターン11,12や膜状抵抗体3が、例えば
スクリーン印刷法等によつて所定の形状に形成さ
れ、いわゆる混成集積回路基板が構成されてい
る。そして、この様な混成集積回路基板の第一の
絶縁基板1の表面上の一部、例えば前記膜状抵抗
体が形成された表面上(第1図中、下側に示す第
一の絶縁基板1の隅部)には、やはり前記第一の
絶縁基板1と同様にアルミナ等から成る他のセラ
ミツク板、すなわち保護用の第二の絶縁基板2が
前記膜状抵抗体3を覆うように設けられている。 As shown in Figures 1 and 2, alumina (AI 2
Conductive patterns 11, 12 and a film resistor 3 are formed in a predetermined shape by, for example, screen printing on the surface of a first insulating substrate 1 made of O 3 ), etc., thereby forming a so-called hybrid integrated circuit board. It is configured. A part of the surface of the first insulating substrate 1 of such a hybrid integrated circuit board, for example, the surface on which the film resistor is formed (the first insulating substrate shown on the lower side in FIG. 1), another ceramic plate made of alumina or the like similarly to the first insulating substrate 1, that is, a second insulating substrate 2 for protection is provided to cover the film resistor 3. It is being
前記の様な混成集積回路基板の第一の絶縁基板
1の表面上の一部(第1図中、下側に示す第一の
絶縁基板1の隅部)について、第2図〜第4図に
より、さらに詳しく説明する。まず、第2図にお
いて、前記第一の絶縁基板1の右下隅部には、導
体パターン11,12が、Ag−Pdペースト等の
導電ペーストを印刷し、乾燥し、焼成することに
より形成されている。これら導体パターン11,
12の間には、RuO2系等の抵抗ペーストを印刷
し、乾燥し、焼成することにより、膜状抵抗体3
が形成されている。 Regarding a part of the surface of the first insulating substrate 1 of the hybrid integrated circuit board as described above (the corner of the first insulating substrate 1 shown on the lower side in FIG. 1), FIGS. This will be explained in more detail. First, in FIG. 2, conductive patterns 11 and 12 are formed at the lower right corner of the first insulating substrate 1 by printing a conductive paste such as Ag-Pd paste, drying it, and baking it. There is. These conductor patterns 11,
Between 12 and 12, a resistance paste such as RuO 2 is printed, dried, and fired to form a film resistor 3.
is formed.
さらに、図中には、第二の絶縁基板2を取り付
けるための、いわゆる半田付け用のパターン1
3,14が、前記導体パターン11,12と同様
に導電ペーストを印刷し、乾燥し、焼成すること
により形成されている。この、半田付け用パター
ン13,14は前記導体パターン11,12と同
時に形成することが可能であり、この場合に、前
記導体パターンを延長して、これらと一体に形成
することもできる。 Furthermore, in the figure, a so-called soldering pattern 1 for attaching the second insulating board 2 is shown.
3 and 14 are formed by printing, drying, and baking a conductive paste in the same way as the conductor patterns 11 and 12. These soldering patterns 13 and 14 can be formed simultaneously with the conductor patterns 11 and 12, and in this case, the conductor patterns can be extended and formed integrally with them.
そして、この様にして形成された混成集積回路
基板は、レーザトリミング法等の手段により、前
記膜状抵抗体3の抵抗値が、例えば3KΩ±0.05%
程度の精度で調整される。 Then, the hybrid integrated circuit board thus formed is processed such that the resistance value of the film resistor 3 is reduced to, for example, 3KΩ±0.05% by means such as a laser trimming method.
Adjusted with a degree of accuracy.
一方、前記の膜状抵抗体3等、いわゆる外的影
響から保護されるべき部分に対応し、これを表面
から十分に覆うように、第3図に示すような他の
セラミツク板等から成る保護用の第二の絶縁基板
2を用意する。図にも示すように、この第二の絶
縁基板2の下側表面の四隅には、やはり前記導体
パターン11,12と同様にAg−Pdペーストを
印刷し、乾燥し、焼成することにより、半田付け
用のパターン21が形成されている。 On the other hand, in order to sufficiently cover the parts such as the film resistor 3 that should be protected from external influences, other ceramic plates as shown in Fig. 3 are used for protection. A second insulating substrate 2 is prepared. As shown in the figure, Ag-Pd paste is printed on the four corners of the lower surface of the second insulating substrate 2 in the same manner as the conductor patterns 11 and 12, dried, and fired to solder. A pattern 21 for attachment is formed.
第4図には、前記第2図に示す混成集積回路基
板の表面上に前記第3図の保護用の第二の絶縁基
板2を取り付けた状態が示されている。この図か
ら明らかなように、前記第一の絶縁基板1の表面
に形成された導体パターン11,12と、半田付
け用のパターン13,14の上に半田層4が形成
され、前記保護用の第二の絶縁基板2の下面の半
田付け用パターン21に半田接合されている。こ
の半田層4の形成には、例えばリフロー法等が利
用できる。 FIG. 4 shows a state in which the second protective insulating substrate 2 shown in FIG. 3 is attached on the surface of the hybrid integrated circuit board shown in FIG. 2. As is clear from this figure, the solder layer 4 is formed on the conductive patterns 11 and 12 formed on the surface of the first insulating substrate 1 and the soldering patterns 13 and 14, and It is soldered to a soldering pattern 21 on the lower surface of the second insulating substrate 2 . For forming this solder layer 4, for example, a reflow method or the like can be used.
さらに、この上から樹脂等の保護手段を施すこ
とができ、この場合、前記樹脂は保護用の第二の
絶縁基板2によつて、膜状抵抗体3の表面には被
着しない。 Furthermore, a protective means such as a resin can be applied from above, and in this case, the resin does not adhere to the surface of the film resistor 3 due to the second protective insulating substrate 2.
なお、前記第二の絶縁基板2の表面や裏面を利
用して回路を形成することにより、より高密度の
回路が構成できる。すなわち、該第二の絶縁基板
2の表面や裏面に回路パターンを形成し、これを
前記半田付け用のパターン21と半田付け用のパ
ターン13,14とを介して、第一の絶縁基板1
側の導体パターン11,12と接続する。 Note that by forming a circuit using the front and back surfaces of the second insulating substrate 2, a higher density circuit can be constructed. That is, a circuit pattern is formed on the front and back surfaces of the second insulating substrate 2, and is then attached to the first insulating substrate 1 via the soldering pattern 21 and the soldering patterns 13 and 14.
It is connected to the conductor patterns 11 and 12 on the side.
この様にして製造された混成集積回路の、完成
後の前記膜状抵抗体3の抵抗値を実際に測定した
結果、その測定値は3KΩ±0.07%と従来のものに
比較してそのドリフトが低減されている。さら
に、−40℃で30分間と125℃で30分間のヒートサイ
クル試験を100サイクル行つたが、本考案に成る
混成集積回路の前記膜状抵抗体3の抵抗値は
3KΩ±0.08%とほとんど変化が見られなかつた。
これに対し、既述の従来例のように、エポキシ系
の樹脂で表面の回路パターンを含めて第一の絶縁
基板1の表面を覆つたものでは、トリミング後の
膜状抵抗体の抵抗値は3KΩ±0.05%であつたにも
かかわらず、その塗装後では3KΩ±0.40%と、そ
の精度が低下している。また、前記のヒートサイ
クル試験を100サイクル行つた後では、抵抗値が
3KΩ±0.60%と、さらに大きく精度が低下してし
まつた。 As a result of actually measuring the resistance value of the film resistor 3 after completion of the hybrid integrated circuit manufactured in this way, the measured value was 3KΩ±0.07%, which shows that the drift is less than that of the conventional one. has been reduced. Furthermore, 100 cycles of heat cycle tests were conducted at -40°C for 30 minutes and at 125°C for 30 minutes, and the resistance value of the film resistor 3 of the hybrid integrated circuit according to the present invention was
Almost no change was observed at 3KΩ±0.08%.
On the other hand, in the case where the surface of the first insulating substrate 1 including the circuit pattern on the surface is covered with epoxy resin as in the conventional example described above, the resistance value of the film resistor after trimming is Even though the resistance was 3KΩ±0.05%, after painting the accuracy decreased to 3KΩ±0.40%. Also, after performing the heat cycle test mentioned above for 100 cycles, the resistance value
The accuracy decreased even more to 3KΩ±0.60%.
[考案の効果]
以上の説明からも明らかなように、本考案によ
れば、膜状抵抗体を調整した後の抵抗値の精度の
低下を防止することができる。しかも、第二の絶
縁基板は、他の電子部品と共に第一の絶縁基板上
に搭載し、半田付けすることができるため、第二
の絶縁基板を取り付ける工程を別途加える必要が
無い。このため、混成集積回路基板の大幅な製造
原価の増大を招かない。さらに、第二の絶縁基板
を利用して膜状抵抗体の上に二重に回路を形成す
ることができるため、回路の高密度化を図ること
ができる。[Effects of the Invention] As is clear from the above description, according to the present invention, it is possible to prevent the accuracy of the resistance value from decreasing after adjusting the film resistor. Furthermore, since the second insulating substrate can be mounted and soldered together with other electronic components on the first insulating substrate, there is no need to add a separate process for attaching the second insulating substrate. Therefore, the manufacturing cost of the hybrid integrated circuit board does not increase significantly. Furthermore, since a double circuit can be formed on the film resistor by using the second insulating substrate, it is possible to increase the density of the circuit.
第1図は本考案の混成集積回路基板を示す一部
斜視図、第2図は前記混成集積回路基板の基板の
構成を示す一部平面図、第3図は前記混成集積回
路基板の保護用基板を示す底面図、第4図は第1
図のA−A断面を示す一部断面図である。
1……第一の絶縁基板、11,12……導体パ
ターン、13,14……半田付け用パターン、2
……第二の絶縁基板、21……第二の絶縁基板の
半田付け用パターン、3……膜状抵抗体、4……
半田層。
FIG. 1 is a partial perspective view showing the hybrid integrated circuit board of the present invention, FIG. 2 is a partial plan view showing the configuration of the board of the hybrid integrated circuit board, and FIG. 3 is a protection screen for the hybrid integrated circuit board. Bottom view showing the board, Figure 4 is the first
It is a partial sectional view showing the AA cross section of the figure. DESCRIPTION OF SYMBOLS 1... First insulating board, 11, 12... Conductor pattern, 13, 14... Soldering pattern, 2
...Second insulating substrate, 21...Soldering pattern for second insulating substrate, 3...Film resistor, 4...
solder layer.
Claims (1)
成して成る混成集積回路基板において、第一の
絶縁基板上に形成された前記膜状抵抗体の周囲
に導体パターンを形成し、該導体パターンに対
応して下面に半田付け用の導体パターンを形成
した第二の絶縁基板を、前記膜状抵抗体から離
すと共に、同膜状抵抗体を跨いで前記第一の絶
縁基板上に搭載すると共に、第二の絶縁基板の
導体パターンを第一の絶縁基板上の導体パター
ンに半田付けしてなることを特徴とする混成集
積回路基板。 (2) 実用新案登録請求の範囲第1項において、前
記絶縁基板の表面にも回路が形成されているこ
とを特徴とする混成集積回路基板。[Utility Model Claims] (1) A hybrid integrated circuit board formed by forming a circuit pattern and a film resistor on an insulating substrate, characterized in that a conductor pattern is formed around the film resistor formed on a first insulating substrate, a second insulating substrate having a conductor pattern for soldering formed on its underside corresponding to the conductor pattern is separated from the film resistor and mounted on the first insulating substrate across the film resistor, and the conductor pattern of the second insulating substrate is soldered to the conductor pattern on the first insulating substrate. (2) A hybrid integrated circuit board according to claim 1, characterized in that a circuit is also formed on the surface of the insulating substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987200460U JPH0514548Y2 (en) | 1987-12-30 | 1987-12-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987200460U JPH0514548Y2 (en) | 1987-12-30 | 1987-12-30 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01104765U JPH01104765U (en) | 1989-07-14 |
| JPH0514548Y2 true JPH0514548Y2 (en) | 1993-04-19 |
Family
ID=31490866
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987200460U Expired - Lifetime JPH0514548Y2 (en) | 1987-12-30 | 1987-12-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0514548Y2 (en) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5386465A (en) * | 1977-01-08 | 1978-07-29 | Mitsubishi Electric Corp | Semiconductor device |
| JPS6049693U (en) * | 1983-09-14 | 1985-04-08 | 株式会社日立製作所 | thick film circuit board |
| JPS60124856A (en) * | 1983-12-09 | 1985-07-03 | Toshiba Corp | Manufacture of electronic parts |
-
1987
- 1987-12-30 JP JP1987200460U patent/JPH0514548Y2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01104765U (en) | 1989-07-14 |
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