JPH0514865A - Time axis correction circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a time axis correction circuit capable of correcting velocity error within one horizontal synchronization period with high accuracy. [Structure] Coefficient adding means (first to fourth coefficient adders and adders)
The phase error signals having the coefficients added by 29 to 33 and one of the plurality of phase error signals stored in the memory means (memory) 11 are respectively associated with the center and the end of one horizontal synchronization period. , A waveform signal for linearly interpolating between them is generated by a waveform signal generation means (waveform signal generation circuit) 25
And the jitter is removed by phase-modulating the D / A conversion clock using this waveform signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time axis correction circuit for eliminating a jitter (Jitter: uncoordinated fluctuation) contained in an input video signal in a video signal recording / reproducing apparatus or the like.

[0002]

2. Description of the Related Art Conventionally, a time base correction circuit called a digital TBC (Time base corrector) is known as a device for removing the jitter contained in the input video signal as described above.

This is because, for example, the input video signal is sampled with a clock that follows the jitter contained in the input video signal, data that is converted into a digital signal is written to the memory, and the data is stored again at a stable fixed clock. It is intended to obtain an input video signal that does not include jitter by reading the data from the input device and converting it into an analog signal.

FIG. 6 shows a conventional configuration of a time axis correction circuit for removing the jitter contained in such an input video signal.

In the figure, reference numeral 1 is an input terminal for inputting a video signal containing jitter. This video signal is, as shown in FIG.
It includes a horizontal sync signal and a burst signal. The video signal input from the input terminal 1 is separated into a horizontal synchronizing signal and a burst signal by the synchronizing signal separating circuit 2, and the horizontal synchronizing signal is phase-locked (PLL: Phase Lock Loop) 3
Then, the burst signals are supplied to the phase comparison circuit 4, respectively.

The phase synchronizing circuit 3 generates a clock having the same frequency as the burst signal phase-locked with the horizontal synchronizing signal. The phase comparison circuit 4 compares the output of the phase synchronization circuit 3 and the burst signal from the synchronization signal separation circuit 2 in phase. Then, the phase difference signal is supplied from the phase comparison circuit 4 to the phase shift circuit 5. This phase shift circuit 5
The output clock of the phase synchronization circuit 3 is phase-shifted according to the phase difference signal supplied from the phase comparison circuit 4.

As a result, a clock having the same phase and the same frequency as the burst signal can be obtained. The output from the phase shift circuit 5 is converted into a signal of N times frequency by the frequency multiplication circuit 6.

In this way, the video signal input from the input terminal 1 is sampled by the A / D conversion circuit 7 by the output of the phase shift circuit 5, converted into a digital signal, and then written in the memory (memory means) 8. Be done.

By the operation described above, the memory 8 is
At least at the position of the burst signal, the data from which the jitter has been completely removed is written.

However, the phase of the video signal changes within one horizontal synchronization period, and a large phase error occurs particularly at the rear part of one horizontal synchronization period. The phase error within one horizontal synchronization period is called velocity error. This velocity error is
It is corrected by the memory reading circuit described below.

The output of the phase comparison circuit 4 is converted from an analog signal to a digital signal in the second A / D conversion circuit 10 based on the timing signal generated from the timing signal generation circuit 9 every horizontal synchronization period, and the second signal is converted into a digital signal. To the memory 11 (memory means). The data written in the second memory 11 is generated by the second timing signal generation circuit 13 which receives the reference clock having the same frequency as the burst signal input from the clock input terminal 12 and is generated at every horizontal synchronization period. The signal is read out, and the D / A conversion circuit 14 converts the digital signal into an analog signal.

Based on the data output from the D / A conversion circuit 14, a velocity error correction waveform signal is generated by the waveform signal generation circuit (waveform signal generation means) 15. The velocity error correction waveform signal generated by the waveform signal generation circuit 15 is output to the second phase shift circuit 16.

In the second phase shift circuit 16, the clock input terminal 12 is operated according to the velocity error correction waveform signal.
The phase of the reference clock input from the
To the frequency multiplication circuit 17 for converting into a signal of N times frequency, and a clock for reading from the memory 8 and the second D /
It is used as a conversion clock for the A conversion circuit 18. The output from the second D / A conversion circuit 18 is obtained from the output terminal 19.

Here, the reading from the second memory 11 must precede the reading timing of the first memory by one horizontal synchronization period. This is because, when the velocity error correction waveform signal is generated from the waveform signal generation circuit 15, the last velocity error value of the one horizontal synchronization period is required.

FIG. 8 shows operation waveforms of the time axis correction circuit described above. In FIG. 8, the vertical axis represents the phase and the horizontal axis represents the time t. The solid line in FIG. 8A shows the waveform of the phase fluctuation waveform signal (jitter waveform signal) of the video signal input,
The alternate long and short dash line shows the waveform of the output waveform signal of the phase comparison circuit 4.

The phase of the clock applied to the first A / D conversion circuit 7 follows the output waveform signal of the phase comparison circuit 4. The phase of the data written on the first memory 8 is
A difference between the output waveform signal of the phase comparison circuit 4 and the phase of the video signal, that is, a velocity error occurs, and the waveform of this velocity error signal is shown in FIG. The solid line in FIG. 8B shows the waveform of the velocity error, and the waveform signal generation circuit 15 outputs 1 of the output waveform signal of the phase comparison circuit 4.
A sawtooth velocity error correction waveform signal having a slope proportional to the amount of change for each horizontal synchronization period is generated, and the waveform is shown by the alternate long and short dash line in FIG.

Since the read clock of the first memory 8 is phase-shifted by the velocity error correction waveform signal generated from the waveform signal generating circuit 15, the second D / A
The velocity error is removed from the output of the conversion circuit 18.

The waveform signal generation circuit 15 is constructed, for example, as shown in FIG. In FIG. 9, 20 is an input terminal to which the phase error signal output from the phase comparison circuit 4 of FIG. 6 is input. The phase error signal input from this input terminal 20 is 1H
It is added to the delay circuit 21 and the subtraction circuit 22. The output of the 1H delay circuit 21 is also added to the subtraction reply 22. As the output of the subtraction circuit 22, the difference ΔPE of the phase error signal in one horizontal synchronizing period is obtained. Reference numeral 23 denotes an integrating circuit, which has a reset input for resetting every horizontal synchronization period. In the integration circuit 23, the difference ΔP
E is integrated and a sawtooth velocity error correction waveform signal whose amplitude is proportional to the difference ΔPE is obtained from the output terminal 24.

[0019]

However, in the above-described conventional time axis correction circuit, the velocity error within one horizontal synchronization period is approximated by a straight line, so that the phase change of the video signal within one horizontal synchronization period. When the (speed) changes, there is a drawback that a phase error that cannot be corrected, that is, a residual phase error remains.

FIG. 8 (c) shows the waveform of this residual phase error signal. This residual phase error is a problem because the central portion of a visually important image tends to be large.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a time base correction circuit capable of correcting a velocity error within one horizontal synchronization period with high accuracy.

[0022]

In order to achieve such an object, the present invention provides a time base correction circuit for removing the jitter by phase-modulating a D / A conversion clock of a video signal containing the jitter. In memory means for storing a plurality of phase error signals in which the phase difference between the video signal and its A / D conversion clock is detected, and coefficient adding means for adding a plurality of coefficients to the phase error signals stored in the memory means. And the phase error signal added by the coefficient adding means and one of the plurality of phase error signals stored by the memory means are made to correspond to the center and the end of one horizontal synchronization period, respectively. And a waveform signal generating means for generating a waveform signal that linearly interpolates between them, and the D / A conversion is performed using the waveform signal generated by the waveform signal generating means. It is characterized in that so as to phase modulate the clock.

[0023]

A plurality of phase error signals obtained by detecting the phase difference between the video signal and its A / D conversion clock are stored in the memory means, and a plurality of the stored phase error signals are added by the coefficient adding means. , One of the phase error signal added with the coefficient and the stored phase error signal
Waveform signals for linearly interpolating between the center and the end of one horizontal synchronization period are generated by the waveform signal generating means, and the waveform signals are used to generate the A /
Velocity error correction is performed by phase-modulating the D conversion clock, and the jitter included in the video signal is removed.

[0024]

Embodiments of the present invention will be described below with reference to FIGS. The time-axis correction circuit according to the present invention and the above-described conventional time-axis correction circuit shown in FIG. 6 are different only in the configuration of the waveform signal generation circuit for generating the velocity error correction waveform signal.

FIG. 1 is a block diagram of a waveform signal generating circuit in a time axis correction circuit according to an embodiment of the present invention. In FIG. 1, 25 is a waveform signal generating circuit. The waveform signal generation circuit 25 includes three 1H delay circuits 26, 2
7, 28 and four coefficient units 29, 30, 31, 32,
It is composed of one adder 33, two subtractors 34 and 35, one switch 36, and one integrator 37.

First to third 1H delay circuits 26 to 28
Are connected in series to each other, and an input terminal 38 for inputting a phase error signal is connected to an input line of the first 1H delay circuit 26.

The phase error signal input from the input terminal 38 is supplied to the first to third 1H delay circuits 26 to 2.
8 are delayed by 1H (one horizontal synchronization period).

The input line of the first coefficient multiplier 29 is connected to the connection line between the first 1H delay circuit 26 and the input terminal 38. The input line of the second coefficient multiplier 30 has a first 1H delay circuit 26 and a second 1H delay circuit 2
It is connected to the connection line with 7. Third coefficient unit 31
Is connected to the connection line between the second 1H delay circuit 27 and the third 1H delay circuit 28. The input line of the fourth coefficient unit 32 is connected to the output line of the third 1H delay circuit 28.

Then, the first to fourth coefficient units 29 to 32
Is the phase error signal input from the input terminal 38 and
The output signals of the third 1H delay circuits 26 to 28 are weighted.

The first and fourth coefficient units 29 and 32 have a weight of "0.5-K", and the second and third coefficient units 30 and 31 have a weight of "K".

The output lines of the first to fourth coefficient units 29 to 32 are connected to the input line of the adder 33.

The adder 33 has the first to fourth coefficient units 2
The outputs of 9 to 32 are added and the phase error predicted value "X'i" at the midpoint of 1H is output.

The first to fourth coefficient units 29 to 32 and the adder 3
3 and 3 form a coefficient adding means. This adder 3
The output line 3 is connected to the (+) input terminal of the first subtractor 34 and the (−) input terminal of the second subtractor 35, respectively.

The output line of the second 1H delay circuit 27 is connected to the (-) input terminal of the first subtractor 34. Then, the first subtractor 34
It takes the difference between the output “Xi” of the H delay circuit 27 and the predicted phase error value “X′i” which is the output of the adder 33.

The output line of the first 1H delay circuit 26 is connected to the (+) input terminal of the second subtractor 35. Then, the second subtracter 35 takes the difference between the output "Xi + 1" of the first 1H delay circuit 26 and the phase error predicted value "X'i".

Output lines of the first and second subtractors 34 and 35 are connected to fixed contacts 36 ₁ and 36 ₂ of the switch 36, respectively. The movable contact 19 of this switch 36
₃ is connected to the input line of the integrator 37.

The switch 36 selectively switches the outputs of the first and second subtractors 34 and 35 based on the timing signal FH. The output of the switch 36 is input to the integrator 37 and integrated, and then output from the output terminal 39 as a velocity error correction waveform signal.

Next, the operation of the waveform signal generating circuit 25 having the above configuration will be described with reference to FIG.

In FIG. 1, the first to third 1H delay circuits 26 to 28, the first to fourth coefficient multipliers 29 to 32, and the adder 33 constitute an FIR filter, and at time "i". Let the phase error be “Xi”, and the phase error at the midpoint between time “i” and “i + 1” be X′i = K (Xi + Xi + 1) + (0.5-K) (Xi-1 + Xi + 2) ... Prediction (interpolation) is performed using the equation (1). FIG. 2A shows this time relationship.

Next, linear interpolation is performed between "Xi", "X'i", and "Xi + 1" to obtain a velocity error correction waveform signal.

The first and second subtractors 34 and 35, the switch 36, the integrator 37 and the output terminal 39 shown in FIG. 1 perform the linear interpolation operation.

The outputs of the first and second subtractors 34 and 35 in FIG. 1 are "X'i-Xi" and "Xi + 1-X'i", respectively.
This is switched by the timing signal FH in FIG.
By switching the center of 1H by controlling, and integrating this by the integrator 37 which is reset every 1H by the reset signal of FIG. 2C, “Xi”,
A linearly-interpolated waveform signal obtained by linearly interpolating between “X′i” and “Xi + 1” is obtained, and is output from the output terminal 39 as a velocity error correction waveform signal.

FIG. 2B shows the output waveform signal of the switch 36 (solid line) and the velocity error correction waveform signal (broken line).

Here, the coefficient "K" in the equation (1) should be selected so that the residual phase error is minimized.

FIG. 3 shows various jitter waveform signals measured,
It is a data table which took the root mean square value of the residual phase error by changing the coefficient "K". When the coefficient “K” is in the range of 0.65 to 0.7, the residual phase error becomes the minimum.

FIG. 4 is a graph showing the result of calculating the residual phase error with respect to the same phase waveform signal as in FIG. 8 with the coefficient “K” = 0.7. In FIG. 4, the vertical axis represents the phase and the horizontal axis represents the horizontal axis. The axes each represent time t.

The solid line in FIG. 4A shows the waveform of the phase fluctuation waveform signal (jitter waveform signal) of the video signal, and the alternate long and short dash line shows the waveform of the phase error signal. Further, FIG. 4B shows the waveform of the residual phase error signal. As is clear from the comparison between FIG. 4 and FIG. 8, the residual phase error of the present invention is reduced to about 1/2 of that of the prior art.

In the above embodiment, the waveform signal generating circuit 25 has a circuit configuration in which the phase error signal is input and the equation (1) is calculated as it is.

On the other hand, by transforming the equation (1), X'i-Xi = (K-0.5) ΔXi + 0.5ΔXi + 1 + (0.5-K) ΔXi + 2 (2) ) Expression Xi + 1−X′i = ΔXi + 1− (X′i−Xi) (3) where ΔXi = Xi−Xi−1 and the configuration of the waveform signal generation circuit 25 ′ for realizing this is given. As shown in FIG.

In FIG. 5, 40 is an input terminal for inputting a phase error signal, 41, 42 and 43 are first, second and third 1H delay circuits, and 44 is a phase error signal input from the input terminal 40. Subtractors for subtracting the output of the first 1H delay circuit 41, 45, 46, 47 are respectively subtractors 4
4, a coefficient unit for weighting each output signal of the second and third 1H delay circuits 42 and 43 with "0.5-K", "0.5", "K-0.5", 48 is a 1st-3rd coefficient unit 45-4
A first adder for adding the outputs of 7 and outputting "X'i-Xi", 49 is an output of the second 1H delay circuit 42 "Δ
"Xi + 1" and the output of the adder 48 are calculated to obtain "Xi + 1-"
It is a second subtractor that outputs X′i ”.

The output of the adder 48 and the output of the first subtractor 49 are equivalent to the outputs of the first and second subtractors 34 and 35 of FIG. 1, and addition (compared to the embodiment of FIG. 1)
It is decreasing. The coefficient of the second coefficient unit 46 is "0.
5 "and can be realized by a bit shift of 1 bit when configured with a digital circuit, which has an advantage of compact circuit scale.

In each of the above-described embodiments, the first D /
The operation is performed on the analog output of the A conversion circuit 14. In this case, the 1H delay circuit is a sample hold circuit, the coefficient unit and the adder are resistance addition circuits, and the integrator is an operational amplifier and a feedback capacitor. Can be realized by an integrating circuit or the like using. Of course, these operations are performed before the D / A conversion or in the second memory 1
The calculation may be performed digitally before passing through 1. In that case, higher-precision calculation is possible.

[0053]

As described above, according to the present invention, in order to correct the velocity error of the time axis correction circuit,
By adding the coefficient of the phase error signals before and after the one horizontal synchronization period of interest to predict the phase error in the central portion of the one horizontal synchronization period, and approximating the velocity error with the two-fold line waveform signal. As a result, the jitter can be corrected with higher accuracy, and the residual phase error can be greatly reduced.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a waveform signal generation circuit in a time base correction circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the waveform signal generation circuit of FIG.

FIG. 3 is a data table showing a root mean square value of residual phase errors with respect to a coefficient K of a coefficient unit in the waveform signal generation circuit of FIG.

FIG. 4 is a timing chart for explaining the effect of the present invention.

FIG. 5 is a similar view to FIG. 1 showing another embodiment of the present invention.

FIG. 6 is a block diagram of a conventional time axis correction circuit.

FIG. 7 is an explanatory diagram of a burst signal and a horizontal synchronization signal included in a video signal.

8 is a timing chart for explaining the operation of the time axis correction circuit shown in FIG.

9 is a block diagram of the waveform signal generation circuit shown in FIG.

[Explanation of symbols]

11 Memory (Memory Means) 29 to 32 Coefficient Unit (Coefficient Addition Means) 33 Adder (Coefficient Addition Means) 25, 25 'Waveform Signal Generation Circuit (Waveform Signal Generation Means)

Claims (1)

Claim: What is claimed is: 1. A time axis correction circuit configured to remove the jitter by phase-modulating a D / A conversion clock of the video signal including the jitter. The memory means has a memory means for storing a plurality of phase error signals, each of which detects a phase difference from the D conversion clock, and a coefficient adding means for adding a plurality of coefficients to the phase error signals stored by the memory means. 1 of the phase error signal added by the coefficient and the plurality of phase error signals stored in the memory means.
And a waveform signal generating means for generating a waveform signal which linearly interpolates between the center and the end of one horizontal synchronization period, respectively, and the waveform signal generated by the waveform signal generating means A time axis correction circuit characterized in that the D / A conversion clock is phase-modulated by using the time axis correction circuit.