JPH0514919B2 - - Google Patents

Description

TECHNICAL FIELD The present invention relates to a pitch control device that controls the pitch between an original sound and a reproduced sound by changing the frequency of an audio signal according to a command.

BACKGROUND ART Data obtained by sampling an audio signal at a predetermined period is sequentially stored in a RAM (Random Access
As a pitch control device that controls pitch by changing the frequency of the reproduced audio signal obtained from the read data by writing data into a storage means such as Memory) and changing the reading cycle of the written data according to the command. A device as shown in FIG. 1 was devised by the present inventor. In FIG. 1, an audio signal is supplied to an A/D (analog-to-digital) converter 1 via an input terminal IN. In the A/D converter 1, the audio signal is sampled at a predetermined period, and then converted into digital data of a predetermined number of bits corresponding to the obtained sample value, and sent to the data bus 2.
Data bus 2 is connected to data input/output terminals of RAM 3. A counter 5 and a multiplexer 6 as write position information generating means are connected to the address input terminal of the RAM 3 via a multiplexer 4.
output is alternatively supplied. multiplexer 6
selectively outputs the output data of the counter 7 as the first read position information generating means when the control input is low level, and outputs the output data of the adder 8 as the second read position information generating means when the control input is high level. The output data is configured to be selectively output. The adder 8 is configured to output data obtained by adding the output data of the counter 7 and predetermined data N.

The RAM 3 is supplied with a write pulse P _W and a read pulse _PR from a pulse generation circuit 9 .
The RAM 3 is configured to be in a write mode when a write pulse P _W is generated and to be in a read mode when a read pulse _PR is generated. Further, the pulse generating circuit 9 generates a write pulse P _W at a predetermined period based on the clock while generating a clock, and reads out a read pulse P _R at a period according to a command from an operation section (not shown). and a timing pulse. The write pulse P _W and read pulse P _R output from this pulse generation circuit 9 are as follows:
It is also supplied to the clock input terminals of counters 5 and 7, respectively. Further, the output of the counter 5 is selectively supplied from the multiplexer 4 to the address input terminal of the RAM 3 for a predetermined period of time only when the write pulse P _W is generated, and at other times, the output of the multiplexer 6 is supplied to the address input terminal of the RAM 3. A switching control signal generation circuit 10 is provided for generating a control input for the multiplexer 4 to be supplied to the terminal.

Therefore, the digital data sent to the data bus 2 is sequentially stored in the RAM 3 at the storage location designated by the output of the counter 5. and,
When a read pulse _PR is generated at a period according to the command, the digital data written in each memory location of the RAM 3 is read out in the order in which it was written, and the data is input to the latch circuits 11 and 12 via the data bus 2. Supplied to the terminal. The clock input terminals of latch circuits 11 and 12 are supplied with the Q outputs of D-type flip-flops 14 and 15 in timing control circuit 13. D
The D input terminal of the flip-flop 14 is supplied with a high-level timing pulse having the same repetition frequency as the read pulse _PR from the pulse generating circuit 9. This D-type flip-flop 14
The Q output of is supplied to the latch circuit 11 and the D
It is supplied to the D input terminal of a flip-flop 16. The Q output of the D-type flip-flop 16 is D
The D input terminal of the flip-flop 15 and the control input terminal of the multiplexer 6 are supplied. The clock input terminals of these D-type flip-flops 14 and 15 are directly supplied with the clock output from the pulse generating circuit 9. Further, the clock input terminal of the D-type flip-flop 16 is supplied with a clock output from the pulse generation circuit 9 via an inverter 17.

When the Q outputs of D-type flip-flops 14 and 15 become high level, the latch circuits 11 and 12
Data supplied from the RAM 3 via the data bus 2 is latched. The output data of these latch circuits 11 and 12 are supplied to latch circuits 18 and 19, respectively, and are latched when a high level timing pulse occurs. These latch circuits 18 and 19 output data are sent to a D/A converter 20.
and 21, and then supplied to VCAs (variable gain amplifiers) 22 and 23, respectively. The VCAs 22 and 23 are configured to amplify the input signal with gains that vary in opposite directions in response to changes in level control data of a predetermined number of bits supplied to the control input terminals, for example. The output data of the level control data generation circuit 24 is supplied to the control input terminals of these VCAs 22 and 23. The level control data generation circuit 24 outputs the output data of the counter 5 and the output data of the counter 7.
When the difference between the output data of the adder 8 and the output data of one of the adders 8 becomes less than a predetermined value, binary data that changes every time the clock is generated a predetermined number of times is output as level control data. Then, the outputs of the VCAs 22 and 23 are added by the adder circuit 25 and then output to the output terminal OUT.

In the above configuration, the D-type flip-flop 1
4 to 16 are assumed to latch the D input at the rising edge of the clock input. Then, when a clock a and a high-level timing pulse b as shown in FIGS. 2A and 2B are generated, the Q output c of the D-type flip-flop 14 will exceed the timing signal b by up to one clock as shown in FIG. 2C. The result is a signal similar to the signal obtained with a delay of 1 minute. Further, the Q output d of the D-type flip-flop 16 is a signal obtained by delaying the Q output c by the time between the rising edge and the falling edge of the clock a, as shown in FIG. Further, the Q output e of the D-type flip-flop 15 is a signal obtained by delaying the Q output c by one clock, as shown in FIG. Therefore, when the Q output d, which is the control input of the multiplexer 6, is at a low level, the Q output c is at a high level, and when the Q output d is at a high level, the Q output e is at a high level. Therefore, when the output data of the counter 7 is used as the read address R and is the address input of the RAM 3, the data read from the RAM 3 is latched in the latch circuit 11. Further, when the output data of the adder 8 is the address input of the RAM 3 as the read address R', the data read from the RAM 3 is latched in the latch circuit 12.

The audio signal obtained from the data latched in the latch circuit 12 is usually attenuated by the VCA 23 and sent to the adder circuit 23 as shown in FIG. 3B.
Instead, only the audio signal obtained from the data latched by the latch circuit 11 is supplied as is to the adder 25 via the VCA 22, as shown in FIG. This latch circuit 1
The frequency of the audio signal obtained from the data latched at 1 changes in accordance with the repetition frequency of the read pulse _PR , which changes in accordance with the command, thereby controlling the pitch of the reproduced sound.

If the repetition frequency of the read pulse P _R and write pulse P _W is different, the read address R or
R' and the write address W output from the counter 5 will be close to each other. Then, the gain of VCA22 gradually decreases and at the same time
The gain of the VCA 23 begins to gradually increase (time t). Therefore, the signal level of the audio signal obtained from the data latched in the latch circuit 11 and passed through the VCA 22 gradually decreases, and at the same time, the signal level of the audio signal obtained from the data latched in the latch circuit 12 and passed through the VCA 23 becomes smaller. gradually becomes larger. Here, when the gain of the VCA 22 becomes 0 and the gain of the VCA 23 becomes 1, the level control data generation circuit 24
When the VCA end signal is generated and then clock a is generated a predetermined number of times (time t ₂ ), the VCA end signal disappears and at the same time the output data of the adder 8 is preset in the counter 7 and the output data of the level control data generation circuit 24 It is assumed that the VCA returns to its initial state and the gains of the VCAs 22 and 23 become 1 and 0, respectively. Then, the audio signal derived to the output terminal OUT is a signal obtained from the data read from the storage location specified by the read address R until time _t1 , as shown in FIG. The _two audio signals obtained from the data read from the storage locations specified by the read addresses R and R' from t ₁ to t 2 are
The signal is obtained by adding and combining the signals at a ratio determined by the gains of the VCAs 22 and 23. And the time
After t ₂ , the signal derived to the output terminal OUT is specified by the output data of the counter 7, which has been preset with the output data of the adder 8 and now outputs the data corresponding to the read address R'. The signal is obtained from the data read from the stored storage location.

Therefore, when the write address becomes equal to the read address R or R', new data may be written to a storage location from which no data has been read, or new data may be written to a storage location from which data has already been read. If a discontinuous change occurs in the reproduced sound because it is read out again before it is read out, it is possible to prevent the change from occurring gradually and impairing the auditory sensation.

However, at a low level as shown in Figure 4A,
Immediately after the VCA end signal disappears, the counter 7 is preset with the output data of the adder 8, and the data read from the storage location specified by the read address R' is latched into the latch circuit 11. The data that was previously latched in the latch circuit 11 when the Q output c became high level and that was obtained by the read address R is now latched in the latch circuit 18 as shown in Figure B. . Therefore, after the VCA end signal disappears, the audio signal obtained by the read address R is instantaneously mixed into the audio signal obtained by the read address R', causing a problem that noise is generated. still,
FIG. 4C shows the data latched in the latch circuit 19.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a pitch control device that can perform pitch control while preventing the generation of noise.

In the pitch control device according to the present invention, when the storage position indicated by the write position information and the storage position indicated by the first or second read position information are close to each other, the pitch control device according to the present invention Gradually lowering the signal level of the first reproduced audio signal obtained from the stored data of the second storage means that temporarily stores the data read from the storage position, and at the same time the storage indicated by the second read position information. After gradually increasing the signal level of the second reproduction audio signal obtained from the stored data of the third storage means for temporarily storing the data read from the position so that only the second reproduction audio signal is output, the second reproduction audio signal is outputted. The first readout position information is changed to the same information as the second readout position information, and only the first reproduction audio signal is output, and while only the second reproduction audio signal is output, the second and third reproduction audio signals are changed. The configuration is such that the storage contents of the storage means are the same.

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 5 to 7.

In FIG. 5, an A/D converter 1, data bus 2, RAM 3, multiplexers 4, 6, counters 5, 7, adder 8, pulse generation circuit 9, switching control signal generation circuit 10, latch circuits 11, 12, 1
8, 19, timing control circuit 13,
D/A converters 20, 21, VCAs 22, 23, level control data generation circuit 24, and addition circuit 25 are connected in the same way as in the device shown in FIG. However, in this example, the Q output C of the D-type flip-flop 14 in the timing control circuit 13 is not directly supplied to the latch circuit 11, but is
(AND) is supplied to one input terminal of the gate 26. A VCA end signal is supplied from the level control data generation circuit 24 to the other input terminal of the AND gate 26. The output of this AND gate 26 is supplied to one input terminal of an OR (logical product) gate 27. The other input terminal of the OR gate 27 is supplied with the Q output e of the D-type flip-flop 15. The output f of this OR gate 27 is supplied to the latch circuit 11.

In the above configuration, when a low level VCA end signal as shown in FIG. 6A is generated, the AND gate 2
Since the output of 6 is low level, OR gate 27
The output f is as shown in B in the same figure and Q as shown in D in the same figure.
Similarly to the output e, the Q output d as shown in C in the same figure is 1/2
The signal is delayed by a clock. Also, VCA
When there is no signal, the Q output c is supplied to one input terminal of the OR gate 27 via the AND gate 26, so the output f of the OR gate 27 goes high at the same timing as the Q output c goes high. level. Therefore, when the VCA end signal is not present, an operation similar to that of the device of FIG. 1 is obtained. When the VCA termination signal is present as shown in FIG. 7A, the output f supplied to the latch circuit 11.
Since the signal becomes high level at the same timing as the Q output e, the latch circuit 18 that latches the output data of the latch circuit 11 as shown in FIG. The data obtained by address R' will be latched. Therefore, immediately after the VCA end signal disappears, the audio signal obtained by the read address R is not mixed into the audio signal obtained by the read address R', and the generation of noise is prevented. Become.

Effects As described in detail above, the pitch control device according to the present invention has the advantage that the latch circuits 11 and 12
Since the configuration is such that the data latched in both are the same, when the read address corresponding to the latch circuit 11 is switched to the read address corresponding to the latch circuit 12, the output of the latch circuit 11 Even if there is a delay in the latch timing in the data latch circuit 18, noise can be prevented from occurring.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram showing a pitch control device proposed by the inventors, FIG. 2 is a waveform diagram showing the circuit operation of the timing control circuit 13 in the device shown in FIG. 1, and FIG. 4 are diagrams showing the operation of the device shown in FIG. 1, FIG. 5 is a circuit block diagram showing an embodiment of the present invention, and FIG. 6 is a diagram showing the timing control circuit 13 in the device shown in FIG. The waveform diagram, Figure 7, showing the circuit operation is as follows:
FIG. 6 is a diagram showing the operation of the device of FIG. 5; 1...A/D converter, 3...RAM, 5, 7...
...Counter, 8...Adder, 11, 12, 18,
19... Latch circuit, 13... Timing control circuit.

Claims (1)

[Claims] 1. A first storage means having a plurality of storage locations, and a first storage means that changes at the predetermined period so that data obtained by sampling an audio signal at a predetermined period is sequentially written and stored in the plurality of storage locations. a write position information generating means for generating write position information, and generating first read position information so that the data written to the plurality of storage positions are sequentially read out at a period according to a command in the order in which they were written. a first read position information generating means for generating second read position information indicating a position separated from each other by a predetermined distance from the first read position information; a second storage means for temporarily storing data read from the storage position indicated by the second reading position information; and a third storage means for temporarily storing data read from the storage position indicated by the second read position information. storage means, the storage position indicated by the write position information and the first or second
When the storage position indicated by the read position information is close to the storage position, the signal level of the first reproduced audio signal obtained from the data stored in the second storage means is gradually lowered, and the signal level is simultaneously stored in the third storage means. After gradually increasing the signal level of the second reproduced audio signal obtained from the reproduced data so that only the second reproduced audio signal is output, the first read position information is made the same as the second read position information. information, and while only the first reproduced audio signal is output, and while only the second reproduced audio signal is output, the stored contents of the second and third storage means are the same. A pitch control device characterized by: