JPH05150856A - GPS receiver - Google Patents

Abstract

(57) [Abstract] [Purpose] CP in a battery-powered GPS receiver
By reducing the current consumption of U, the operating time of the device per battery charge is extended. [Structure] CPU 1 equipped with frequency divider 3, selector 5, etc.
The output voltage of the CPU drive clock signal can be changed by setting the output port 4, and the battery voltage monitoring circuit 6 for monitoring the voltage of the battery 7 is provided to detect that the battery voltage has dropped below a preset voltage. In this case, it is possible to reduce the current consumption of the CPU 1 by selecting a clock signal of a lower frequency output from the frequency divider 3 as the CPU drive clock signal in accordance with an instruction from the CPU 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a battery-operated GP which receives a signal from an artificial satellite to detect a position.
Regarding S receiver.

[0002]

2. Description of the Related Art In recent years, various wireless communication devices using artificial satellites have been popular, and position detectors using artificial satellites called GPS receivers have become widespread.

A conventional GPS receiver will be described below. As shown in FIG. 2, the main configuration of the conventional GPS receiver is a CPU 1 that controls the calculation and control, and an oscillator 2 that oscillates a clock signal of a constant frequency suitable for driving the CPU 1.

The operation of the GPS receiver having the above components will be described below. First, since the output clock signal from the oscillator 2 is used as it is as the drive clock signal of the CPU 1, the drive clock signal of the CPU 1 is constant if the error of the oscillator 2 is ignored. However, in a battery-powered GPS receiver, inoperability occurs due to the life of the battery, so intermittent operation or
It has been devised to reduce the total current consumption of the entire device. Further, it has been found that most of the total current consumption is consumed in the CPU 1 and the peripheral logic section, and the current consumption of the CPU 1 is proportional to the drive clock signal frequency from the oscillator 2 if the load is constant.

[0005]

However, in the above-mentioned conventional configuration, if the CPU load is constant, the CPU drive clock signal is constant, so the current consumption of the CPU depends on the load and the frequency of the drive clock signal. There was a problem that the operation time of the device when using the battery was short, since it did not drop below a certain level.

The present invention solves the above-mentioned problems of the prior art. By reducing the current consumption of the CPU, the operating time of the device for one battery charge is lengthened.
It is an object to provide a PS receiver.

[0007]

In order to achieve the above object, the GPS receiver of the present invention comprises a frequency divider for frequency-dividing and outputting an output clock signal from an oscillator, and a selector for performing a write access from a CPU. It has an output port for changing the logic of the switching signal, and has a configuration such as a selector and a battery voltage monitoring circuit for switching the output of the frequency divider and the output of the oscillator by the switching signal to supply the CPU drive clock signal to the CPU.

[0008]

According to the present invention, in the above configuration, when the battery voltage monitoring circuit detects that the battery voltage has dropped below a predetermined voltage, the CPU performs write access to the output port and the logic of the switching signal. By changing the, the selector can select the output of the frequency divider and drive the CPU with a clock signal of a lower frequency.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

As shown in FIG. 1, the GPS receiver of the present invention comprises the same components as those of the conventional example of the CPU 1 and the oscillator 2, as well as a frequency divider 3, an output port 4, a selector 5 and the like. Each circuit is driven by a battery 7 and has a battery voltage monitoring circuit 6.

With respect to the GPS receiver having the above components, the relationship and operation of each component will be described with reference to FIG.

First, the clock signal output from the oscillator 2 is frequency-divided by the frequency divider 3 to be output, and the switching signal of the selector 5 is generated at the output port 4 by the write access from the CPU 1. The selector 5 selects the input from the terminal A and outputs it from the terminal Y when the logic of the terminal S is "0", and selects the input from the terminal B and outputs from the terminal Y when the logic of the terminal S is "1". Output. Here, the output from the output port 4 is output to the terminal S, the clock signal output from the oscillator 2 to the terminal A, and the clock signal output from the frequency divider 3 to the terminal B is 2
Input the divided clock signal, and output the output of terminal Y to CPU
It is input to the clock input terminal of the CPU 1 as a driving clock signal. The battery voltage monitoring circuit 6 constantly monitors the voltage of the battery 7, and when the voltage drops below a predetermined voltage, the CP
Supply an output signal to U1.

When the CPU 1 detects the voltage drop of the battery 7 based on the output of the battery voltage monitoring circuit 6, it makes a write access to the output port 4, sets the logic of the switching signal to "1", and selects the selector 5. The output of the frequency divider 3 is selected and switched so as to be output as the CPU drive clock signal from the terminal Y. This makes the frequency of the CPU drive clock signal halved and the current consumption of the CPU 1 halved.
This makes it possible to prolong the operating time of the device.

[0014]

As is apparent from the above embodiments, the present invention divides the frequency of the output clock signal from the oscillator and outputs it, and the output which generates the selector switching signal by the write access from the CPU. Since the CPU is equipped with a port, a selector for switching the output of the frequency divider and the output of the oscillator by the switching signal and supplying the CPU drive clock signal to the CPU, and the battery voltage monitoring circuit, the CPU can monitor the battery voltage, By changing the logic of the switching signal by performing write access to the output port to switch the clock frequency with respect to the remaining battery power,
The selector is switched to select and output the output of the frequency divider, whereby the frequency of the drive clock of the CPU is reduced and the current consumption of the CPU is reduced, and the operating time of the device with respect to the battery life can be lengthened accordingly. It is possible to realize an excellent GPS receiver having the effect of being possible.

[Brief description of drawings]

FIG. 1 is a block diagram of a GPS receiver according to an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional GPS receiver.

[Explanation of symbols]

 1 CPU 2 Oscillator 3 Divider 4 Output Port 5 Selector 7 Battery

Claims (1)

[Claims] 1. An oscillator that oscillates a clock signal of a certain constant frequency while controlling calculation and control by a built-in CPU, a frequency divider that divides and outputs the clock signal output from the oscillator, and an oscillator from the oscillator. Output clock signal from the frequency divider and the output clock signal from the frequency divider are selected by a switching signal and used as a CPU drive clock.
And a battery voltage monitoring circuit for monitoring the battery voltage and an output port for changing the theory of the switching signal of the selector by the write access of the CPU, and the battery voltage monitoring circuit has a voltage equal to or lower than a predetermined voltage. When the CPU detects that the battery voltage has dropped, the CPU performs write access to the output port to change the theory of the switching signal, and the selector switches the output of the frequency divider to a lower frequency. GPS receiver designed to output.