JPH05160738A - Cmi decoding system - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a CMI decompression method capable of always correctly decomposing regardless of the input polarity of a CMI code. [Structure] A phase synchronization pulse that is phase-synchronized with the changing point of the CMI code and has a repetition cycle equal to 1/2 of the repetition cycle of the CMI code is divided by a binary counter and divided into positive and negative phases. Get the lap output. On the other hand, when the CMI code has the same polarity for more than ½ of the repetition cycle, the logical product of the same polarity detection output that sets the output to “1” and the positive phase and negative phase frequency division outputs is calculated, and the positive phase side logic is obtained. The phase of the frequency-divided output is controlled so that the product output is more frequently "1" than the negative-phase side logical product output, and the same polarity detection output is output when the positive-phase side frequency-divided output is "1". The CMI code is restored by determining

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMI (coded mark inversion) code decoding system.

[0002]

2. Description of the Related Art When a data code is transmitted using a balanced pair cable, there is no DC component and C having a timing component.
Generally, it is converted into MI code or the like. The CMI code is "01" corresponding to the data "0" as shown in FIG.
(The polarity changes from "0" to "1" at the middle point), and "00" or "11" is alternately sent in correspondence with the data "1". In order to recover the original data code by receiving this, the falling point of the CMI code is detected (normal connection in FIG. 3) and synchronized with the phase locked loop circuit which outputs a pulse equal to the code repetition period. , The boundary of the code is recognized, and it is determined whether the polarities are the same or different in the first half and the second half of the CMI code based on the sync output pulse.
A method of determining "0" is used.

[0003]

FIG. 3 shows the case of replacing the tips and rings of the balanced pair of cables in the transmission line with the above-mentioned conventional method.

As shown in [at the time of reverse connection], the trailing edge detection output does not always show the switching point (boundary) of the code, and there is a drawback that the CMI cannot be restored. The present invention eliminates the above-mentioned drawbacks of the conventional method, and enables CM even in the case of reverse connection.
The purpose is to enable the reconstruction of I.

[0004]

[Means for Solving the Problems] In order to achieve the above object,
In the present invention, first, all the changing points including the rising point of the CMI are detected, and the cycle is 1/2 of the repetition cycle of the data code.
Generates a pulse that is phase-synchronized with the above change point. Next, this pulse is divided by 2 with the clock input to obtain frequency-divided outputs of the positive and negative phases whose repetition period is equal to the repetition period of the data code. However, one clock of the input clock is removed and the divided output and CMI are obtained. It also has a function of changing the phase relationship of the codes by 180 degrees. On the other hand, in the CMI code, a detection circuit is provided to set the output to “1” when the same polarity continues for ½ or more of the code repetition period, and the detection output and the positive and negative phase-divided outputs are provided. AND of the positive phase side logical product output "1" is generated more frequently than the negative phase side,
Controls the phase of the divided output.

[0005]

As a result of the above, from the characteristics of the CMI code, the "1" section of the positive phase frequency division output coincides with the latter half section of the CMI code, and it is determined in this section whether the polarities coincide with the preceding section. As a result, the CMI code can be restored.

[0006]

An embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram of a CMI decoding method showing an embodiment of the present invention, and FIG. 2 is an operation waveform diagram showing an outline of the operation. The block diagram of FIG. 1 shows a change point detection unit 1, a digital phase locked loop circuit 2, a shift register 3, 4, an exclusive OR circuit 5, an AND gate 6, a binary counter 7, a positive phase side AND circuit 8, and an inverse circuit. Phase side AND circuit 9,
It is composed of an up / down counter 10, a clock removal flip-flop 11, a decoding flip-flop 12, and the like. In FIG. 1, the clock pulse is a pulse having a repetition frequency that is an integral multiple (for example, 32 times) of the repetition frequency of the data code of the input CMI. The change point detection unit 1 has 2
Consisting of a shift register of stages and an exclusive OR circuit,
The CMI input signal is shifted using the above clock, and the exclusive output of the output of the first stage and the output of the second stage of the shift register is exclusive-ORed to obtain a detection output in synchronization with the change point of CMI. Next, in the phase-locked loop circuit 2, the above-mentioned detection output is used as a phase comparison input, the phase is synchronized with the detection output as shown in FIG. 2, and the repetition cycle is 1/2 of the CMI code cycle.
Create a sync pulse equal to. Subsequently, in the same polarity detection circuit including the two-stage shift registers 3 and 4 and the exclusive OR circuit 5, the case where the same polarity continues while the CMI code is 1/2 or more of the code period is shown in FIG. Obtain the detection output. On the other hand, the binary counter 7 divides the phase-locked pulse output from the phase-locked loop circuit 2 to obtain the positive and negative phase-divided outputs, but has the AND gate 6 in the clock input circuit. One clock of the phase synchronization pulse which is the input clock of the binary counter 7 is removed, and the phase relationship between the CMI code and the positive phase and negative phase divided outputs can be changed by 180 degrees. In addition, in order to maintain the correct phase relationship between the CMI code and the positive-phase and negative-phase frequency-divided outputs, up / down (hereinafter U / D)
A counter 10, positive-phase side and negative-phase side AND circuits 8, 9, a clock removal flip-flop 11 and the like. The positive-phase side AND circuit 8 takes the logical product of the same polarity detection output and the positive-phase frequency division output, and the output is added to the down side input of the U / D counter 10. The opposite-phase side AND circuit 9 takes the logical product of the same polarity detection output and the opposite-phase frequency division output, and the output is connected to the up-side input of the U / D counter. In the case where the U / D counter is set to the quaternary, the period in which the positive phase frequency division output is "1" in the first half of the CMI code (the period before the clock removal pulse in Fig. 2 becomes "0") Then, the number of times the negative-phase side logical product output becomes “1” becomes larger than the number of times that the positive-phase side logical product output becomes “1”,
The U / D counter counts up to “11”, and when “1” is output to the negative-phase side AND output in this state, the clock removal flip-flop 11 outputs an output for one clock, and U / D The counter returns to the "00" state. As a result, since the binary counter 7 has its clock removed by the input AND gate 6, the stepping is stopped for one clock, and the phase relationship between the CMI code and the positive phase and negative phase divided outputs is 180 degrees. Therefore, the positive phase frequency division output becomes "1" in the latter half of the CMI code. Therefore, after that, the frequency at which the logical product output on the positive phase side becomes “1” becomes higher than the output on the negative phase side, and U /
The D counter holds the state near "00", and the correct phase relationship is maintained. Even if a down count input is input while the U / D counter is "00", the state of "00" is not changed. With the phase relationship between the CMI code and the normal phase frequency division output maintained correctly, as shown in FIG. 1, the decoding flip-flop 12 outputs 1, 0 of the same polarity detection output in the latter half period of the CMI code. By identifying, the data code is correctly decoded. In the above description, it is clear that the normal phase frequency division output and the negative phase side frequency division output have the same operation even if they are replaced with each other.

[0007]

As described above, according to the present invention, C
Even if the MI code is connected with the opposite polarity, the data code can be correctly restored. Therefore, when transmitting using a balanced pair cable, etc., it is not necessary to be aware of the polarity of the chip, ring, etc., and the installation work is extremely easy. Become. In addition, this decoupling method can be configured as a digital circuit and can be easily integrated into an integrated circuit, which has a great effect on cost reduction of the device.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a waveform diagram showing a schematic operation of the block diagram.

FIG. 3 is a waveform diagram showing CMI waveforms and timing components.

[Explanation of symbols]

 1 Change Point Detection Unit 2 Digital Phase Locked Loop Circuit 3, 4 Shift Register 5 Exclusive OR Circuit 6 AND Gate 7 Binary Counter 8 Positive Phase Side AND Circuit 9 Reverse Phase Side AND Circuit 10 Up Down Counter 11 Clock Removal Flip Flop 12 Decoding Flip Flop

Claims (1)

[Claims] 1. A phase synchronization pulse which is phase-synchronized with a changing point of a CMI code and whose repetition period is equal to ½ of the repetition period of the CMI code is divided into two and divided into a positive phase and a negative phase. The logical product of the same polarity polarity detection output that sets the output to "1" when the same polarity continues in the CMI code for 1/2 or more of the repeating cycle and the frequency division outputs of the positive and negative phases The phase of the frequency division output is controlled so that the logical product output on the positive (reverse) phase side has a higher frequency of "1" than the logical product output on the reverse (positive) phase side. A CMI decoding method characterized in that the same polarity detection output is discriminated when the frequency division output is "1".