JPH0548588A - Parity block synchronization method - Google Patents

Abstract

(57) [Abstract] [Purpose] A parity block synchronization method for synchronizing a parity block in which a parity bit is added to a transmission signal, and a parity block synchronization capable of quickly synchronizing the parity block with a simple circuit configuration. The purpose is to provide a method. [Structure] 2n divider circuit 200 for inputting an mB1P encoded signal with a parity bit, dividing it by 2n and outputting it
And a rising / falling detection unit 300 which inputs the output of the 2n frequency divider circuit and detects a rising or falling part and outputs a detection pulse, and a clock which is input and shifts by a constant phase under a predetermined condition. Output by the clock shift unit 110, an m + 1 frequency divider circuit 120 that inputs the output of the clock shift unit and frequency-divides and outputs it, and an output of the rising / falling detection unit and the m + 1 frequency divider circuit. And a coincidence detection unit 600 that outputs a detection signal to the clock shift unit, and is configured to synchronize the parity blocks.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parity block synchronization system for synchronizing a parity block in which a parity bit is added to a transmission signal.

In the receiving section of the transmission device, it is necessary to synchronize the parity blocks in order to extract only the main signal excluding the parity bits from the reception signal to which the parity bits are added. In this case, there is a demand for a parity block synchronization method that can synchronize the parity blocks quickly and with a simple circuit configuration.

[0003]

2. Description of the Related Art Conventionally, in order to synchronize a parity block, by focusing on a frame pattern in a transmission path signal and performing frame synchronization, the parity block is synchronized and only a main signal is removed except a parity bit. I was taking it out.

[0004]

As described above, conventionally, since the parity blocks are synchronized by taking the frame synchronization, it takes a long time to establish the synchronization, and there is a problem that the circuit scale becomes large. there were.

Therefore, an object of the present invention is to provide a parity block synchronization system capable of synchronizing parity blocks quickly and with a simple circuit configuration.

[0006]

The above problems can be solved by the structure of the circuit shown in FIG. That is, in FIG. 1, 20
Reference numeral 0 is a 2n frequency dividing circuit which inputs a signal having a parity block mB1P encoded by a parity bit, divides it by 2n (n: a positive integer), and outputs it.

Reference numeral 300 is a rising / falling detection unit which receives the output of the 2n frequency dividing circuit 200, detects the rising or falling portion of the input pulse, and outputs a detection pulse.

Reference numeral 110 denotes a clock shift unit which inputs a clock extracted from an input signal to the 2n frequency dividing circuit 200, shifts it by a constant phase under a predetermined condition, and outputs it. 120
Is an m + 1 frequency divider circuit that receives the output of the clock shift unit 110, divides it by m + 1, and outputs the result.

Reference numeral 600 denotes a rising / falling detection unit 30.
It is a coincidence detection unit that inputs the detection pulse of 0 output and the output of the m + 1 frequency dividing circuit 120, detects the coincidence or non-coincidence of the both, and outputs a detection signal to the clock shift unit 110.

Then, the parity blocks are configured to be synchronized.

[0011]

In FIG. 1, a 2n frequency dividing circuit 200 inputs a signal having a parity block mB1P encoded by a parity bit, frequency-divides it by 2n (n: positive integer), and outputs it. When the parity bit is "1", the output pulse is always divided by 2n at the timing of the parity bit, from "1"
The change point of the fall to "0" occurs. Also, when an error occurs in the input signal, a rising transition point from "0" to "1" occurs.

Therefore, the output divided by 2n is input to the rising / falling detection section 300, the rising edge or the falling edge of the input pulse is detected, and the detection pulse output is added to the coincidence detection section 600.

On the other hand, the clock extracted from the input signal to the 2n frequency dividing circuit 200 is input to the clock shift section 110,
When a mismatch pulse is input from the match detection unit 600, the input clock is shifted by a certain phase and output. When the coincidence pulse is input from the coincidence detection unit 600, the clock is output without shifting.

The clock output of the clock shift unit 110 is m
It is input to the +1 frequency dividing circuit 120, frequency-divided by m + 1, the rising portion of the m + 1 frequency-divided pulse is detected, and a detection pulse is output. As a result, the m + 1 frequency divider circuit 120 outputs a detection pulse for each m + 1 bit. This matches the period of the parity bit.

The detection pulse of the output of the m + 1 frequency dividing circuit 120 and the detection pulse of the output of the rising / falling detection unit 300 described above are input to the coincidence detection unit 600 to detect the coincidence or non-coincidence of the two, and the coincidence is detected. Alternatively, a pulse indicating a mismatch is output and added to the clock shift unit 110.

As a result, when the coincidence detecting section 600 detects a disagreement between the detection pulse of the output of the rising / falling detecting section 300 and the detection pulse of the output of the m + 1 frequency dividing circuit 120, the parity bit (or parity block) is detected. Is not synchronized, and the clock shift unit 110 continues to output the clock obtained by shifting the input clock.

Further, when the coincidence detecting section 600 detects the coincidence of the both and outputs the coincidence pulse, it means that the parity block is synchronized, and the clock shift section 110 outputs the clock without shifting the phase. .. At this time, the output of the m + 1 frequency dividing circuit 120 becomes the timing of the parity bit.

In this way, the parity blocks can be synchronized.

[0019]

FIG. 2 is a block diagram showing a circuit configuration of an embodiment of the present invention. FIG. 3 is a block diagram showing the configuration of the rising / falling detection unit of the embodiment.

FIG. 4 is a time chart (No. 1) for explaining the operation of the embodiment. FIG. 5 is a time chart (No. 2) for explaining the operation of the embodiment. The same reference numerals denote the same objects throughout the drawings.

The information of the mB1P code transmitted through the transmission line is, for example, as shown in (1) of FIG. 4, a 4-bit main signal (in the case of m = 4) and a 1-bit parity bit (P in FIG. 4). (Shown) is composed of repeated parity blocks. Then, the parity bit is inserted so that the number of "1" in m bits is an even number. A frame pattern (not shown) is applied to a part of the main signal at regular intervals.
Is inserted.

This transmission path information is input as an NRZ-encoded data signal as shown in (2) of FIG. 4, and the NRZ / RZ conversion section 1 shown in FIG. 2 uses RZ as shown in (3) of FIG.
It is converted into a coded data signal and output. This output is 2
In addition to the frequency dividing circuit 2, the frequency of the input data is converted to ½ and output as shown in (4) of FIG. It should be noted that, in general, the frequency division is not limited to two, and an even ratio (2n:
The frequency division of 1) is sufficient.

The output divided by two is applied to the rising / falling detecting section 3. The rising / falling detection unit 3 is composed of, for example, the circuit shown in FIG. 3, and divides an input signal into a logical product circuit (hereinafter referred to as an AND circuit) 16 and a negative logical sum circuit (hereinafter referred to as a NOR circuit) 17 respectively. One of the input terminals is added to the delay circuit 14. The delay circuit 14 delays the phase of the input signal by, for example, one clock and outputs the delayed signal. The phase of the signal is inverted via the inverter 15 and then applied to the other input terminals of the AND circuit 16 and the NOR circuit 17.

As a result, the NOR circuit 17 outputs a pulse having a width of, for example, 1 clock at the trailing edge of the pulse divided by two. (In (5) of FIG. 4, the parity bit P
The timing (indicated by the arrow) that coincides with the phase of (). This falling detection pulse is applied to one input terminal of an AND circuit 5 via a logical sum circuit (hereinafter referred to as an OR circuit) 4 in the timing coincidence detection section 7, and its phase is inverted to make the AND circuit 6 Add to one input terminal.

On the other hand, in the clock shift circuit 12, when the parity block is not synchronized, "H" is output from the Q inversion terminal of the flip-flop circuit (hereinafter referred to as FF) 8.
A level signal is output and applied to one input terminal of the AND circuit 10. A pulse output generated from the 1-pulse generator 9 at a constant cycle is applied to the other input terminal of the AND circuit 10.

As a result, the AND circuit 10 outputs a pulse at a constant period when the parity blocks are not synchronized. When the output pulse of the AND circuit 10 is applied to one input terminal of the NOR circuit 11 and the original clock is applied to the other input terminal, the NOR circuit 11 outputs a clock train from which pulses have been omitted at a constant cycle.

The output clock of the NOR circuit 11 is divided by 5
In addition to 13, the frequency of the input clock is divided by 5, and the rising portion is detected and a detection pulse is output. mB1
Since the case of m = 4 of the P code has been described, (m
The +1) frequency dividing circuit is used as the frequency dividing circuit, but naturally, this changes depending on the value of m. (Of FIG. 4
See (a) and (b) in (6) and (a) and (b) in (7).

The output of the frequency dividing circuit 13 is applied to the other input terminals of the AND circuits 5 and 6 in the timing coincidence detecting section 7. As described above, the falling detection pulse of the output of the rising / falling detection unit 3 is applied to one input terminal of the AND circuit 5 via the OR circuit 4, and one input terminal of the AND circuit 6 is connected to the other input terminal. The phase of the fall detection pulse is inverted and added.

Then, when the phase of the rising portion of the falling detection pulse and the rising portion of the clock pulse divided by 5, match, the AND circuit 5 outputs a pulse indicating the matching of the timing. Further, when the phases of the rising edge of the rising edge detection pulse and the rising edge of the clock pulse divided by 5, do not match, the AND circuit 6 outputs a pulse indicating a timing mismatch. (See (8) and (9) in Fig. 4).

A pulse indicating the coincidence of the output timing of the AND circuit 5 is applied to the clock (C) terminal of the FF8, and AN
A pulse indicating the disagreement of the output of the D circuit 6 is applied to the reset (R) terminal of the FF8. Then, when the phases of the rising edge of the falling detection pulse and the rising edge of the clock pulse divided by 5, do not coincide with each other from the Q terminal of FF8 as shown in (10) of FIG.
Continue to output "H" level signal.

On the other hand, when both match, the Q of FF8
Since the "L" level signal is output from the inverting terminal, the pulse output from the 1-pulse generator 9 is not applied to the NOR circuit 11, and the input clock is directly transmitted to the 5 frequency dividing circuit 13 via the NOR circuit 11. Added.

As a result, the divide-by-5 circuit 13 can output a pulse for detecting the rising portion at the timing of the parity bit of the input signal to synchronize the parity block.

Further, when an error occurs in the input transmission path information as shown in FIG. 5A, the output of the divide-by-2 circuit 2 is output at the parity bit timing as shown in FIG. 5D. To
There is a transition point from "0" to "1". This rising part is detected by the rising / falling detection part 3 and a detection pulse is added to the timing coincidence detection part 7. Subsequent operations are the same as those in the case where no error occurs in the above-mentioned transmission path information, and therefore description thereof will be omitted.

As a result, the parity blocks can be synchronized quickly and with a simple circuit configuration.

[0035]

As described above, according to the present invention, the parity blocks can be quickly synchronized with a simple circuit configuration.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention,

FIG. 2 is a block diagram showing a circuit configuration of an embodiment of the present invention,

FIG. 3 is a block diagram showing a configuration of a rising / falling detection unit of the embodiment,

FIG. 4 is a time chart (No. 1) for explaining the operation of the embodiment,

FIG. 5 is a time chart (No. 2) for explaining the operation of the embodiment.

[Explanation of symbols]

110 is a clock shift unit, 120 is an m + 1 frequency divider, 200
Is a 2n frequency dividing circuit, 300 is a rising / falling detecting section, and 600 is a coincidence detecting section.

Claims (1)

[Claims] 1. A signal having a parity block mB1P encoded by a parity bit is input, and 2n
(N: positive integer) Divide and output 2n divider (200)
And a rising / falling detection unit (300) which inputs the output of the 2n frequency dividing circuit (200) and detects the rising or falling part of the input pulse and outputs a detection pulse, and the 2n The clock extracted from the input signal to the frequency circuit (200) is input, and the clock shift unit (110) that shifts and outputs a fixed phase under a predetermined condition and the output of the clock shift unit (110) are input. Then, by inputting the m + 1 frequency dividing circuit (120) which outputs by dividing by m + 1, the detection pulse of the output of the rising / falling detecting section (300) and the output of the m + 1 frequency dividing circuit (120), A parity block characterized by having a match detection unit (600) for detecting a match or a mismatch between the two and outputting a detection signal to the clock shift unit (110), and synchronizing the parity block. Synchronous method.