JPH05166830A - Vertical bipolar transistor having SOI structure and method of manufacturing the same - Google Patents
Vertical bipolar transistor having SOI structure and method of manufacturing the sameInfo
- Publication number
- JPH05166830A JPH05166830A JP3354644A JP35464491A JPH05166830A JP H05166830 A JPH05166830 A JP H05166830A JP 3354644 A JP3354644 A JP 3354644A JP 35464491 A JP35464491 A JP 35464491A JP H05166830 A JPH05166830 A JP H05166830A
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- Prior art keywords
- region
- base
- electrode
- insulating film
- base region
- Prior art date
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Abstract
(57)【要約】
【目的】 縦型バイポーラトランジスタの占有面積の縮
小を図る。
【構成】 コレクタ領域となるＳＯＩ層の島状部分の反
研磨面側の部分にベース領域を形成し、該ベース領域の
側面と接するベース電極を島状部分間分離用絶縁膜の下
層を成すように形成し、上記ベース領域の底面の一部に
エミッタ領域を形成し、上記ＳＯＩ層の下側にエミッタ
電極を形成し、上記ＳＯＩ層の研磨面上にコレクタ電極
を形成する。
(57) [Abstract] [Purpose] To reduce the area occupied by vertical bipolar transistors. A base region is formed on a portion of the SOI layer serving as a collector region on the side opposite to the polishing surface of the island-shaped portion, and the base electrode in contact with the side surface of the base region is formed as a lower layer of an insulating film for separating the island-shaped portion. Then, an emitter region is formed on a part of the bottom surface of the base region, an emitter electrode is formed below the SOI layer, and a collector electrode is formed on the polished surface of the SOI layer.
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ＳＯＩ構造の縦型バイ
ポーラトランジスタとその製造方法、特に占有面積を小
さくできる新規なＳＯＩ構造の縦型バイポーラトランジ
スタとその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical bipolar transistor having an SOI structure and a method of manufacturing the same, and more particularly to a novel vertical bipolar transistor having an SOI structure and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】一般に、縦型バイポーラトランジスタは
コレクタ領域、ベース領域、エミッタ領域の各電極をす
べて素子の上部から取り出し、これ等の電極は略同じ層
（の配線層）として形成される場合が多かった。2. Description of the Related Art Generally, in a vertical bipolar transistor, electrodes of a collector region, a base region, and an emitter region are all taken out from the upper part of an element, and these electrodes may be formed as substantially the same layer (wiring layer thereof). There were many.
【０００３】[0003]
【発明が解決しようとする課題】従来の縦型バイポーラ
トランジスタはコレクタ領域、ベース領域、エミッタ領
域の電極が素子の上部に略同じ平面上に位置するように
形成されていたので、コレクタ領域、ベース領域、エミ
ッタ領域の電極取り出しのために無視できない広い面積
を割かなければならなかった。即ち、従来、電極取り出
しが行われるのは略同一平面上においてであった。その
ため、縦型バイポーラトランジスタの占有面積の縮小を
図ることが難しかった。In the conventional vertical bipolar transistor, the electrodes of the collector region, the base region and the emitter region are formed on the upper part of the device so as to be located on substantially the same plane. In order to take out the electrodes in the region and the emitter region, a large area that cannot be ignored had to be allocated. That is, conventionally, the electrodes are taken out on substantially the same plane. Therefore, it is difficult to reduce the occupied area of the vertical bipolar transistor.
【０００４】本発明はこのような問題点を解決すべく為
されたものであり、縦型バイポーラトランジスタの占有
面積の縮小を図ることを目的とする。The present invention has been made to solve such a problem, and an object thereof is to reduce the occupied area of a vertical bipolar transistor.
【０００５】[0005]
【課題を解決するための手段】本発明は、コレクタ領域
となるＳＯＩ層の島状部分の反研磨面側の部分にベース
領域を形成し、該ベース領域の側面と接するベース電極
を島状部分間分離用絶縁膜の下層を成すように形成し、
上記ベース領域の底面の一部にエミッタ領域を形成し、
上記ＳＯＩ層の下側にエミッタ電極を形成し、上記ＳＯ
Ｉ層の研磨面上にコレクタ電極を形成してなることを特
徴とする。According to the present invention, a base region is formed on a portion of an SOI layer, which is a collector region, on the side opposite to the polishing surface of an island portion, and a base electrode contacting the side surface of the base region is formed on the island portion. Is formed so as to form the lower layer of the insulating film for space separation,
Form an emitter region on a part of the bottom surface of the base region,
An emitter electrode is formed below the SOI layer, and the SO
A collector electrode is formed on the polished surface of the I layer.
【０００６】[0006]
【作用】従って、本発明によれば、コレクタ電極の取り
出しがコレクタ領域表面（ＳＯＩ層研磨面）にて、ベー
ス電極の取り出しがベース領域側面（島状部分側面）に
て、エミッタ電極の取り出しがエミッタ領域の底面にて
行われ、３つの電極の取り出し部分の高さが異なり、同
一平面を占有しない。従って、電極の取り出しのために
広い面積が占有されることを回避でき、延いては縦型バ
イポーラトランジスタの微細化を図ることができる。Therefore, according to the present invention, the collector electrode is taken out at the collector region surface (SOI layer polishing surface), the base electrode is taken out at the base region side surface (island-like side surface), and the emitter electrode is taken out. It is performed on the bottom surface of the emitter region, and the heights of the extraction portions of the three electrodes are different so that they do not occupy the same plane. Therefore, it is possible to avoid occupying a large area for taking out the electrodes, and it is possible to further miniaturize the vertical bipolar transistor.
【０００７】[0007]
【実施例】以下、本発明を図示実施例に従って詳細に説
明する。図１乃至図６は本発明縦型バイポーラトランジ
スタの製造方法の一つの実施例を工程順に示すものであ
り、この図１乃至図６に従って縦型バイポーラトランジ
スタの製造方法の説明をする。すると、自ずと製造され
た本発明縦型バイポーラトランジスタの一つの実施例の
構造も明らかにされる。The present invention will be described in detail below with reference to the illustrated embodiments. 1 to 6 show one embodiment of a method of manufacturing a vertical bipolar transistor of the present invention in the order of steps, and a method of manufacturing a vertical bipolar transistor will be described with reference to FIGS. 1 to 6. Then, the structure of one embodiment of the vertical bipolar transistor of the present invention manufactured naturally will be clarified.
【０００８】（１）先ず、形成するコレクタ領域２と同
じ導電型（この場合ｎ- 型）で同じ不純物濃度の第１の
半導体基板、即ちコレクタ領域２を成す第１の半導体基
板１を用意し、その表面部にそれと逆導電型（この場合
ｐ型）不純物をドープしてベース領域３を形成する。そ
の後、第１の半導体基板１の表面部を選択的にエッチン
グすることにより島状部分４を形成する。このエッチン
グ深さはコレクタ領域２・ベース領域間接合の深さより
も相当に深くする。図１は島状部分４形成後の状態を示
す。(1) First, a first semiconductor substrate having the same conductivity type (n − type in this case) and the same impurity concentration as the collector region 2 to be formed, that is, the first semiconductor substrate 1 forming the collector region 2 is prepared. The surface region of the base region 3 is doped with an impurity of the opposite conductivity type (p type in this case). Then, the island portion 4 is formed by selectively etching the surface portion of the first semiconductor substrate 1. This etching depth is made considerably deeper than the junction depth between the collector region 2 and the base region. FIG. 1 shows a state after the island-shaped portion 4 is formed.
【０００９】（２）次に、バイアスＥＣＲＣＶＤ法によ
りＳＯＩ層間を分離する分離用絶縁膜５を形成する。５
ａはこのバイアスＥＣＲＣＶＤで島状部分（ＳＯＩ層）
４上に形成された絶縁膜である。上記分離用絶縁膜５の
厚さは、上記エッチング深さよりも薄くし、また、表面
がコレクタ領域・ベース領域間接合よりも高いところに
位置するようにする。これは、次に形成するベース電極
（６）がベース領域３の側面に接するようにすると共
に、コレクタ領域２には接しないようにするためであ
る。(2) Next, the isolation insulating film 5 for isolating the SOI layers is formed by the bias ECRCVD method. 5
a is an island portion (SOI layer) in this bias ECRCVD
4 is an insulating film formed on the upper surface. The thickness of the isolation insulating film 5 is made thinner than the etching depth, and the surface is located higher than the junction between the collector region and the base region. This is because the base electrode (6) to be formed next is in contact with the side surface of the base region 3 and is not in contact with the collector region 2.
【００１０】その後、ｐ+ 型の多結晶シリコン層をＣＶ
Ｄにより形成し、しかる後、適宜パターニングし、これ
をもってベース電極６とする。このベース電極６はＳＯ
Ｉ層の島状部分４のベース領域３の側面に接する。即
ち、ベース電極の取り出しはベース領域３の側面に行う
ことができるのである。図２はｐ+ 型多結晶シリコン層
からなるベース電極６形成後の状態を示す。Thereafter, the p + -type polycrystalline silicon layer is CV
D, and then appropriately patterned to form the base electrode 6. This base electrode 6 is SO
It contacts the side surface of the base region 3 of the island-shaped portion 4 of the I layer. That is, the base electrode can be taken out to the side surface of the base region 3. FIG. 2 shows a state after the base electrode 6 made of the p + type polycrystalline silicon layer is formed.
【００１１】（３）次に、後でＳＯＩ層４を支持する支
持絶縁膜（ＳＯＩ構造のＩに該当する絶縁膜）となる絶
縁膜７をＣＶＤにより形成し、該絶縁膜７に対しての選
択的エッチングにより上記ベース領域３の表面を露出さ
せるエミッタ用コンタクトホール８を形成する。その
後、該コンタクトホール８内周面に絶縁物（例えばシリ
コン酸化物ＳｉＯ2 ）からなるサイドウォール９を形成
する。これは、次に形成されるエミッタ電極（１０）ベ
ース電極６との間に充分な余裕を設けるために形成され
るが、コンタクトホール８内周とベース領域３の側面と
の間に充分な余裕がある場合には必ずしも必要ではな
い。図３はサイドウォール９形成後の状態を示す。(3) Next, an insulating film 7 to be a supporting insulating film (an insulating film corresponding to I in the SOI structure) which later supports the SOI layer 4 is formed by CVD, and the insulating film 7 is formed. An emitter contact hole 8 exposing the surface of the base region 3 is formed by selective etching. After that, a sidewall 9 made of an insulating material (eg, silicon oxide SiO 2 ) is formed on the inner peripheral surface of the contact hole 8. This is formed to provide a sufficient margin between the emitter electrode (10) and the base electrode 6 to be formed next, but a sufficient margin is provided between the inner periphery of the contact hole 8 and the side surface of the base region 3. If there is, it is not necessary. FIG. 3 shows a state after forming the sidewall 9.
【００１２】（４）次に、サイドウォール９によってシ
ュリンクされたエミッタコンタクトホール８にｎ+ 型多
結晶シリコン層を埋め込み、これをもってエミッタ電極
１０とする。次に、高融点金属からなり、エミッタ電極
１０と接続される配線膜１１及びそれと同層の配線膜
（図示しない）を形成し、しかる後、表面に絶縁膜１２
を形成する。図４は該絶縁膜１２形成後の状態を示す。(4) Next, an n + type polycrystalline silicon layer is buried in the emitter contact hole 8 that is shrunk by the sidewall 9, and this is used as the emitter electrode 10. Next, a wiring film 11 made of a refractory metal and connected to the emitter electrode 10 and a wiring film (not shown) in the same layer as the wiring film 11 are formed, and thereafter, the insulating film 12 is formed on the surface.
To form. FIG. 4 shows a state after the insulating film 12 is formed.
【００１３】（５）次に、図５に示すように、第１の半
導体基板１を、その絶縁膜１２の表面にて第２の半導体
基板１３の表面に貼り合わせる。貼り合せ温度は例えば
８００℃以下である。 （６）その後、第１の半導体基板１を裏面側から前記分
離用絶縁膜５の表面が露出し島状部分４がＳＯＩ層とし
て他から名実共に分離した状態になるまで研磨する。(5) Next, as shown in FIG. 5, the first semiconductor substrate 1 is attached to the surface of the second semiconductor substrate 13 with the surface of the insulating film 12 thereof. The bonding temperature is, for example, 800 ° C. or lower. (6) After that, the first semiconductor substrate 1 is polished from the back surface side until the surface of the isolation insulating film 5 is exposed and the island-shaped portion 4 becomes a SOI layer in a state in which it is separated from others in both name and reality.
【００１４】その後、研磨面１４に露出するｎ- 型コレ
クタ領域２の表面部に電極取り出しのためにｎ+ 型不純
物をイオン打込みしてｎ+ 型領域とする。その後、アニ
ールする。すると、イオン打込みした不純物は活性化さ
れると共に、ｐ+ 型多結晶シリコンからなるベース電極
６中の不純物がベース領域６内に拡散してベース電極取
り出し用の高濃度領域１６が形成され、同時に、ｎ+ 型
多結晶シリコンからなるエミッタ電極１０中の不純物が
ベース領域３内に拡散してエミッタ電極１５が形成され
る。After that, an n + type impurity is ion-implanted into the surface portion of the n − type collector region 2 exposed on the polishing surface 14 to take out an electrode to form an n + type region. Then, it anneals. Then, the ion-implanted impurities are activated, and the impurities in the base electrode 6 made of p + -type polycrystalline silicon diffuse into the base region 6 to form a high-concentration region 16 for taking out the base electrode. Impurities in the emitter electrode 10 made of n + -type polycrystalline silicon diffuse into the base region 3 to form the emitter electrode 15.
【００１５】しかる後、分離用絶縁膜５に図示しない上
下配線間接続用スルーホールを形成し、その後選択タン
グステンでそのスルーホールを埋め込む等し、コレクタ
配線膜１７及びそれと同層の配線膜を形成する。すると
図６に示す構造の本発明縦型バイポーラトランジスタの
一つの実施例が出来上る。Thereafter, a through hole (not shown) for connecting the upper and lower wirings is formed in the insulating film for isolation 5, and then the through hole is filled with selective tungsten to form a collector wiring film 17 and a wiring film in the same layer. To do. Then, one embodiment of the vertical bipolar transistor of the present invention having the structure shown in FIG. 6 is completed.
【００１６】図６に示す本発明縦型バイポーラトランジ
スタの一つの実施例の構造を示すと下記のとおりであ
る。即ち、ＳＯＩ層の分離用絶縁膜５によって他から分
離された島状部分４の研磨面側の部分にコレクタ領域２
が形成され、上記ＳＯＩ層の島状部分４の下側の部分に
ベース領域３が形成され、該ベース領域３と接するベー
ス電極６が上記分離用絶縁膜５の下層を成すように形成
され、上記ベース領域３の底面の一部にエミッタ領域１
５が形成され、上記ＳＯＩ層の下側にエミッタ電極１０
が形成され、上記ＳＯＩ層の研磨面１４上に上記コレク
タ領域１５と接続されたコレクタ電極が形成されてな
る。The structure of one embodiment of the vertical bipolar transistor of the present invention shown in FIG. 6 is as follows. That is, the collector region 2 is formed on the polishing surface side of the island-shaped portion 4 separated from the others by the insulating insulating film 5 of the SOI layer.
Is formed, a base region 3 is formed below the island-shaped portion 4 of the SOI layer, and a base electrode 6 in contact with the base region 3 is formed so as to form a lower layer of the isolation insulating film 5. The emitter region 1 is formed on a part of the bottom surface of the base region 3.
5 is formed, and the emitter electrode 10 is formed below the SOI layer.
And a collector electrode connected to the collector region 15 is formed on the polished surface 14 of the SOI layer.
【００１７】つまり、コレクタ領域２となるＳＯＩ層の
島状部分４の反研磨面側の部分にベース領域３を形成
し、該ベース領域３の側面と接するベース電極６を島状
部分４間分離用絶縁膜５の下層を成すように形成し、上
記ベース領域３の底面の一部にエミッタ領域１５を形成
し、上記ＳＯＩ層の下側にエミッタ電極１０を形成し、
上記ＳＯＩ層の研磨面上にコレクタ電極１７を形成して
なる。従って、コレクタ電極１７の取り出しがコレクタ
領域２表面（ＳＯＩ層研磨面１４）にて、ベース電極６
の取り出しがベース領域３側面（島状部分側面）にて、
エミッタ電極１０の取り出しがエミッタ領域１０の底面
にて行われ、３つの電極１０、６、１７の取り出し部分
の高さが異なり、同一平面を占有しない。従って、電極
の取り出しのために広い面積が占有されることを回避で
き、延いては縦型バイポーラトランジスタの微細化を図
ることができる。That is, the base region 3 is formed on a portion of the SOI layer, which is the collector region 2, on the side opposite to the polishing surface of the island-shaped portion 4, and the base electrode 6 contacting the side surface of the base region 3 is separated between the island-shaped portions 4. Forming a lower layer of the insulating film 5 for forming, an emitter region 15 is formed on a part of the bottom surface of the base region 3, and an emitter electrode 10 is formed on the lower side of the SOI layer.
A collector electrode 17 is formed on the polished surface of the SOI layer. Therefore, the collector electrode 17 is taken out at the surface of the collector region 2 (SOI layer polishing surface 14) at the base electrode 6
Is taken out on the side surface of the base region 3 (side surface of the island portion),
The emitter electrode 10 is taken out at the bottom surface of the emitter region 10, and the heights of the taken-out portions of the three electrodes 10, 6, 17 are different and do not occupy the same plane. Therefore, it is possible to avoid occupying a large area for taking out the electrodes, and it is possible to miniaturize the vertical bipolar transistor.
【００１８】[0018]
【発明の効果】本発明は、ＳＯＩ層の分離用絶縁膜によ
って他から分離された島状部分の研磨面側の部分にコレ
クタ領域が形成され、上記ＳＯＩ層の島状部分の下側の
部分にベース領域が形成され、該ベース領域と接するベ
ース電極が上記分離用絶縁膜の下層を成すように形成さ
れ、上記ベース領域の底面の一部にエミッタ領域が形成
され、上記ＳＯＩ層の下側にエミッタ電極が形成され、
上記ＳＯＩ層の研磨面上に上記コレクタ領域と接続され
たコレクタ電極が形成されるようにしてなることを特徴
とするものである。従って、本発明によれば、コレクタ
電極の取り出しがコレクタ領域表面（ＳＯＩ層研磨面）
にて、ベース電極の取り出しがベース領域側面（島状部
分側面）にて、エミッタ電極の取り出しがエミッタ領域
の底面にて行われ、３つの電極の取り出し部分の高さが
異なり、同一平面を占有しない。従って、電極の取り出
しのために広い面積が占有されることを回避でき、延い
ては縦型バイポーラトランジスタの微細化を図ることが
できる。According to the present invention, the collector region is formed on the polishing surface side of the island-shaped portion separated from the other by the isolation insulating film of the SOI layer, and the portion below the island-shaped portion of the SOI layer is formed. A base region is formed on the base region, a base electrode in contact with the base region is formed as a lower layer of the isolation insulating film, an emitter region is formed on a part of the bottom surface of the base region, and a lower side of the SOI layer is formed. An emitter electrode is formed on
It is characterized in that a collector electrode connected to the collector region is formed on the polished surface of the SOI layer. Therefore, according to the present invention, the collector electrode is taken out from the collector region surface (SOI layer polished surface).
, The base electrode is taken out from the side surface of the base region (side surface of the island-shaped portion), and the emitter electrode is taken out from the bottom surface of the emitter region. do not do. Therefore, it is possible to avoid occupying a large area for taking out the electrodes, and it is possible to further miniaturize the vertical bipolar transistor.
【図１】本発明縦型バイポーラトランジスタの製造方法
の一つの実施例の第１の工程を示す断面図である。FIG. 1 is a sectional view showing a first step of one embodiment of a method for manufacturing a vertical bipolar transistor of the present invention.
【図２】上記実施例の第２の工程を示す断面図である。FIG. 2 is a sectional view showing a second step of the above embodiment.
【図３】上記実施例の第３の工程を示す断面図である。FIG. 3 is a sectional view showing a third step of the above embodiment.
【図４】上記実施例の第４の工程を示す断面図である。FIG. 4 is a sectional view showing a fourth step of the above embodiment.
【図５】上記実施例の第５の工程を示す断面図である。FIG. 5 is a cross-sectional view showing a fifth step of the above embodiment.
【図６】上記実施例の第６の工程を示し且つ本実施例に
より製造された本発明縦型バイポーラトランジスタの構
造を示す断面図である。FIG. 6 is a sectional view showing a sixth step of the above-mentioned embodiment and showing the structure of the vertical bipolar transistor of the present invention manufactured according to the present embodiment.
１ 第１の半導体基板 ２ コレクタ領域 ３ ベース領域 ４ ＳＯＩ層の島状部分 ５ 分離用絶縁膜 ６ ベース電極 ７ 支持絶縁膜 ８ エミッタコンタクトホール １０ エミッタ電極 １３ 第２の半導体基板 １４ 研磨面 １５ エミッタ領域 １７ コレクタ電極 1 First Semiconductor Substrate 2 Collector Region 3 Base Region 4 Island Part of SOI Layer 5 Separation Insulation Film 6 Base Electrode 7 Support Insulation Film 8 Emitter Contact Hole 10 Emitter Electrode 13 Second Semiconductor Substrate 14 Polished Surface 15 Emitter Region 17 Collector electrode
Claims (2)
分離された島状部分の研磨面側の部分にコレクタ領域が
形成され、 上記ＳＯＩ層の島状部分の下部にベース領域が形成さ
れ、 上記ベース領域と接するベース電極が上記分離用絶縁膜
の下層を成すように形成され、 上記ベース領域の底面の一部にエミッタ領域が形成さ
れ、 上記ＳＯＩ層の下側にエミッタ電極が形成され、 上記ＳＯＩ層の研磨面上に上記コレクタ領域と接続され
たコレクタ電極が形成されてなることを特徴とするＳＯ
Ｉ構造の縦型バイポーラトランジスタ1. A collector region is formed on a portion of the island-shaped portion separated from the other by an insulating film for isolation of the SOI layer on the polishing surface side, and a base region is formed below the island-shaped portion of the SOI layer. A base electrode in contact with the base region is formed so as to form a lower layer of the isolation insulating film, an emitter region is formed on a part of a bottom surface of the base region, and an emitter electrode is formed on a lower side of the SOI layer, An SO characterized in that a collector electrode connected to the collector region is formed on the polished surface of the SOI layer.
Vertical I-structured bipolar transistor
表面部にベース領域を形成し、 上記第１の半導体基板の表面部を上記コレクタ領域・ベ
ース領域間接合よりも深く選択エッチングすることによ
りＳＯＩ層となる島状部分を形成し、 上記島状部分を他から分離する分離絶縁膜を形成し、 上記分離用絶縁膜上に、島状部分のベース領域の側面と
接するベース電極を形成し、 上記第１の半導体基板の表面上にＳＯＩ層を支持する支
持絶縁膜を形成し、 上記支持絶縁膜に上記ベース領域を露出させるコンタク
トホールを形成し、 上記コンタクトホール内にエミッタ形成用不純物を含ん
だ半導体からなるエミッタ電極を形成し、 上記ベース電極中の不純物を上記ベース領域中に拡散さ
せることによりエミッタ領域を形成し、 上記第１の半導体基板の表面に上記ベース電極を介して
上記ベース領域に接続される配線膜を形成し、 上記第１の半導体基板の表面に第２の半導体基板を貼り
合せ、 上記第１の半導体基板の裏面を上記分離用絶縁膜が露出
するまで研磨し、 上記島状部分の研磨面に露出したコレクタ領域と接続さ
れたコレクタ電極を形成することを特徴とする縦型バイ
ポーラトランジスタの製造方法2. A base region is formed on a surface portion of a first semiconductor substrate forming a collector region, and the surface portion of the first semiconductor substrate is selectively etched deeper than the junction between the collector region and the base region. An island-shaped portion to be an SOI layer is formed, an isolation insulating film is formed to separate the island-shaped portion from others, and a base electrode is formed on the isolation insulating film to be in contact with a side surface of a base region of the island-shaped portion. A supporting insulating film supporting the SOI layer is formed on the surface of the first semiconductor substrate, a contact hole exposing the base region is formed in the supporting insulating film, and an impurity for forming an emitter is formed in the contact hole. Forming an emitter electrode made of a semiconductor containing the impurity, and forming an emitter region by diffusing impurities in the base electrode into the base region; A wiring film connected to the base region via the base electrode is formed on the front surface of the plate, a second semiconductor substrate is attached to the front surface of the first semiconductor substrate, and the back surface of the first semiconductor substrate is attached. Polishing until the isolation insulating film is exposed to form a collector electrode connected to the collector region exposed on the polished surface of the island-shaped portion, and a method for manufacturing a vertical bipolar transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP35464491A JP3146582B2 (en) | 1991-12-18 | 1991-12-18 | Vertical bipolar transistor having SOI structure and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP35464491A JP3146582B2 (en) | 1991-12-18 | 1991-12-18 | Vertical bipolar transistor having SOI structure and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05166830A true JPH05166830A (en) | 1993-07-02 |
| JP3146582B2 JP3146582B2 (en) | 2001-03-19 |
Family
ID=18438945
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP35464491A Expired - Fee Related JP3146582B2 (en) | 1991-12-18 | 1991-12-18 | Vertical bipolar transistor having SOI structure and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3146582B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102004061327A1 (en) * | 2004-12-11 | 2006-06-14 | IHP GmbH - Innovations for High Performance Microelectronics/Institut für innovative Mikroelektronik | Vertical bipolar transistor |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6518342B1 (en) | 1998-10-29 | 2003-02-11 | Nippon Shokubai Co., Ltd. | Emulsion for pressure-sensitive adhesive |
-
1991
- 1991-12-18 JP JP35464491A patent/JP3146582B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102004061327A1 (en) * | 2004-12-11 | 2006-06-14 | IHP GmbH - Innovations for High Performance Microelectronics/Institut für innovative Mikroelektronik | Vertical bipolar transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3146582B2 (en) | 2001-03-19 |
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