JPH0715940B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH0715940B2 JPH0715940B2 JP61233626A JP23362686A JPH0715940B2 JP H0715940 B2 JPH0715940 B2 JP H0715940B2 JP 61233626 A JP61233626 A JP 61233626A JP 23362686 A JP23362686 A JP 23362686A JP H0715940 B2 JPH0715940 B2 JP H0715940B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- type
- semiconductor device
- groove
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 26
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 238000000034 method Methods 0.000 title description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 9
- 238000009792 diffusion process Methods 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 229910052814 silicon oxide Inorganic materials 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 238000005468 ion implantation Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
- Element Separation (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に係わり、特に素子間の
絶縁分離として絶縁物を含む溝を有する半導体装置の製
造方法に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a groove containing an insulator as an insulation separation between elements.
従来、素子間の絶縁分離は選択酸化法によって形成され
た厚い酸化膜によって行なわれていたが、この方法で
は、選択酸化の際の酸化膜の素子領域への喰い込みによ
って絶縁分離領域が広くなり半導体装置の高集積化の妨
げになっていた。このためシリコン基板に溝を形成し、
その溝内に絶縁材料や多結晶シリコンを埋設する方法
が、近年用いられるようになった。特にバイポーラ型半
導体装置では、厚いエピタキシャル層とサブコレクタ層
とを分離しなければならないので、溝分離法の採用が急
務である。Conventionally, isolation between elements has been performed by using a thick oxide film formed by a selective oxidation method.However, in this method, the isolation layer is widened by the oxide film being embedded in the element region during selective oxidation. This has been a hindrance to high integration of semiconductor devices. For this reason, a groove is formed in the silicon substrate,
In recent years, a method of burying an insulating material or polycrystalline silicon in the groove has been used. Particularly in a bipolar semiconductor device, the thick epitaxial layer and the subcollector layer have to be separated, so that there is an urgent need to adopt the groove separation method.
しかしながらバイポーラ型素子を分離する場合は、溝の
底部には高濃度のサブコレクタ層が近接する為、溝の底
部には、比較的高濃度のチャンネル・ストッパー層を形
成する必要があった。以下図面を用いて説明する。However, in the case of separating the bipolar type element, since a high concentration sub-collector layer is close to the bottom of the groove, it is necessary to form a relatively high concentration channel stopper layer at the bottom of the groove. This will be described below with reference to the drawings.
第４図（ａ）（ｂ）は、従来の溝分離構造を用いた半導
体装置の製造方法を説明するための工程順に示した半導
体チップ断面図である。FIGS. 4A and 4B are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a method for manufacturing a semiconductor device using a conventional groove separation structure.
まず、第４図（ａ）に示す様にｐ型シリコン基板１上に
選択的にｎ型サブコレクタ層３を形成し、更にｎ型エピ
タキシャル層４を形成する。次に、全面にシリコン酸化
膜10,シリコン窒化膜30を形成し、フォトレジスト12を
マスクにシリコン酸化膜10,シリコン窒化膜30及びｐ型
シリコン基板１のエッチングを行い溝15を設け、イオン
注入法によってチャンネル・ストッパー層7Aを形成す
る。First, as shown in FIG. 4A, an n-type subcollector layer 3 is selectively formed on a p-type silicon substrate 1, and an n-type epitaxial layer 4 is further formed. Next, a silicon oxide film 10 and a silicon nitride film 30 are formed on the entire surface, the silicon oxide film 10, the silicon nitride film 30 and the p-type silicon substrate 1 are etched using the photoresist 12 as a mask to form a groove 15 and ion implantation is performed. The channel stopper layer 7A is formed by the method.
次に第４図（ｂ）に示すように、溝15の表面にシリコン
酸化膜８を形成したのち、多結晶シリコン９を埋設し更
に多結晶シリコン表面に酸化膜10を形成したのち、素子
形成領域にベース層5,エミッタ層6,Al電極11を形成しバ
イポーラ型半導体装置を完成させていた。Next, as shown in FIG. 4 (b), after forming a silicon oxide film 8 on the surface of the groove 15, burying polycrystalline silicon 9 and further forming an oxide film 10 on the surface of the polycrystalline silicon, element formation is performed. The base layer 5, the emitter layer 6, and the Al electrode 11 were formed in the region to complete the bipolar semiconductor device.
しかしながら、上述した従来の半導体装置の構造では、
イオン注入で形成したチャンネル・ストッパー層7Aは、
溝15の底部だけでなく、溝15の側壁下部にも形成され、
高濃度のサブコレクタ層３とチャンネル・ストッパー層
7A間の接合容量が増加し、素子の特性が劣化したり、イ
オン注入のダメージに起因した結晶欠陥が発生し半導体
装置の製造歩留を低下させるという欠点がある。However, in the structure of the conventional semiconductor device described above,
The channel stopper layer 7A formed by ion implantation is
Not only on the bottom of the groove 15, but also on the lower part of the side wall of the groove 15,
High concentration sub-collector layer 3 and channel stopper layer
There are drawbacks that the junction capacitance between 7A increases, the characteristics of the element are deteriorated, and crystal defects due to damage of ion implantation occur to reduce the manufacturing yield of semiconductor devices.
本発明の目的は、特性の劣化が少く、製造歩留りの向上
した半導体装置の製造方法を提供することにある。An object of the present invention is to provide a method for manufacturing a semiconductor device in which the characteristics are less deteriorated and the manufacturing yield is improved.
本発明の半導体装置の製造方法は、一導電型半導体基板
の少くとも一部に熱拡散により一導電型高濃度層を形成
したのち全面に一導電型エピタキシャル層を形成する工
程と、前記エピタキシャル層内に逆導電型高濃度層を形
成したのち全面に逆導電型エピタキシャル層を形成する
工程と、前記逆導電型エピタキシャル層の表面から前記
一導電型高濃度層に達する溝を形成したのち該溝の表面
に絶縁膜を形成する工程と、前記溝中に多結晶シリコン
又は絶縁物を埋込む工程とを含むことを特徴とするもの
である。A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a high concentration layer of one conductivity type on at least a part of a semiconductor substrate of one conductivity type by thermal diffusion and then forming an epitaxial layer of the one conductivity type on the entire surface, Forming a reverse-conductivity-type high-concentration layer in the inside and then forming a reverse-conductivity-type epitaxial layer on the entire surface; and forming a groove from the surface of the reverse-conductivity-type epitaxial layer to the one-conductivity-type high-concentration layer, And a step of burying polycrystalline silicon or an insulating material in the groove.
次に、本発明の実施例について図面を参照して説明す
る。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は第３図に示す本発明の第１の実施例の製造方法
により製造された半導体装置の断面図である。FIG. 1 is a sectional view of a semiconductor device manufactured by the manufacturing method of the first embodiment of the present invention shown in FIG.
第１図において、ｐ型シリコン基板１の一部には、チャ
ンネル・ストッパーを形成するｐ型高濃度層７が形成さ
れている。そしてその上面にはｐ型エピタキシャル層２
が形成されており、このｐ型エピタキシャル層２内には
ｎ型サブコレクタ層３が形成されている。そしてこのｐ
型エピタキシャル層２上にはｎ型エピタキシャル層４が
形成されている。In FIG. 1, a p-type high-concentration layer 7 forming a channel stopper is formed on a part of the p-type silicon substrate 1. The p-type epitaxial layer 2 is formed on the upper surface.
And the n-type subcollector layer 3 is formed in the p-type epitaxial layer 2. And this p
An n-type epitaxial layer 4 is formed on the type epitaxial layer 2.
更にｎ型エピタキシャル層４表面からｐ型高濃度層７に
達し表面にシリコン酸化膜８が形成された素子分離用の
溝15が形成されており、この溝15中には多結晶シリコン
９が埋込まれている。尚、素子形成領域のｎ型エピタキ
シャル層４内にはベース層5,エミッタ層６及びAl電極11
からなるバイポーラトランジスタが形成されている。Further, a trench 15 for element isolation is formed from the surface of the n-type epitaxial layer 4 to the p-type high concentration layer 7 and a silicon oxide film 8 is formed on the surface thereof. The trench 15 is filled with polycrystalline silicon 9. It is embedded. In addition, in the n-type epitaxial layer 4 in the element formation region, the base layer 5, the emitter layer 6 and the Al electrode 11 are formed.
Is formed of a bipolar transistor.
このように構成された第１の実施例による半導体装置に
おいては、溝15の底部はｐ型高濃度層７内に含まれるた
め、溝底部の界面におけるチャンネルの形成を防ぐこと
ができる。又ｐ型高濃度層７とｎ型サブコレクタ層３間
には低濃度のｐ型エピタキシャル層12が介在する為に、
イオン注入によって形成された従来構造でのチャンネル
・ストッパー層であるｐ型高濃度層７とｎ型サブコレク
タ層３との容量増大もなく、更にｐ型高濃度層７は、熱
拡散で形成される為に、結晶欠陥の発生等の問題も生じ
ない。In the semiconductor device according to the first embodiment having such a configuration, since the bottom of the groove 15 is included in the p-type high concentration layer 7, formation of a channel at the interface of the groove bottom can be prevented. Further, since the low-concentration p-type epitaxial layer 12 is interposed between the p-type high-concentration layer 7 and the n-type subcollector layer 3,
The p-type high-concentration layer 7 and the n-type sub-collector layer 3 which are channel stopper layers in the conventional structure formed by ion implantation do not increase in capacity, and the p-type high-concentration layer 7 is formed by thermal diffusion. Therefore, problems such as generation of crystal defects do not occur.
次に、第１図に示した半導体装置を製造する第１の実施
例の製造方法を第３図（ａ）〜（ｄ）を用いて説明す
る。Next, a manufacturing method of the first embodiment for manufacturing the semiconductor device shown in FIG. 1 will be described with reference to FIGS. 3 (a) to 3 (d).
まず第３図（ａ）に示すようにｐ型シリコン基板１上に
選択的に形成したシリコン酸化膜20をマスクにｐ型高濃
度層７を形成する。First, as shown in FIG. 3A, the p-type high concentration layer 7 is formed using the silicon oxide film 20 selectively formed on the p-type silicon substrate 1 as a mask.
次に第３図（ｂ）に示すように全面に、ｐ型エピタキシ
ャル層２を成長させた後、ｎ型不純物を導入し高濃度の
ｎ型サブコレクタ層３を選択的に形成する。Next, as shown in FIG. 3B, after growing the p-type epitaxial layer 2 on the entire surface, an n-type impurity is introduced to selectively form the high-concentration n-type subcollector layer 3.
次に第３図（ｃ）に示すように、全面にｎ型エピタキシ
ャル層４を成長させる。Next, as shown in FIG. 3C, the n-type epitaxial layer 4 is grown on the entire surface.
次に第３図（ｄ）に示すように、選択的にｎ型エピタキ
シャル層4,p型エピタキシャル層２をエッチングし、ｐ
型高濃度層７内に迄達する溝15を形成する。その後溝15
の壁を酸化してシリコン酸化膜８を形成したのち、多結
晶シリコンを溝15内に埋設後多結晶シリコン表面を酸化
する。多結晶シリコンの代りにSiO2等の絶縁物を埋設し
てもよい。Next, as shown in FIG. 3 (d), the n-type epitaxial layer 4 and the p-type epitaxial layer 2 are selectively etched to form p
A groove 15 is formed which reaches the high-concentration mold layer 7. Then groove 15
After oxidizing the walls of the silicon oxide film to form the silicon oxide film 8, the polycrystalline silicon is buried in the groove 15 and the surface of the polycrystalline silicon is oxidized. An insulator such as SiO 2 may be embedded instead of polycrystalline silicon.
以下通常の方法でベース層5,エミッタ層6,Al配線を形成
する事によって第１図に示した第１の実施例による半導
体装置が完成する。Thereafter, the base layer 5, the emitter layer 6, and the Al wiring are formed by the usual method, whereby the semiconductor device according to the first embodiment shown in FIG. 1 is completed.
第２図は第３図に示した第１の実施例の製造方法のうち
第３図（ａ）の工程を変更した第２の実施例による半導
体装置の断面図である。すなわち、第３図（ａ）におい
てｐ型シリコン基板１の全面に熱拡散によりｐ型高濃度
層７を形成したものである。この場合第１の実施例に比
べシリコン酸化膜20の形成とそのパターニング工程が不
要となる利点がある。FIG. 2 is a sectional view of a semiconductor device according to a second embodiment in which the step of FIG. 3 (a) is changed in the manufacturing method of the first embodiment shown in FIG. That is, in FIG. 3A, the p-type high concentration layer 7 is formed on the entire surface of the p-type silicon substrate 1 by thermal diffusion. In this case, there is an advantage that the step of forming the silicon oxide film 20 and the patterning step thereof are unnecessary as compared with the first embodiment.
以上説明したように本発明は、素子分離用の溝の底部に
チャンネル・ストッパーとなる一導電型高濃度層が形成
され、又、この高濃度層とサブコレクタ層である逆導電
型高濃度層との間には一導電型のエピタキシャル層があ
るので、従来構造の半導体装置におけるチャンネル・ス
トッパー層とサブコレクタ層との接触による容量増加も
なく、チャンネル・ストッパー形成の際の欠陥発生もな
い。従って、半導体装置の特性劣化が少なく、製造歩留
りが向上するという効果がある。As described above, according to the present invention, the one-conductivity-type high-concentration layer serving as a channel stopper is formed at the bottom of the isolation trench, and the high-concentration layer and the reverse-conductivity-type high-concentration layer that is the subcollector layer are formed. Since there is an epitaxial layer of one conductivity type between and, there is no increase in capacitance due to the contact between the channel stopper layer and the subcollector layer in the semiconductor device having the conventional structure, and no defect occurs when forming the channel stopper. Therefore, the characteristics of the semiconductor device are less deteriorated and the manufacturing yield is improved.
第１図及び第２図は本発明の第１及び第２の実施例の製
造方法により製造された半導体装置の断面図、第３図
（ａ）〜（ｄ）は本発明の第１の実施例の製造方法を説
明する為の工程順に示した半導体チップの断面図、第４
図（ａ）（ｂ）は従来の半導体装置の製造方法を説明す
るための半導体チップの断面図である。 １……ｐ型シリコン基板、２……ｐ型エピタキシャル
層、３……ｎ型サブコレクタ層、４……ｎ型エピタキシ
ャル層、５……ベース層、６……エミッタ層、７……ｐ
型高濃度層、7A……チャンネル・ストッパー層、8,10,2
0,20A……シリコン酸化膜、９……多結晶シリコン、11
……Al電極、12……フォトレジスト、30……シリコン窒
化膜。1 and 2 are sectional views of a semiconductor device manufactured by the manufacturing method of the first and second embodiments of the present invention, and FIGS. 3 (a) to 3 (d) are the first embodiment of the present invention. FIG. 4 is a cross-sectional view of the semiconductor chip showing the order of steps for explaining an example manufacturing method.
1A and 1B are cross-sectional views of a semiconductor chip for explaining a conventional method of manufacturing a semiconductor device. 1 ... p-type silicon substrate, 2 ... p-type epitaxial layer, 3 ... n-type subcollector layer, 4 ... n-type epitaxial layer, 5 ... base layer, 6 ... emitter layer, 7 ... p
Type high concentration layer, 7A ... Channel stopper layer, 8,10,2
0,20A: Silicon oxide film, 9: Polycrystalline silicon, 11
…… Al electrode, 12 …… photoresist, 30 …… silicon nitride film.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 29/72 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI technical display location H01L 29/72
Claims (1)
散により一導電型高濃度層を形成したのち全面に一導電
型エピタキシャル層を形成する工程と、前記エピタキシ
ャル層内に逆導電型高濃度層を形成したのち全面に逆導
電型エピタキシャル層を形成する工程と、前記逆導電型
エピタキシャル層の表面から前記一導電型高濃度層に達
する溝を形成したのち該溝の表面に絶縁膜を形成する工
程と、前記溝中に多結晶シリコン又は絶縁物を埋込む工
程とを含むことを特徴とする半導体装置の製造方法。1. A step of forming a high concentration layer of one conductivity type by thermal diffusion on at least a part of a semiconductor substrate of one conductivity type and then forming an epitaxial layer of one conductivity type on the entire surface, and a reverse conductivity type in the epitaxial layer. Forming a high-concentration layer and then forming a reverse-conductivity type epitaxial layer on the entire surface; and forming a groove from the surface of the reverse-conductivity-type epitaxial layer to the high-concentration layer of one conductivity type, and then forming an insulating film on the surface of the groove. And a step of burying polycrystalline silicon or an insulator in the groove, the method of manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61233626A JPH0715940B2 (en) | 1986-09-30 | 1986-09-30 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61233626A JPH0715940B2 (en) | 1986-09-30 | 1986-09-30 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6387740A JPS6387740A (en) | 1988-04-19 |
| JPH0715940B2 true JPH0715940B2 (en) | 1995-02-22 |
Family
ID=16957993
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61233626A Expired - Fee Related JPH0715940B2 (en) | 1986-09-30 | 1986-09-30 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0715940B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5213441B2 (en) * | 2004-07-28 | 2013-06-19 | クォンタム セミコンダクター リミテッド ライアビリティ カンパニー | Layout for integrated integration of CMOS and stacked photoactive layers |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59124153A (en) * | 1982-12-29 | 1984-07-18 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit device |
| JPS60154626A (en) * | 1984-01-25 | 1985-08-14 | Hitachi Ltd | Deposition in groove and equipment thereof |
-
1986
- 1986-09-30 JP JP61233626A patent/JPH0715940B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6387740A (en) | 1988-04-19 |
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