JPH05175230A - Method of manufacturing thin film transistor - Google Patents

Abstract

(57) [Summary] [Structure] The thin film transistor of the present invention makes good use of the magnitude relation between the gate electrode and the patterning film for the gate electrode patterning formed by isotropic etching.
A thin film transistor having a DD structure is formed. According to the present invention, the length of the low-concentration doped region is determined by the size relationship between the patterning film for the gate electrode patterning and the gate electrode or the difference in the diffusion coefficient of the implanted ions. Excellent and can secure a uniform structure over a large area.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor for turning on / off each pixel of an active matrix type liquid crystal display device, or a thin film transistor in which an active layer used in a peripheral driving circuit is a polycrystalline silicon thin film.

[0002]

2. Description of the Related Art In recent years, a liquid crystal display device using a thin film transistor whose active layer is made of a polycrystalline silicon thin film has been developed for the purpose of realizing a high-definition and high-performance active matrix liquid crystal display device.

By using high-mobility polycrystalline silicon instead of amorphous silicon as the active layer of the thin film transistor, the thin film transistor can be made smaller, which allows the liquid crystal display device to have higher definition.
Further, by using polycrystalline silicon as the active layer of the thin film transistor, the peripheral drive circuit can be formed at the same time, so that the peripheral drive circuit can be provided integrally with the liquid crystal cell and the cost of the liquid crystal display device can be reduced. be able to.

As a thin film transistor used for switching each pixel in an active matrix type liquid crystal display device, there is no flicker or crosstalk in the display, and it is off because of the demand for a large contrast ratio.
It is required that the current is small and the on / off ratio of the current is 100: 1 or more. The structure of the polycrystalline silicon thin film transistor will be briefly described below.

This polycrystalline silicon thin film transistor is
A polycrystalline silicon thin film is provided in an island shape on an insulating substrate such as quartz glass, and a gate electrode formed by doping polycrystalline silicon with impurities through a gate insulating film is provided thereon. In the polycrystalline silicon film adjacent to this gate electrode, phosphorus ion (P ⁺ ) Or boron ion (B
⁺ ) Impurities such as ions are doped to form a source region and a drain region. The source region and the drain region are connected to each electrode by a metal such as aluminum (Al), and the active layer is made of a polycrystalline silicon film. The thin film transistor is configured.

However, in the polycrystalline silicon thin film transistor having such a structure, the gate voltage is 0 V (Vg = 0.
V) has a large leak current and a reverse bias condition,
For example, when a negative gate voltage is applied to an n-channel transistor, an electric field due to the applied gate voltage and drain voltage concentrates on the drain junction, carriers move through crystal defects near the drain junction, and the gate voltage is increased. However, there is a problem that a large leak current flows depending on the drain voltage.

In order to solve such a problem, for example, Japanese Patent Laid-Open No. 63-204769 discloses an LDD (lightly light) which is often used in a single crystal silicon thin film transistor.
It is disclosed that the drain electric field is relaxed and the leak current is suppressed by adopting a doped drain) structure for a polycrystalline silicon thin film transistor.

[0008]

A polycrystalline silicon thin film transistor having an LDD structure is usually manufactured as shown in FIG. 5, for example.

That is, as shown in FIG. 5 (a), a polycrystalline silicon layer (20) is formed on a quartz substrate (11) and etched into islands, and then, as shown in FIG. 5 (b). Then, an insulating film (31) is formed on the polycrystalline silicon film (21).

Thereafter, as shown in FIG. 5C, a gate electrode 45 having a predetermined shape is formed on the insulating film 31 by anisotropic dry etching so that the gate electrode 45 has a predetermined shape. As shown in (d), low-concentration ion implantation is performed using the gate electrode (45) as a mask, and the low-concentration doped regions (25a), (2
5b) is formed.

Thereafter, as shown in FIG. 3E, an oxide film (101) is formed on the gate electrode (45) by a CVD method, and an oxide film side wall (103) is formed on the side wall of the gate electrode (45). The oxide film (101) is etched by anisotropic dry etching so that it remains. Then, as shown in FIG.
5) and the side wall of the oxide film (103) as a mask to perform high-concentration ion implantation, and
Highly doped regions (23a) and (23b) adjacent to (25b) are formed to form an LDD structure.

Further, the above-cited patent discloses a method of implanting low concentration ions with the gate electrode (45) as a mask, and then forming a resist mask larger than the gate electrode (45) and implanting high concentration ions.

However, the LDD structure has a lightly doped region.
Since the off current and the on current greatly depend on the dose amount of (25a) and (25b) and the width of the region, accuracy in production becomes very important.

For example, the method using the oxide film side wall (103) has a problem that a liquid crystal display device having a large area has a process difficulty and a controllable side wall (103) width is narrow. Even when the resist is used as a mask, the accuracy of the resist pattern is limited, and it is difficult to manufacture the resist pattern over a large area with high accuracy. In addition to this, in the case of a thin film transistor for a pixel of a liquid crystal display device, since an alternating voltage is required to be applied to the liquid crystal to prevent deterioration, the source and drain of the thin film transistor are inverted, for example, every frame. The unevenness of the impurity regions affects display characteristics such as flicker.

The present invention has been made in view of the above problems, and an object thereof is to provide a method of manufacturing a thin film transistor in which the length of the lightly doped region on both sides of the gate can be easily controlled by a simple manufacturing method. Is.

[0016]

A method of manufacturing a thin film transistor according to the present invention comprises a step of forming a polycrystalline silicon film on a substrate and an insulating film on the polycrystalline silicon film, and a step of forming a gate electrode film on the insulating film. A step of providing a patterning film for patterning the gate electrode on the gate electrode film, and overetching the gate electrode film by an isotropic etching method so as to be smaller than the pattern of the patterning film to form a gate electrode And a step of implanting impurities into the island-shaped polycrystalline silicon to form a source region and a drain region, and a process of forming and processing a metal wiring film connected to the source region and the drain region. It is what

In the present invention, particularly, the step of implanting impurities to form the source region and the drain region includes the step of implanting impurities using the patterning film as a mask and the step of removing the patterning film and implanting impurities. The present invention is characterized by comprising the steps of: and further, injecting two kinds of impurities having different diffusion coefficients.

[0018]

In the past, the anisotropic dry etching method or the like was used for the etching of the gate electrode film because it is necessary to secure an accurate gate length, and the etching is generally performed so that the end face becomes approximately 90 degrees.

However, according to the present inventor, even in the isotropic etching method, the over-etching amount becomes large and the etching end surface approaches 90 degrees, so that an accurate gate length can be secured as in the anisotropic dry etching method. Was confirmed. The present invention has been made based on these facts.

The present invention takes advantage of the characteristics of the isotropic etching method, in particular, the fact that the gate electrode is smaller than the pattern of the patterning film of the gate electrode film. is there. Then, due to the difference between the pattern of the patterning film and the gate electrode, it becomes possible to easily manufacture the thin film transistor having the LDD structure. That is, the length of the low-concentration doped region is determined by the difference between the patterning film and the gate electrode, or the length of the low-concentration doped region is determined by the difference in the diffusion coefficient of the implanted impurities. No positional accuracy is required. Therefore, it is possible to manufacture a thin film transistor having a lightly doped region with a uniform length.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the method of manufacturing a thin film transistor according to the present invention will be described below with reference to the drawings. Figure 1
FIG. 1 is a schematic sectional view of a thin film transistor (1) according to an embodiment of the present invention.

The thin film transistor (1) manufactured according to the present embodiment has an island-shaped polycrystalline silicon film (2) formed on a quartz substrate (11).
1) is installed, and the gate electrode (45) is installed via the insulating film (31).

In the portion of the polycrystalline silicon film (21) adjacent to the gate electrode (45), a source region (28a) and a drain region (28b) formed by doping impurities are formed. Then, these source region (28a) and drain region (28b) are
Lightly doped regions (25a), (25a) close to the gate electrode (45)
b) and heavily doped regions (23a), (23b) in contact with the lightly doped regions (25a), (25b). The source region (28a) and the drain region (28b) are made of aluminum (A
The metal wirings (71a) and (71b) made of (1) are wired outside. Next, the thin film transistor in this embodiment
The manufacturing method (1) will be described with reference to FIG.

First, a quartz substrate (11) is used as a substrate, and 100 (%) silane gas is used on the substrate (11) by a low pressure CVD method at a pressure of 1 (torr) and a film forming temperature of 550 ° C. to form amorphous silicon. An (a-Si) film was deposited to a thickness of 2000 angstroms and solid phase growth was performed at 600 ° C. to obtain a polycrystalline silicon film (21) having a large grain size of about 2 μm. The crystal grain size of the polycrystalline silicon film (21) is 1 to 5
It is possible to obtain preferable characteristics of about micron. There are various methods for obtaining the polycrystalline silicon film (21), but the method of solid phase growing an amorphous silicon (a-Si) film is particularly preferable. Among them, a material obtained by solid phase growth of an amorphous silicon (a-Si) film formed by a low pressure CVD method is particularly preferable, and a polycrystalline silicon film (21) having a large particle diameter can be obtained. Then, as shown in FIG. 1A, the polycrystalline silicon film (21) is etched into an island shape and thermally oxidized to form a silicon oxide film (S) having a thickness of 500 Å.
A gate insulating film (31) made of an iO ₂ ) film was formed. Next, as shown in FIG. 2B, a gate electrode film (41) having a film thickness of 4000 angstrom is formed.

Then, as shown in (c) of the figure, as a patterning film for patterning the gate electrode film (41), for example, a resist applied on the gate electrode film (41) is patterned. Using the resist pattern (51) of a predetermined shape, the gate electrode film (41) under the end of the resist pattern (51) is isotropically etched, and the gate electrode 45)
To form. Thus, a gate electrode (45) smaller than the resist pattern (51) was obtained. Incidentally, the gate electrode (45)
The size of can be easily controlled by the etching time or the mixed gas ratio.

Next, as shown in (d) of the figure, using the resist pattern (51) as a mask, As ⁺ 5x ion
Ions were implanted at a concentration of 10 ¹⁵ (atoms / 2) to form heavily doped regions (23a) and (23b).

Further, as shown in (e) in the figure, the resist pattern (51) is removed, and As ⁺ is self-aligned using the gate electrode (45) as a mask. 1 × 10 ¹² (atoms /
Ion implantation is performed at the concentration of 2) and the lightly doped region (25
Formed a) and (25b).

As film forming conditions, film forming temperature 830
High temperature oxidation (HTO:
High Temperature Oxide) film is formed to form interlayer insulation layer (61)
After forming the, as shown in (f) in the figure, the interlayer insulating layer (61)
Contact holes (63a) and (63b) are formed in the. The activation of the implanted ions is also performed in the manufacturing process of the interlayer insulating layer (61), and in the figure, high-concentration doped regions (23a), (23b), low-concentration doped regions (25a), (25b ) Is obtained.

Then, as shown in (g) of FIG. 2, the doped regions (28a), (2) are formed through the contact holes (63a), (63b).
Metal wirings (71a) and (71b) connected to 8b) were formed to form a thin film transistor.

FIG. 3 shows the characteristics of the n-channel thin film transistor when the drain current (ID) is plotted on the vertical axis and the gate voltage (VG) is plotted on the horizontal axis, and the source-drain voltage VSD is 10 (V). The curve (a) in the figure shows the characteristic of the n-channel thin film transistor according to this embodiment, and the curve (b) in the figure shows the characteristic of the conventional n-channel thin film transistor having no LDD structure. From this figure, it is understood that according to the n-channel thin film transistor of this embodiment, the leak current when the gate voltage (VG) is 0 (V) and the leak current under the reverse bias are significantly reduced.

Further, according to this embodiment, the size relationship between the gate electrode (45) and the resist pattern (51) due to over-etching is used satisfactorily, and it is completely due to the positional accuracy of the mask and the like. And the length (d) of the lightly doped region can be controlled. The low-concentration doped region length (d) means a high-concentration doped region (2
Lightly doped regions (25a) and (25b) that do not overlap with 3a) and (23b)
Of the lightly doped regions (25a) and (25b).

According to this embodiment, the length (d) of the lightly doped region can be controlled relatively freely by overetching the gate electrode film (41), and only the gate insulating film (31) is formed. As the ion implantation is performed via As, the diffusion coefficient As ⁺ is small ^. Ion, BF ₂ ⁺ Ions, etc. can be used. Therefore, it is easier to control the length (d) of the lightly doped region.

For the above reason, the symmetry of the length (d) of the lightly doped region adjacent to both ends of the gate electrode (45) can be ensured over a large area, so that the characteristics are required to be uniform over a large area. It is most suitable for an active matrix type liquid crystal display device. Next, another embodiment of the present invention will be described with reference to FIG. 4A to 4C are performed in the same manner as in the above-described embodiment, and the gate electrode 45 is over-etched into a predetermined shape.

After that, in the present embodiment, impurities having different diffusion coefficients of the implanted ions are implanted as the implanted ions in the high concentration impurity implantation and the implantation ions in the low concentration impurity implantation. That is, it is possible to form a good LDD structure by using implanted ions having different sizes of the resist pattern (51) and the gate electrode (45) and different diffusion coefficients.

That is, as shown in (d) of FIG.
As using the pattern (51) as a mask⁺ Implanting ions
To form heavily doped regions (23a) and (23b). And
Continue without removing the resist pattern (51).
P in 2 (d)⁺ Low concentration dose using ions
Form regions (25a) and (25b).

Thereafter, the resist pattern (51) is peeled off, and a high temperature oxide (HTO) film is formed at a film forming temperature of 830 ° C. for 1 hour to form an interlayer insulating layer (61), as in the above-mentioned embodiment. And contact holes (63a) and (63b) are formed in the interlayer insulating layer (61) as shown in FIG.

Under the film forming conditions of the interlayer insulating layer (61), injection
ON is activated, but each implanted ion has a diffusion coefficient.
Since the numbers are different, the gate electrode (45)
The bite length is As⁺ Ion 0.4 micron, P
⁺ Ions are 1.5 microns. In addition, P-channel tiger
In the case of a transistor, form the heavily doped regions (23a), (23b).
As ions to be implanted,⁺ Aeon's Kawa
For example, BF₂ ⁺ Ions are available and low
Implanted ions for forming the heavily doped regions (25a), (25b)
As P⁺ Instead of ions, for example B⁺ ion
Is available.

Then, as shown by (g) in the figure, the doped regions (28a), (2) are formed through the contact holes (63a), (63b).
Metal wirings (71a) and (71b) connected to 8b) were formed to form a thin film transistor.

As described above, according to the manufacturing method of this embodiment, the ion implantation can be performed continuously as compared with the above-mentioned embodiment,
It can be manufactured more efficiently. Further, the symmetry of the lightly doped region length (d) is maintained because the difference in diffusion coefficient of implanted ions is utilized instead of using a mask or the like.

As described in detail above, according to this embodiment,
It is possible to secure the symmetry of the length of the low-concentration doped region adjacent to both ends of the gate electrode over a large area by a simple manufacturing process without the need for highly accurate alignment. Therefore, it is particularly suitable for a large area such as a switching element of each display pixel of an active matrix type liquid crystal display device or a drive circuit element.

According to the present invention, it is also possible to form thin film transistors having different conductivity types, that is, a p-channel thin film transistor and an n-channel thin film transistor on the same substrate.

First, as a patterning film for patterning the gate electrode, the gate electrode is over-etched using a silicon oxide film or the like, and then a resist mask is used to form desired portions of the n-channel portion and the p-channel portion. It can be formed by ion-implanting and diffusing impurities having different diffusion coefficients.

Of course, a resist is useful as a patterning film for patterning the gate electrode, but it goes without saying that a silicon oxide film may be used in consideration of pattern accuracy and the like.

[0044]

As described above, according to the present invention, the size relationship between the patterning film for patterning the gate electrode formed by isotropic etching and the gate electrode can be effectively used, and the size relationship between Since the length of the lightly doped region is determined by the difference in the diffusion coefficient of the implanted ions, it is possible to form a thin film transistor having an LDD structure that is excellent in the symmetry of the source / drain and is uniform over a large area.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view of a thin film transistor according to an embodiment of the present invention.

FIG. 2 is a manufacturing process diagram illustrating a method of manufacturing a thin film transistor according to an embodiment of the present invention.

FIG. 3 is a diagram showing a current-voltage characteristic of a thin film transistor according to an embodiment, in which a vertical axis represents a drain current (ID) and a horizontal axis represents a gate voltage (VG).

FIG. 4 is a manufacturing process diagram illustrating a method of manufacturing a thin film transistor according to another embodiment of the present invention.

FIG. 5 is a manufacturing process diagram for explaining a conventional method of manufacturing a thin film transistor.

[Explanation of symbols]

 (1) ... thin film transistor (11) ... quartz substrate (21) ... polycrystalline silicon film (45) ... gate electrode (51) ... resist pattern

Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 8617-4M H01L 21/265 F

Claims (3)

[Claims] 1. A step of providing a polycrystalline silicon film on a substrate and an insulating film on the polycrystalline silicon film, a step of providing a gate electrode film on the insulating film, and the gate electrode film on the gate electrode film. A step of providing a patterning film for patterning the gate electrode film, a step of overetching the gate electrode film by an isotropic etching method so as to be smaller than the pattern of the patterning film to form a gate electrode, and the island shape. A thin film transistor comprising: a step of implanting impurities into polycrystalline silicon to form a source region and a drain region; and a step of forming and processing a metal wiring film connected to the source region and the drain region. Manufacturing method. 2. The step of implanting an impurity according to claim 1 to form a source region and a drain region comprises implanting an impurity using the patterning film as a mask, and removing the patterning film to remove the impurity. And a step of injecting the thin film transistor. 3. A method of manufacturing a thin film transistor, wherein the step of implanting an impurity according to claim 1 to form a source region and a drain region implants two kinds of impurities having different diffusion coefficients.