JPH05181793A - SCSI bus control method - Google Patents

Abstract

(57) [Summary] [Object] A bus control method for controlling a hard disk connected by a SCSI bus, and an object of the present invention is to control data transfer only in a data phase by bypass without passing through a general-purpose LSI. [Structure] CC interface unit 1, microprocessor unit 2, direct memory access controller 3, buffer memory 4, read-only memory
In a file memory control device 9 having a memory 5, a random access memory 6 and a SCSI protocol controller 7, and controlling connection of a hard disk device 8 by a SCSI bus, the SCSI protocol controller 7 and the hard disk device 8 are connected. By providing the data transfer control device 10 by bypass on the SCSI bus connecting the
Only the data transfer in the transfer phase of the I protocol is configured to be controlled by the data transfer control device 10 provided outside the SCSI protocol controller 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus control method for controlling hard disks connected by a SCSI bus. The SCSI bus (scuzzy bus) is a connection bus having a general-purpose interface with a hard disk device, a magnetic tape device, etc., and can transfer 8-bit parallel data by a series of 50 cores. FIG. 4 shows an example of the system configuration of the exchange using the SCSI bus.

In FIG. 4, 31 is a central control unit (C
C), 32 is a main memory (MM), 33 is a channel controller (CHC), 34 is a file memory controller (FMC),
Reference numeral 35 is a data terminal control device (DCC), 36 is a hard disk device (HD), and 37 is a data terminal device (DT).
A 50-core SCSI bus is used between the file memory control device 34 and the hard disk device 36, and a serial interface bus (SIF) bus is used between the data terminal control device 35 and the data terminal device 37.

The channel controller 33 is a direct memory access controller (DMAC) and is a file memory controller connected to the SCSI bus via the file memory controller 34 and the data terminal controller 35.
Central control unit by controlling 34 and hard disk unit 36
The main memory is operated by operating each device by the command from 31.
Inputs / outputs data to / from 32.

[0004]

2. Description of the Related Art A conventional file memory controller (FM)
FIG. 5 shows a block diagram of C). In the figure, 21 is a CC interface unit, 22 is a microprocessor unit (MPU), and 23 is a direct memory access unit.
Controller (DMAC), 24 is buffer memory (B
M), 25 is read only memory (ROM), 26 is random access memory (RAM), 27 is SCSI
Protocol controller (SPC), 28 is a hard disk drive (HD), 29 is a file memory control device (FM)
C) is shown.

The file memory controller 29 operates according to a command from the central controller (CC), and the main memory (M
Data is input to and output from M). The CC interface unit 21 holds a command from the CC, a command register for the internal MPU to read, a status of the FMC for holding the status register for the CC to read, and a data transfer control circuit between the FMC and the MM. The microprocessor unit 22 operates by decoding the program in the ROM. The direct memory access controller 23 controls data transfer between the SPC 27 and the BM 24. The random access memory 26 is a memory accessible by the MPU, and the SPC 27 controls data transfer with the hard disk device 28.

[0006]

A general-purpose control LSI is generally used as a SCSI protocol controller (SPC) which is a general-purpose interface for hard disk devices, MT devices and the like. At this time, the throughput performance such as the transfer speed is limited by the maximum transfer capacity of the LSI when the hard disk device or the like has a high speed. Further, when a higher-speed general-purpose LSI is used, the cost becomes high, and the soft interface is largely changed.

The present invention is directed to a file memory controller (FM).
In C), by replacing only the data phase, which has the greatest effect on throughput improvement, with an external high-speed processing circuit, and controlling other complicated protocol processing with a general-purpose LSI, a relatively small amount of hardware increases and high performance is achieved. The purpose is to make the control circuit inexpensive.

[0008]

FIG. 1 is a block diagram showing the principle of the present invention. In the figure, 1 is a CC interface section (C
CINF), 2 is a microprocessor unit (MP
U), 3 is a direct memory access controller (DMAC), 4 is a buffer memory (BM), 5 is a read only memory (ROM), and 6 is a random memory.
Access memory (RAM), 7 is SCSI protocol controller (SPC), 8 is hard disk drive (HD), 9 is file memory control device (FMC), 10
Indicates a data transfer controller (DTC).

The file memory controller 9 operates according to a command from the central controller (CC), and the main memory (M
Data is input to and output from M). The CC interface unit 1 holds the command from the CC, holds the status of the command register and the file memory control device 9 for the internal microprocessor unit 2 to read, and the status register and the file memory control device for the CC to read. 9 and a data transfer control circuit between the MM. The microprocessor unit 2 decodes the program in the read-only memory 5 and operates. Direct memory access controller 3 is SCSI
It controls the data transfer between the protocol controller 7 and the buffer memory 4. The random access memory 6 is a memory that the microprocessor unit 2 can access, and the SCSI protocol controller 7 controls data transfer with the hard disk device 8.

The data transfer control device 10 is provided as a bypass between the SCSI protocol controller 7 and a file device such as the hard disk device 8 and only transfers data in the data transfer phase of the SCSI protocol. It is controlled outside the controller 7.

[0011]

The SCSI bus phase sequence diagram is shown in FIG. In the SCSI protocol, a plurality of phases are combined and continuously controlled to perform the entire input / output operation. In the figure, is the bus unused phase, is the bus allocation adjustment phase that adjusts which device the bus is allocated to, is the device selection connection phase that actually connects this device when the allocated device is decided, is the actually repeated transfer phase (Command, data, status, message).

First, in the bus unused phase, the file memory controller (FMC) 9 sends a selection command to the SCSI protocol controller (SPC) 7.
To start. The SPC 7 controls the bus allocation adjustment phase and the device selection connection phase by hardware, and connects the FMC 9 and the hard disk device 8 to the SCSI bus. Next, when the data phase is detected by the status register in the SPC 7, the data is set in the register in the data transfer control device (DTC) 10.

The RE which controls the input / output of data by this
Q / ACK is switched to the DTC circuit side, and data transfer is performed under the control of DTC10. Data transfer between the SCSI bus and the buffer memory 4 is performed by the timing generation circuit in the DTC 10 and the direct memory access controller 3. (At this timing, by using a memory that can be accessed at high speed as the buffer memory, it can be configured to operate at the maximum speed of the file device.) At this point, when the data transfer ends, the SCSI transfer phase changes to the message phase. Then, when the microprocessor unit (MPU) 2 knows that the transfer is completed, the DTC 10 is switched and the message and status phase are continuously processed to the HD 8 via the SPC 7 to complete a series of operations.

[0014]

FIG. 3 shows an embodiment of a block diagram of a data transfer control device (DTC) according to the present invention. In the figure, the same numbers as in the principle configuration diagram indicate the same devices, and 3 indicates direct
Memory access controller (DMAC), 7 is S
CSI protocol controller (SPC), 8 hard disk (HD), 9 file memory controller (F
MC) and 10 are data transfer controllers (DTC).

In the data transfer control device (DTC) 10, 11 is a control register (CTL), 12 is a switching selector (SEL), 13 is a timing generator (TGN), 14 is a data input / output controller (DIOC), 15 Indicates an interrupt signal generator (IRQGN). Data transfer controller 10 is SCS
Connected to SPC7 and HD8 by I bus, and D
Control signals are transmitted and received to and from the MAC3.

The control register 11 is a register assigned to the address space of the MPU to enable the DTC circuit, and the switching selector 12 outputs the REQ / ACK signal, which is a SCSI control signal, to the SPC 7 or D by the output of the control register 11.
Used to switch connect to TC10. The timing generator 13 receives the REQ signal from the SCSI bus,
3 sends a DMA request signal (DMAREQ) to
A to SCSI bus by A response signal (DMAACK)
Controls CK output timing.

The data input / output control unit 14 for controlling the input / output of data is controlled by the phase control signal PH from the SCSI bus and controls the data direction and the timing generation unit.
The control signal from 13 controls the data input / output timing. Further, the interrupt signal generation unit 15 detects that the SCSI bus phase is no longer in the data transfer phase (transfer end or abnormality), and generates an IRQ (interrupt signal) to the MPU.

In the SCSI protocol, as shown in FIG. 2, a plurality of phases are combined and continuously controlled to control the overall input / output. First, in the bus unused phase, the FMC 9 activates a selection command to the SPC 7. S
The PC 7 hardware-controls the bus allocation adjustment / device selection connection phase and couples the FMC 9 and HD 8 to the SCSI bus. After that, in the command phase state, FMC9 becomes SP
Control parameters are sent via C7.

Next, when the data phase is detected by the status register in the SPC 7, the data is set in the control register 11 in the DTC 10. As a result, REQ / ACK for controlling data input / output is switched to the DTC circuit side, and data transfer is performed under the control of DTC10. Data transfer between the SCSI bus and BM4 is performed by the timing generator 13 and the DMAC3. (At this timing, it is possible to configure the BM4 to operate at the highest speed that the HD8 has by performing a high-speed accessible memory.) When the transfer ends here, the SCS
Since the I phase is the message phase, the interrupt signal generation unit 15 generates the interrupt signal IRQ, and the MPU can know the end of the transfer. Next, CTL11 DTE
By clearing the signal, the message and status phases are continuously processed through the SPC 7, and the series of operations is completed.

[0020]

By replacing only the data phase, which has the greatest effect on the throughput direction, with an external high-speed processable circuit, and controlling other complicated protocol processes with a general-purpose LSI, a relatively small amount of hardware increases and The performance circuit can be constructed at low cost.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of the present invention.

FIG. 2 Sequence diagram of SCSI bus phase

FIG. 3 is an example of a block configuration diagram of a data transfer control device.

[Fig. 4] System configuration example of an exchange using a SCSI bus

FIG. 5 is a block configuration diagram of a conventional file memory control device.

[Explanation of symbols]

 1,21 CC interface section 2,22 Microprocessor unit 3,23 Direct memory access controller 4,24 Buffer memory 5,25 Read only memory 6,26 Random access memory 7,27 SCSI protocol・ Controller 8, 28 Hard disk device 9, 29 File memory controller 10 Data transfer controller 11 Control register 12 Switch selector 13 Timing generator 14 Data input / output controller 15 Interrupt signal generator 31 Central controller 32 Main memory 33 Channel controller 34 File memory controller 35 Data terminal controller 36 Hard disk device 37 Data terminal device

Claims (2)

[Claims] 1. A CC interface unit (1), a microprocessor unit (2), a direct memory access controller (3) and a buffer memory (4).
A read only memory (5), a random access memory (6) and a SCSI protocol controller (7), and a hard disk drive (8)
File memory controller for connection control by bus (9)
In the above, in the SCSI bus connecting the SCSI protocol controller (7) and the hard disk device (8), a data transfer control device (10) is provided in a bypass manner, and only the data transfer in the transfer phase of the SCSI protocol is performed. ,
A SCSI bus control method characterized by controlling by a data transfer control device (10) provided as a bypass outside a SCSI protocol controller (7). 2. A data transfer control device (10) provided as a bypass outside the SCSI protocol controller (7), and a control register (11) for enabling a bypass circuit and the control register (10). Switching selector (12) that switches the connection of control signals by the output of 11) and SCS
A timing generator (13) for controlling the ACK output timing to the I bus, a buffer input / output controller (14) for controlling the data input / output for bypassing, and an SCS.
2. The SCSI bus control method according to claim 1, further comprising an interrupt signal generator (15) which detects switching of the I phase and generates an IRQ signal.