JPH0518312B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a video signal recording device, and particularly to a video signal recording device that records one or several fields of video using a memory, for example, in a television receiver or a video tape recorder. This invention relates to improvements in signal recording devices.

[Prior Art] Conventionally, devices for recording video signals as described above record composite video signals as they are or as A/
There was one that was recorded as a digital signal using a D converter. However, the composite video signal
As shown in Figure 1, when a horizontal synchronization signal and a vertical synchronization signal are included, and when recording in memory, only the time corresponding to the period of the horizontal and vertical synchronization signals or the recording signal level range corresponding to the level of the synchronization signal is recorded. It required extra memory. In response, a method has been proposed to reduce memory usage without recording the synchronization signal part, but this method requires a circuit that generates and adds a synchronization signal to the reproduced video signal during playback. This has the disadvantage that new equipment is required, making the equipment complex and expensive.

[Summary of the Invention] This invention was made to eliminate the drawbacks of the conventional ones as described above, and it separates the address inputs of the memory into two sets, and connects to each address input to specify the storage location of the memory. It is an object of the present invention to provide a simple and inexpensive video signal recording device by installing a designated address counter and simultaneously generating a synchronization signal by the address counter.

The above objects and other objects and features of the present invention will become more apparent from the following detailed description with reference to the drawings.

[Embodiment of the Invention] FIG. 2 is a schematic block diagram showing an embodiment of the invention. In the figure, an input terminal 1 is given a composite video signal a to be recorded. This composite video signal a is given to a synchronization signal separation circuit 2.
The synchronization signal separation circuit 2 is a circuit for separating a given composite video signal a into a video signal b that does not include a synchronization signal, a horizontal synchronization signal c, and a vertical synchronization signal d. Video signal b is given to video signal memory 3. This video signal memory 3 is an A/D converter for converting the video signal b into a digital signal.
A converter 31, a memory 32 for storing the digital video signal output of the A/D converter 31, and a D/A converter 33 for converting the digital video signal read from the memory 32 into an analog video signal. include. The memory 32 includes a horizontal address counter 4
The address is specified by the horizontal address A0 and vertical address A1 given from the vertical address counter 5. Horizontal address counter 4 generates a horizontal address by counting the clocks generated from clock generation circuit 6. Further, the vertical address counter 5 generates a vertical address by counting the overflow signal h of the horizontal address counter 4.
The output of the video signal memory 3, ie, the analog video signal g that does not include a synchronization signal, is provided to a reproduction synchronization signal addition circuit 7. Further, the reproduction synchronization signal adding circuit 7 is supplied with a reproduction horizontal synchronization signal j and a reproduction vertical synchronization signal k from the reproduction synchronization signal generation circuit 8. The reproduction synchronization signal addition circuit 7 is a circuit for adding a reproduction horizontal synchronization signal j and a reproduction vertical synchronization signal k to the video signal g to generate a composite synchronization signal l. This composite video signal l is output from the output terminal 9.

On the other hand, the horizontal synchronization signal c and vertical synchronization signal d separated by the synchronization signal separation circuit 2 are provided to the address counter control circuit 10. Address counter control circuit 10 includes a switching circuit 101 and two delay circuits 102 and 103. The switching circuit 101 includes a changeover switch having terminals m, n, and o, and a changeover switch having terminals p, q, and r. A horizontal synchronizing signal c is applied to a terminal m, a reproduced horizontal synchronizing signal j is applied to a terminal n, and a terminal o is connected to a delay circuit 102. Further, a vertical synchronizing signal d is applied to a terminal p, a reproduced vertical synchronizing signal k is applied to a terminal q, and a terminal r is connected to a delay circuit 103. These two changeover switches are switched in response to a changeover signal input from the input terminal 11. That is, terminal o is connected to either terminal m or n, and terminal r is connected to either terminal p or q. Delay circuit 102
The output e of the delay circuit 103 and the output f of the delay circuit 103 are applied as reset pulses to the horizontal address counter 4 and the vertical address counter 5, respectively. The reproduction synchronization signal generation circuit 8 includes two delay circuits 81 and 82 and two single pulse generation circuits 83 and 84. Delay circuits 81 and 8
2 are given overflow signals h and i from horizontal address counter 4 and vertical address counter 5, respectively. The outputs of delay circuits 81 and 82 are sent to single pulse generation circuit 83, respectively.
and 84. Single pulse generation circuit 83
and 84 output the aforementioned reproduced horizontal synchronizing signal j and reproduced vertical synchronizing signal k.

FIG. 3 is a waveform diagram showing signals (especially signals a, b, c, e, g, h, j, and l) in each part of the circuit shown in FIG. The operation of the embodiment shown in FIG. 2 will be described below with reference to FIG.

First, the operation when recording a video signal will be explained. In this case, the composite video signal a input from the input terminal 1 is input into the video signal memory 3 as a video signal b from which the horizontal and vertical synchronization signals are removed by the synchronization signal separation circuit 2. In the video signal memory 3 , the input video signal b is converted into a digital signal by an A/D converter 31 and is input into a memory 32 . On the other hand, the horizontal synchronization signal c and vertical synchronization signal d separated by the synchronization signal separation circuit 2 are input to the address counter control circuit 10, and during recording, the switching circuit 101 connects the terminals m and o, and the terminals p and r, respectively. Therefore, it is guided to delay circuits 102 and 103. Then, after a certain time delay, it is input to the reset input R of the horizontal address counter 4 and the vertical address counter 5. After being reset by the delayed horizontal synchronizing signal e, the horizontal address counter 4 counts the signals from the clock signal generating circuit 6 and outputs the count value as the horizontal address signal A0. Further, after the vertical address counter 5 is reset by the delayed vertical synchronization signal f, the horizontal address counter 4
The overflow signal h is counted and the count value is output as the vertical address signal A1. Horizontal address counter 4 and vertical address counter 5
After overflowing, the count will not be output until it is reset.

Here, the delay time of the delay circuits 102 and 103 is set to the time from the horizontal synchronization signal c and the vertical synchronization signal d to the start of the video signal b, and the overflow count of the horizontal address counter 4 and the vertical address counter 5 is set. If the value is set so that overflow occurs at the end of the recording signal b, the signal can be recorded in the memory 32 only during the valid period of the video signal b. Therefore, the memory 32 can save capacity for storing synchronization signals.

Next, the operation during playback will be explained. In this case, the digital signal read from the memory 32 is input to the A/D converter 33 and output as a reproduced video signal g. Further, the overflow signals h and i of the horizontal address counter 4 and the vertical address counter 5 are delayed for a certain period of time by delay circuits 81 and 82, and then sent to a single pulse generation circuit 83.
and 84, resulting in a reproduced horizontal synchronizing signal j and a reproduced vertical synchronizing signal k having the same pulse length as the horizontal synchronizing signal c and the vertical synchronizing signal d, respectively,
In the reproduction synchronization signal addition circuit 7, the reproduction video signal g
, and outputs a reproduced composite video signal l to the output terminal 9. On the other hand, the reproduced horizontal synchronization signal j and the reproduced vertical synchronization signal k are transmitted to the address counter control circuit 1.
0, and during playback, switching circuit 101 is guided to delay circuits 102 and 103 because terminals n and o and terminals q and r are connected, respectively.
Then, after a certain time delay, it is input to the reset inputs R of the horizontal and vertical address counters 4 and 5. The operations of horizontal and vertical address counters 4 and 5 are the same as during recording.

Here, the delay times of the delay circuits 102 and 103 are set to the time from the horizontal synchronizing signal c and the vertical synchronizing signal d to the start of the video signal b, as in the case of recording, and the delay times of the delay circuits 83 and 84 are also set. They are set to the time from the end of video signal b to the next horizontal synchronization signal c and vertical synchronization signal d, respectively. In this way, the time from the reproduced horizontal synchronizing signal j and the reproduced vertical synchronizing signal k to the start of the reproduced video signal g becomes equal to the time from the horizontal synchronizing signal c and the vertical synchronizing signal d to the start of the video signal b, The time from the end of the playback video signal g to the next playback horizontal synchronization signal j and playback vertical synchronization signal k is equal to the time from the end of the video signal b to the next horizontal and vertical synchronization signals c and d, and the playback horizontal synchronization signal The periods of the signal j and the reproduced vertical synchronization signal k are equal to the periods of the horizontal synchronization signal c and the vertical synchronization signal d. Therefore, the reproduced composite video signal l
becomes a signal equal to the composite video signal a.

[Effects of the Invention] As described above, according to the present invention, the address input of the video signal memory is separated into two sets, and the horizontal and vertical synchronization during playback is achieved using an address counter that specifies the memory storage and readout position. Since the signal is generated, only the video signal can be stored in the memory without using a special synchronization signal generation circuit, and the circuit configuration can be made simple and inexpensive, and the memory capacity can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a waveform diagram of a composite video signal. FIG. 2 is a schematic block diagram showing one embodiment of the present invention. FIG. 3 is a waveform diagram of signals at various parts of the device shown in FIG. 2. In the figure, 1 is an input terminal, 2 is a synchronization signal separation circuit, 3 is a video signal memory, 4 is a horizontal address counter, 5 is a vertical address counter, 6 is a clock generation circuit, 7 is a reproduction synchronization signal addition circuit, and 8 is a reproduction circuit. 10 represents a synchronizing signal generation circuit and an address counter control circuit.

Claims (1)

[Scope of Claims] 1. Composite video signal input means for inputting a composite video signal to be recorded; signal separation means for separating the composite video signal into a video signal, a horizontal synchronization signal, and a vertical synchronization signal; and a video signal memory for recording the video signal separated by the signal separation means in a storage location designated by the vertical address signal; a horizontal address signal for designating the storage location of the video signal memory; horizontal and vertical address counters generating vertical address signals, the horizontal and vertical address counters respectively outputting a horizontal count status signal indicating a horizontal address count status and a vertical count status signal indicating a vertical address count status; reproduction synchronization signal generating means for generating a reproduction horizontal synchronization signal and a reproduction vertical synchronization signal in response to a horizontal count state signal and a vertical count state signal respectively output from the horizontal and vertical address counters; and said reproduction horizontal synchronization signal and reproduction. reproduction synchronization signal adding means for adding a vertical synchronization signal to the video signal read from the video signal memory; and synchronizing with the horizontal synchronization signal and vertical synchronization signal separated by the signal separation means during recording,
A video signal recording device comprising address counter control means for controlling the horizontal and vertical address counters in synchronization with the reproduction horizontal synchronization signal and the reproduction vertical synchronization signal during reproduction. 2. The horizontal address counter outputs an overflow signal in a counting operation for generating a horizontal address signal as the horizontal count state signal, and the vertical address counter outputs an overflow signal in a counting operation for generating a vertical address signal. The reproduction synchronization signal generating means outputs the vertical count state signal as the vertical count state signal; 2. The video signal recording device according to claim 1, wherein the reproduction horizontal synchronization signal and the reproduction vertical synchronization signal are generated after a predetermined period of time after an overflow occurs. 3. The address counter control means responds to the horizontal synchronization signal and vertical synchronization signal separated by the signal separation means during recording, and in response to the reproduction horizontal synchronization signal and reproduction vertical synchronization signal during reproduction, for a certain period of time. 3. The video signal recording apparatus according to claim 1, further comprising address counter reset means for later resetting the horizontal address counter and the vertical address counter.