JPH05183155A - Semiconductor device and fabrication thereof - Google Patents

Abstract

(57) [Summary] [Object] A semiconductor device having a MOS transistor is intended to suppress variation in threshold voltage due to a short channel effect. A M including a gate electrode 3 formed on a semiconductor layer 1 via a gate insulating film 2, and a source 4 and a drain 5 formed on the semiconductor layer 1 on both sides of the gate electrode 3.
In a semiconductor device having an OS transistor, the gate insulating film 2 is formed by a plurality of dielectric films 2a and 2b distributed in the gate length direction and having different dielectric constants, and the dielectric constant increases as the gate length decreases. It is configured including that the distribution ratio of the dielectric film 2a is set small.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a MOS transistor and a manufacturing method thereof.

[0002]

2. Description of the Related Art A MOS transistor generally has a structure as shown in FIG. 5 (c), and a gate electrode 53 formed on a semiconductor layer 51 via an insulating film 52 and a semiconductor layer 51 on both sides of the gate electrode 53. The formed source layer 54 and drain layer 55
It consists of

Next, the manufacturing process will be briefly described with reference to FIG. First, as shown in FIG. 5A, a conductive film 56 is formed on a semiconductor layer 51 such as silicon with an insulating film 52 made of a single material having a uniform thickness interposed therebetween.
6 is patterned by photolithography to form a gate electrode 53 (FIG. 5 (b)).

Then, using the gate electrode 53 as a mask, impurities are ion-implanted into the semiconductor layer 51 on both sides of the gate electrode 53, and the impurities are activated to form a source layer 54 and a drain layer 55 (FIG. 5C).

By the way, the channel length between the source layer 54 and the drain layer 55 formed in self-alignment is governed by the gate length.

[0006]

However, when the semiconductor device is miniaturized and the channel length (gate length) of the MOS transistor is shortened, a short channel effect occurs, and the channel length is designed as shown in FIG. 5 (d). There is a problem that the threshold voltage Vth tends to fluctuate even if it deviates slightly from the value.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device including a MOS transistor capable of suppressing the fluctuation of the threshold voltage due to the short channel effect, and a manufacturing method thereof. ..

[0008]

As illustrated in FIG. 1, the above-mentioned problems are solved by a gate electrode 3 formed on a semiconductor layer 1 via a gate insulating film 2 and both sides of the gate electrode 3. In a semiconductor device having a MOS transistor composed of a source 4 and a drain 5 formed in the semiconductor layer 1, the gate insulating film 2 has a plurality of dielectric films 2a, 2b distributed in the gate length direction and having different dielectric constants. And a distribution ratio of the dielectric film 2a having a higher dielectric constant is set to be smaller as the gate length becomes shorter.

Alternatively, as illustrated in FIGS. 1 and 4, a MOS is formed on the semiconductor layer 1 via the first dielectric films 2a and 28.
The step of forming the gate electrode 3 of the transistor, and the etching of at least one end portion in the gate length direction of the first dielectric film 2a, 28 under the gate electrode 3 to form the lateral grooves 16, 18 is performed. The step of forming and filling the lateral grooves 16 and 18 with the second dielectric films 2b and 29 having a dielectric constant lower than that of the first dielectric films 2a and 28, 28 and the second dielectric films 2b and 29 to form a gate insulating film of the MOS transistor, and the source 4 of the MOS transistor self-aligned with the semiconductor layer 1 using the gate electrode 3 as a mask. And a step of forming the drain 5 are provided.

Alternatively, as illustrated in FIG. 3, a step of patterning the first dielectric film 2a and the first conductive film 21 which are sequentially stacked on the semiconductor layer 1 into a strip shape using the same mask. Then, the semiconductor layer 1 exposed on both sides of the first dielectric film 2a is oxidized to form a second dielectric film 23 having a dielectric constant lower than that of the first dielectric film 2a. A step of stacking the semiconductor 24 on the whole, and the semiconductor 2
4 is anisotropically etched to leave the semiconductor 24 on both side walls of the first conductive film 2a, and a gate electrode 25 of a MOS transistor is formed by the first conductive film 21 and the semiconductor 24 on the side wall. , The first dielectric film 2a and the second dielectric film 2 under the gate electrode 25
4 as the gate insulating film 26 of the MOS transistor, and using the gate electrode 25 as a mask to introduce impurities into the semiconductor layer 1 to form the source 26 and the drain 26 of the MOS transistor. This is achieved by a method for manufacturing a semiconductor device characterized by the above.

[0011]

According to the present invention, in the MOS transistor, the high dielectric film 2a and the low dielectric film 2b are distributed in the gate length direction to form the gate insulating film 2, and the dielectric constant increases as the gate length decreases. The distribution ratio of the dielectric film 2a having a high temperature is set to be small.

Therefore, when the gate length is formed to be shorter than the designed value, the influence of the low dielectric film 2b becomes large and the reduction of the threshold voltage is suppressed, and the gate length becomes larger than the designed value. In this case, the proportion of the low dielectric film 2b is small, so that the increase in the threshold voltage can be suppressed.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. (A) Description of First Embodiment of the Present Invention FIG. 1 is a sectional view of an apparatus showing a first embodiment of the present invention.

In FIG. 1D, reference numeral 1 is a p-type silicon layer (semiconductor layer) on which a gate electrode 3 is formed via a gate insulating film 2 which will be described later. An n-type source layer 4 and an n-type drain layer 5 are formed in self-alignment on the silicon layer 1 on both sides of the source layer 4
The distance between the drain layer 5 and the drain layer 5 is the channel length.

The gate insulating film 2 is formed of the gate electrode 3
High dielectric constant film 2a having a high dielectric constant composed of a three-layer structure of SiO ₂ / Si ₃ N ₄ / SiO ₂ formed under the central region of SiO ₂ and low dielectric constant composed of SiO ₂ formed on both sides thereof. Low dielectric constant film 2b
And is configured such that as the gate length L becomes shorter, the ratio of the length of the high dielectric constant film 2a to the gate length L becomes smaller.

Next, the operation of the above embodiment will be described.
First, the channel length L of the MOS transistor is gradually reduced from 1 μm, and a plurality of the high dielectric constant film 2a having the ratio of the gate length L simultaneously reduced are formed. Examining Vth Fig. 2
The result shown by the solid line is obtained.

On the other hand, as shown in FIG. 5 (c), regarding the conventional MOS transistor in which the gate insulating film 52 is formed of a single material to have a uniform film thickness, the relationship between the gate length L and the threshold voltage Vth is shown. Is obtained, the characteristics shown by the broken line in FIG. 2 are obtained.

As a result, according to the MOS transistor of this embodiment, the threshold voltage Vth increases as the gate length decreases.
It can be seen that the rate of reduction of the threshold voltage is smaller than that of the conventional MOS transistor, and the fluctuation of the threshold voltage due to the short channel effect is small.

This is because as the channel length governed by the gate length L becomes shorter, the proportion of the high-dielectric film 2a also becomes smaller, and the factor for reducing the threshold voltage Vth is reduced. Therefore, even if the channel length L of the gate electrode 3 slightly changes from the designed value, the fluctuation of the threshold voltage Vth is suppressed, and stable operation can be obtained.

Next, the manufacturing method of the above embodiment will be described with reference to FIG.
Description will be made based on (a) to (d). First, as shown in FIG. 1 (a), the upper surface of the silicon layer 1 is thermally oxidized to grow a first SiO ₂ film 11 having a thickness of 20 Å, then, by a CVD method, a first SiO ₂ film 11 On top of which Si ₃ N ₄ film 12 and second SiO ₂
Each film 13 is grown to a thickness of 20Å.

After that, a polycrystalline silicon film 14 is formed on the entire surface, a photoresist 15 is applied on the polycrystalline silicon film 14, and the photoresist 15 is exposed and developed to form a band-shaped pattern covering the gate region. Using the mask as a mask, each layer from the polycrystalline silicon film 14 to the first SiO ₂ film 11 is etched by the reactive ion etching method.

Then, the strip-shaped polycrystalline silicon film 14 remaining under the photoresist 15 is used as the gate electrode 3,
The SiO ₂ films 11 and 13 and the Si ₃ N ₄ film 12 thereunder are used as the high dielectric constant film 2a. The design gate length L of the gate electrode 3 is
The thickness is 0.3 μm.

After this, the SiO ₂ film 1 under the gate electrode 3 is formed.
1, 13 and the Si ₃ N ₄ film 12 are isotropically etched by 0.05 μm on both sides by a wet etching method to form a lateral groove 16 under the side portion of the gate electrode 3.

Then, the surfaces of the polycrystalline silicon film 14 and the silicon layer 1 located above and below the lateral groove 16 are thermally oxidized.
The SiO ₂ film 17 is formed, and the SiO ₂ film 1 formed in the lateral groove 16 is formed.
7 is the low dielectric film 2b. Then, the low dielectric film 2b and the high dielectric film 2a form the gate insulating film 2.

Next, using the gate electrode 3 as a mask, arsenic is ion-implanted into the semiconductor layer 1 with an acceleration energy of, for example, 40 keV, and this is activated to form a source layer 4 and a drain layer 5.

When a MOS transistor is formed through these steps, even if the gate length (channel length) becomes shorter than the design value, the length of the low dielectric film 2b in the gate length direction does not change and the high dielectric film is formed. Only the length of 2a will change.

As a result, when the gate length L is formed shorter than the designed value, the influence of the low dielectric film 2b becomes large, and the reduction of the threshold voltage Vth is suppressed. Further, when the gate length L becomes larger than the design value, the ratio occupied by the low dielectric film 2b becomes small, so that the threshold voltage V
The rise of th can be suppressed.

The lateral groove 16 can be formed by the reactive ion etching method, and in this case, the ions are supplied obliquely. (B) Description of the Second Embodiment of the Present Invention Although the gate electrode is formed of a polycrystalline silicon film in the above-mentioned embodiments, it can be similarly applied to the case of using metal such as tungsten, titanium, aluminum or silicide. When a metal is used, the following manufacturing method can be used.

The manufacturing process will be described with reference to FIG. First, similarly to the first embodiment, a high dielectric film 2a having a three-layer structure of SiO ₂ film 11 / Si ₃ N ₄ film 12 / SiO ₂ film 13 is formed on the silicon layer to a thickness of 60Å.

Then, as shown in FIG. 3 (a), a tungsten film 21 is deposited by several thousand liters by a CVD method, and a stripe-shaped mask covering the gate region is used as a photoresist 22.
Then, each layer from the tungsten film 21 to the first layer SiO ₂ film 11 is etched.

Thereafter, as shown in FIG. 3B, the surface of the silicon layer 1 on the side of the high dielectric film 2a is thermally oxidized to form a SiO ₂ film 23 having a film thickness of 60 Å. Next, as shown in FIG. 3 (c), a polycrystalline silicon film 24 is laminated on the entire surface in a thickness of about several thousand Å, and this is anisotropically etched perpendicularly to the layer by a reactive ion etching method to form an end tool. The upper surface of the seedling 21 is exposed and the polycrystalline silicon film 24 is left on the sidewall of the tungsten film 21.

The gate electrode 25 is formed by the strip-shaped tungsten film 21 and the polycrystalline silicon film 24 on the side thereof.
(Fig. 3 (d)). In this case, the SiO ₂ film 2 existing under the polycrystalline silicon film 24 on both sides of the gate electrode 25
3 is the low dielectric film 2b. Then, the low dielectric film 2
The gate insulating film 26 is constituted by b and the high dielectric film 2a.

Thereafter, the n-type source layer 26 and the drain layer 27 are formed in the same manner as in the first embodiment. According to such a manufacturing process, since the width of the polycrystalline silicon film 24 forming the gate electrode 25 in the gate length direction is substantially constant, the length of the underlying low dielectric film 2a is equal to the gate length L. Even if it becomes shorter than the design value, it can be kept constant.

Further, since the tungsten film 21 and the high-dielectric film 2a thereunder have the same length, when the tungsten film 21 becomes shorter than the designed value, the ratio of the high-dielectric film 2a having the gate length occupies. As a result, the threshold voltage is reduced and the decrease in threshold voltage is suppressed.

(C) Description of Third Embodiment of the Present Invention In the above-mentioned embodiments, the high dielectric film is formed in the central region of the gate insulating film and the low dielectric films are formed on both sides thereof. As shown in FIG. 4, the low dielectric film may be formed only on one side.

The manufacturing process in this case is as shown in FIGS. 4 (a) to 4 (c). First, a SiO ₂ film 11, a Si ₃ N ₄ film 12 and a SiO ₂ film 13 were sequentially laminated by the same method as shown in FIGS. 1 (a) and 1 (b) of the first embodiment, and a polycrystalline film was formed thereon. After the silicon film 14 is laminated, these are patterned into stripes. Then, the patterned polycrystalline silicon film 14 becomes the gate electrode 3.

Next, reactive ion etching is performed obliquely to remove the SiO ₂ films 11 and 13 under the gate electrode 3 and the Si ₃ N ₄ film.
A lateral groove 18 is formed by etching only one side of the film 12 in the gate length direction.

Thereafter, the lateral groove 18 is filled with a low dielectric film 29 of SiO ₂ by the same method as in the first embodiment, and then the source layer 4 and the drain layer 5 are formed (FIG. 4 (c)). ..
The SiO ₂ film 11, the Si ₃ N ₄ film 12 and the SiO ₂ film 13 under the gate electrode 3 form a high dielectric film 28, and the low dielectric film 29 forms a gate insulating film.

The electric field is strong near the drain layer 5,
Although many hot carriers are generated, the gate insulating film thereon is not formed of the SiO ₂ / Si ₃ N ₄ / SiO ₂ three-layer structure film having many interface states, but is formed of the SiO ₂ film 29. The hot carrier breakdown voltage is high.

(D) Description of Other Embodiments of the Present Invention In the above-mentioned embodiments, SiO ₂ and Si ₃ N ₄ were used as the combination of the high dielectric film serving as the gate insulating film, but Ta ₂ O ₅ and The same applies when other high dielectric constant materials are used.

If the interface order with the semiconductor layer is not taken into consideration, the high dielectric film may be formed of only Si ₃ N ₄ . The semiconductor layer in the above-described embodiments is the semiconductor substrate itself, a semiconductor layer for forming an element of the SOI substrate, a well of the semiconductor substrate, or the like.

[0042]

As described above, according to the present invention, the MO
In the S-transistor, a high dielectric film and a low dielectric film are distributed in the gate length direction to form a gate insulating film, and as the gate length becomes shorter, the distribution ratio of the dielectric film having a higher dielectric constant becomes smaller. Therefore, when the gate length is formed shorter than the design value, the influence of the low dielectric film becomes large and the reduction of the threshold voltage can be suppressed.
When the gate length is longer than the designed value, the low dielectric film occupies a small proportion, so that the increase in the threshold voltage can be suppressed.

[Brief description of drawings]

FIG. 1 is a sectional view showing a first embodiment of the present invention.

FIG. 2 is a characteristic diagram showing the relationship between the gate length and the threshold voltage of the device of the first embodiment of the present invention.

FIG. 3 is a sectional view showing a second embodiment of the present invention.

FIG. 4 is a sectional view showing a third embodiment of the present invention.

FIG. 5 is a cross-sectional view showing an example of a manufacturing process of a conventional device, and a characteristic diagram showing a relationship between a gate length and a threshold voltage.

[Explanation of symbols]

1 Silicon Layer (Semiconductor Layer) 2 Gate Insulating Film 2a High Dielectric Film 2b Low Dielectric Film 3 Gate Electrode 4 Source Layer 5 Drain Layer 16, 18 Transverse Groove 21 Tungsten Film 23 SiO ₂ Film (Dielectric Film) 24 Polycrystalline Silicon Film (semiconductor) 25 Gate electrode 26 Gate insulating film

Claims (3)

[Claims] 1. A gate insulating film (2) on a semiconductor layer (1).
Semiconductor device having a gate electrode (3) formed through the gate electrode and a MOS transistor including a source (4) and a drain (5) formed in the semiconductor layer (1) on both sides of the gate electrode (3) The gate insulating film (2) is formed of a plurality of dielectric films (2a, 2b) having different permittivities distributed in the direction of the gate length, and the dielectric constant having a higher permittivity as the gate length becomes shorter. A semiconductor device, wherein the distribution ratio of the body film (2a) is set small. 2. A first dielectric film (2) on the semiconductor layer (1).
a, 28) to form a gate electrode (3) of a MOS transistor, and a gate length direction of the first dielectric film (2a, 28) under the gate electrode (3). A lateral groove (16, 18) by etching at least one end of the second dielectric film (2b, 29) having a dielectric constant lower than that of the first dielectric film (2a, 28). The lateral groove (16, 1
8) is filled, and the MOS is formed by the first dielectric film (2a, 28) and the second dielectric film (2b, 29).
Forming a gate insulating film of a transistor; forming the source (4) and drain (5) of the MOS transistor in a self-aligned manner on the semiconductor layer (1) using the gate electrode (3) as a mask; A method of manufacturing a semiconductor device, comprising: 3. A step of patterning a first dielectric film (2a) and a first conductive film (21), which are sequentially stacked on a semiconductor layer (1), in a strip shape using the same mask, The second dielectric film having a lower dielectric constant than the first dielectric film (2a) is obtained by oxidizing the semiconductor layer (1) exposed on both sides of the first dielectric film (2a). A step of forming (23), a step of laminating a semiconductor (24) on the entire surface, and a step of anisotropically etching the semiconductor (24) on both side walls of the first conductive film (2a). ) Is left, and the first conductive film (21) and the semiconductor (2
4) forms the gate electrode (25) of the MOS transistor, and the first dielectric film (2a) and the second dielectric film (2) under the gate electrode (25) are formed.
4) forming the gate insulating film (26) of the MOS transistor, and using the gate electrode (25) as a mask to introduce impurities into the semiconductor layer (1) to form the source (26) of the MOS transistor, And a step of forming a drain (26).