JPH05189997A - Memory fault detecting mechanism - Google Patents

Abstract

PURPOSE:To provide a memory fault detecting mechanism capable of detecting invalid write by utilizing parity data. CONSTITUTION:An address when write is performed is monitored by a write area detecting part 7. and the write on a write inhibiting area set in advance is detected. A parity data change part 8 changes the parity data generated at a parity data generating part 5 to an invalid content compulsorily when a detection result in the write area detecting part 7 shows the write on the write inhibiting area, and prevents the matching of the parity data with the data on data memory 3 from being taken place.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory fault detecting mechanism for detecting a fault in a data memory that stores data based on parity data generated when writing data.

[0002]

2. Description of the Related Art In computers, memories such as RAM are generally used as hardware for storing data. A mechanism for detecting a memory failure is provided in order to prevent a failure in this memory and an inaccurate processing result. Specifically, when a failure occurs in a memory, data cannot be written (stored) normally, and a situation occurs in which data differs between writing and reading.

When such a situation occurs, the processing is carried out with reference to data having completely different contents, and the processing result becomes inaccurate. Generally, in order to detect a memory failure, parity data is generated based on the data at the time of writing, and the parity data is stored in correspondence with the data. When reading data, parity data is generated again based on the read data, and this parity data is compared with the previously stored parity data. If they match, the memory is normal and the read data is regarded as valid. Handle it.

On the other hand, if the comparison results do not match, it indicates that the memory has failed, so the read data is treated as invalid. Here, a mechanism for detecting a memory failure using parity data will be referred to as a memory failure detection mechanism.

FIG. 2 shows a block diagram of a conventional memory failure detection mechanism. The figure shows a memory system MS1 having a conventional memory failure detection mechanism. In the figure, a processor (CPU) 1 includes an address bus AB and a control line C.
The memory control unit 2 is connected via. A data memory 3 and a parity data memory 4 are connected to the memory control unit 2 via a memory address line MA and a memory control line MC.

The processor 1 also includes a data bus DB
The parity data generation unit 5, the parity data comparison unit 6, and the data memory 3 are connected via the. The processor 1 is based on the contents of the data memory 3
It controls various processes. Address bus AB
Is a signal line for transmitting an address that specifies an access target of the processor 1.

The control line C is a signal line for transmitting the control signal output from the processor 1. The memory control unit 2
Based on instructions from the processor 1, writing and reading control of the data memory 3 and the parity data memory 4 are performed. The memory control line MC specifies R for specifying an access area on the data memory 3 and the parity data memory 4.
It is a signal line for transmitting the AS and CAS signals and the WE signal for setting the write state.

The memory address line MA is a signal line for transmitting an address that specifies whether the access target is the data memory 3 or the parity data memory 4. The data bus DB is a signal line for writing data in the data memory 3 and transmitting data read from the data memory 3. The parity data generation unit 5 generates parity data indicating whether the number of bits of the content “1” is an even number or an odd number in the bit string of the write data to the data memory 3.

The parity data generator 5 outputs the generated parity data to the parity data memory 4 as parity write data PWD. The parity data comparison unit 6 converts the parity read data PRD indicating the parity data read from the parity data memory 4 into the data read from the data memory 3 and input via the data bus DB similarly to the parity data generation unit 5. The parity data generated based on the comparison is compared, and the parity data error signal PES indicating the comparison result is output to the processor 1.

This parity data error signal PES is
When the signal is used for an interrupt (for example, NMI) to the processor 1 and is set to be valid, the processor 1 holds information such as the address bus AB and the control line C, and interrupts the processing. In the memory system MS1 having the above configuration, the memory failure detection mechanism is constructed by the parity data memory 4, the parity data generation unit 5, and the parity data comparison unit 6.

When writing data to the data memory 3, the processor 1 issues a write address to the address bus AB, a write request to the control line C, and the data bus DB.
Output the data to. The memory control unit 2 analyzes the address on the address bus AB and accesses the memory address line MA and the memory control lines RAS, CAS, and WE.
The data memory 3 receives the access from the memory address line MA and the memory control line MC to write the data on the data bus DB.

On the other hand, the parity data generator 5 receives the data output to the data bus DB, generates parity data based on this data, and outputs it as parity write data to the parity data memory 4. Like the data memory 3, the parity data memory 4 receives access from the memory address line MA and the memory control line MC and writes the parity data. The data in the data memory 3 and the parity data in the parity data memory 4 are stored in a one-to-one correspondence.

When reading data from the data memory 3, the processor 1 outputs a read address on the address AB and a read request on the control line C. The address and the request are analyzed by the memory control unit 2, and the data is read from the data memory 3 based on the analysis result. The read data is recognized by the processor 1 and the parity data comparison unit 6 via the data bus DB.

Similar to the parity data generation unit 5, the parity data comparison unit 6 generates parity data based on the data on the data bus DB. On the other hand, also in the parity data memory 4, like the data memory 3, the memory control unit 2
Parity data is read out based on the analysis result of. The read parity data is output to the parity data comparison unit 6 as parity read data PRD.

The parity data comparison unit 6 compares the previously generated parity data with the parity data read from the parity data memory 4, and if the comparison results are in agreement, the parity data error signal PES is invalidated and does not match. In this case, the parity data error signal PES is set valid. The processor 1 uses the parity data error signal P
If ES is invalid, the subsequent processing is performed assuming that the data read from the data memory 3 and output on the data bus DB is reliable. When the parity data error signal PES is valid, the operation of the processor 1 is interrupted because the data output on the data bus DB is unreliable.

[0016]

By the way, in the storage area of the data memory 3, a certain area may be set as read-only in order to use it for storing universal parameters. When writing is performed in such a read-only area due to a program bug or the like, parity data is also newly generated and stored, so if there is no hardware failure of the data memory 3, it is regarded as valid data. It will be handled. That is, there has been a problem that it is not possible to detect that improper writing has been performed using the parity data. The present invention has been made in view of the above points, and an object thereof is to provide a memory failure detection mechanism capable of detecting an illegal write by using parity data.

[0017]

A memory failure detection mechanism according to the present invention includes a data memory for storing data, a parity data generation unit for generating parity data unique to the data written in the storage area, and A parity data memory that stores the parity data corresponding to the data, and a parity data determination that determines the validity of the data by reading the parity data from the parity data memory at the same time as reading the data from the data memory. Unit, a write area detection unit that detects writing to a preset write protected area of the data memory, and a write area detection unit that writes to the parity data memory when the write area detection unit detects writing to the write protected area. And a parity data changing unit for forcibly changing the parity data Those were.

[0018]

In this mechanism, the write area detection unit monitors the address at the time of writing and detects writing to the preset write prohibited area. The parity data changing unit forcibly changes the parity data generated by the parity data generating unit to invalid contents when the detection result of the write area detecting unit indicates writing to the write prohibited area, and the parity data and the data memory. Do not match the above data.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 is a block diagram of a memory failure detection mechanism of the present invention. The figure shows a memory system MS2 provided with a memory failure detection mechanism of the present invention, which is newly provided with a write area detection section 7 and a parity data change section 8 as compared with the memory system MS1 previously described in FIG. .. Since other configurations are similar to those of the related art, duplicate description will be omitted, and the characteristic part of the present invention will be described.

The input side of the write area detecting section 7 is connected to the address bus AB, and the output side is connected to one input of the parity data changing section 8. Parity data changing unit 8
The output side of the parity data generator 5 is connected to the other input of the. The output side of the parity data changing unit 8 is
It is connected to the parity data memory 4. The write area detection unit 7 is composed of a table provided in a RAM or the like for specifying a write area and a write prohibited area on the data memory 3.

This table is composed of 1-bit data corresponding to each address assigned to the data memory 3, and the content "0" is set in the case of the write area and "1" is set in the case of the write-inhibited area. .. For example, data memory 3
If the storage area specified by the start address of the write area is the write area, the start data of the write area detection unit 7 has the content "0".
Is set, and in the case of the write-protected area, the content “1” is set as the head data.

The parity data changing unit 8 is composed of an exclusive OR circuit.
When the output of the write area detecting unit 7 indicates the content “0”, that is, the write area, the parity data changing unit 8 outputs the output of the parity data generating unit 5 as it is to the parity write data P.
Output as WD. On the other hand, when the output of the write area detection unit 7 indicates the content “1”, that is, the write prohibited area, the output of the parity data generation unit 5 is inverted.

When writing data to the data memory 3, the processor 1 issues a write address to the address bus AB, a write request to the control line C, and the data bus DB.
Output the data to. The memory control unit 2 analyzes the address on the address bus AB and accesses the memory address line MA and the memory control lines RAS, CAS, and WE.
The data memory 3 receives the access from the memory address line MA and the memory control line MC to write the data on the data bus DB.

Upon receipt of the data output to the data bus DB, the parity data generator 5 generates parity data based on this data and outputs it to the parity data changer 8. The write area detecting unit 7 outputs the content of the bit specified by the address on the address bus AB to the parity data changing unit 8.

When the address on the address bus AB is the write area, the output of the write area detecting section 7 is the content "0", so the parity data changing section 8 changes the output content of the parity data generating section 5 to the parity write data. Is output to the parity data memory 4. The parity data memory 4 has the same memory address line MA as the data memory 3.
Also, the parity data is written in response to the access from the memory control line MC.

When the address on the address bus AB is the write prohibited area, the output of the write area detecting unit 7 is the content "1".
Therefore, the parity data changing unit 8 inverts the output content of the parity data generating unit 5, outputs the parity write data PWD to the parity data memory 4, and writes the parity write data PWD to the parity data memory 4.

Next, when reading data from the data memory 3, the processor 1 outputs a read address on the address AB and a read request on the control line C. The address and the request are analyzed by the memory control unit 2, and the data is read from the data memory 3 based on the analysis result. The read data is recognized by the processor 1 and the parity data comparison unit 6 via the data bus DB. Similar to the parity data generation unit 5, the parity data comparison unit 6 generates parity data based on the data on the data bus DB.

On the other hand, also in the parity data memory 4, like the data memory 3, the parity data is read based on the analysis result of the memory control unit 2. The read parity data is output to the parity data comparison unit 6 as parity read data PRD. The parity data comparison unit 6 compares the previously generated parity data with the parity data read from the parity data memory 4, invalidates the parity data error signal PES if the comparison results match, and compares the parity data error signal PES if they do not match. Sets the parity data error signal PES to valid.

If the previously executed write is in the write-prohibited area, the parity data changing unit 8 has changed (inverted) the parity data generated by the parity data generating unit 5, and therefore the parity data comparing unit 6 compares the parity data. Will not match. That is, it is possible to set the parity data error signal to be valid based on the writing to the write protected area instead of the failure of the data memory 3, and the processor 1 treats the data read from the data memory 3 as valid. To avoid. The present invention is not limited to the above embodiments.

By setting whether the output of the write area detecting unit 7 is supplied to the parity data changing unit 8 or not by a switch or the like, the data to the data memory 3 is simply stored without performing the parity data check. Writing and data reading can be realized.

[0031]

As described above, according to the present invention,
The address at the time of writing is monitored, whether this address is a write to the write protected area, that is, whether it is an illegal write or not, and if it is an illegal write, the parity data is forced to the data memory. Change the contents to be inconsistent with the above data. Therefore, when the data is read, since the parity data has a content indicating a failure, the improper writing can be treated as a failure.

[Brief description of drawings]

FIG. 1 is a block diagram of a memory failure detection mechanism of the present invention.

FIG. 2 is a block diagram of a conventional memory failure detection mechanism.

[Explanation of symbols]

 3 data memory 4 parity data memory 5 parity data generation unit 6 parity data comparison unit 7 write area detection unit 8 parity data change unit

Claims (1)

[Claims] 1. A data memory for storing data, a parity data generation unit for generating parity data unique to the data to be written in the storage area, and parity data for storing the parity data corresponding to the data. A memory and reading the data from the data memory,
A parity data determination unit that reads the parity data from the parity data memory and determines the validity of the data; a write area detection unit that detects writing to a preset write prohibited area of the data memory; A memory failure, comprising: a parity data changing unit for forcibly changing the parity data to be written in the parity data memory to invalid contents when the area detecting unit detects writing to the write prohibited area. Detection mechanism.