JPH05190767A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH05190767A JPH05190767A JP2451292A JP2451292A JPH05190767A JP H05190767 A JPH05190767 A JP H05190767A JP 2451292 A JP2451292 A JP 2451292A JP 2451292 A JP2451292 A JP 2451292A JP H05190767 A JPH05190767 A JP H05190767A
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- film
- electrode
- polysilicon film
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 239000003990 capacitor Substances 0.000 abstract description 33
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 18
- 229920005591 polysilicon Polymers 0.000 abstract description 18
- 229910052751 metal Inorganic materials 0.000 abstract description 10
- 239000002184 metal Substances 0.000 abstract description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 9
- 229910052710 silicon Inorganic materials 0.000 abstract description 9
- 239000010703 silicon Substances 0.000 abstract description 9
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 9
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 8
- 230000003071 parasitic effect Effects 0.000 abstract description 6
- 238000000059 patterning Methods 0.000 abstract description 4
- 239000010408 film Substances 0.000 description 51
- 239000012535 impurity Substances 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 5
- 239000010410 layer Substances 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910052451 lead zirconate titanate Inorganic materials 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229910018125 Al-Si Inorganic materials 0.000 description 1
- 229910018520 Al—Si Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- HFGPZNIAWCZYJU-UHFFFAOYSA-N lead zirconate titanate Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ti+4].[Zr+4].[Pb+2] HFGPZNIAWCZYJU-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置に係り、特
に、半導体集積回路に用いられるキャパシタの構造に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to the structure of a capacitor used in a semiconductor integrated circuit.
【０００２】[0002]
【従来の技術】従来の一般的なキャパシタの構造を図４
に示す。シリコン基板１にキャパシタの第１の電極とし
ての不純物拡散層２が形成されている。この不純物拡散
層２の上に、キャパシタの容量絶縁膜としてのシリコン
窒化膜（Ｓｉ3 Ｎ4 ）３と、第２の電極としてのアルミ
ニウム配線４が積層形成されている。なお、図中の符号
５はシリコン酸化膜、６はシリコン酸化膜５に形成され
たコンタクトホールを介して、不純物拡散層２に接続す
るアルミニウム配線である。2. Description of the Related Art The structure of a conventional general capacitor is shown in FIG.
Shown in. An impurity diffusion layer 2 as a first electrode of a capacitor is formed on a silicon substrate 1. On this impurity diffusion layer 2, a silicon nitride film (Si 3 N 4 ) 3 as a capacitance insulating film of a capacitor and an aluminum wiring 4 as a second electrode are laminated. In the drawing, reference numeral 5 is a silicon oxide film, and 6 is an aluminum wiring connected to the impurity diffusion layer 2 through a contact hole formed in the silicon oxide film 5.
【０００３】周知のようにキャパシタの容量は、電極面
積に比例するとともに、容量絶縁膜の厚みに反比例す
る。キャパシタの占有面積を増やすことなく大容量のキ
ャパシタを実現しようとした場合、上述したキャパシタ
構造によれば、容量絶縁膜の厚みを薄くする必要かあ
る。しかし、容量絶縁膜の厚みを余り薄くすると、絶縁
耐圧が低下するので、容量絶縁膜の厚みを薄くするにも
限界がある。そのため、上述したキャパシタ構造で大容
量のキャパシタを得ようとすると、必然的に電極面積を
多くしなければならず、半導体装置の高集積化の妨げに
なっていた。As is well known, the capacitance of a capacitor is proportional to the electrode area and inversely proportional to the thickness of the capacitive insulating film. In order to realize a large-capacity capacitor without increasing the occupied area of the capacitor, it is necessary to reduce the thickness of the capacitive insulating film according to the above-mentioned capacitor structure. However, if the thickness of the capacitance insulating film is too thin, the withstand voltage will be lowered, so there is a limit to reducing the thickness of the capacitance insulating film. Therefore, in order to obtain a large-capacity capacitor with the above-mentioned capacitor structure, the electrode area must be increased inevitably, which hinders high integration of the semiconductor device.
【０００４】そこで、キャパシタの占有面積を増加する
ことなく、電極面積を大きくできるキャパシタ構造とし
て、図５に示すようなものが提案されている（特開平３
−２４７５６号公報参照）。このキャパシタは、不純物
拡散層２の上にパターンニングされた導電性のポリシリ
コン膜７を形成し、このポリシリコン膜７の上にシリコ
ン窒化膜３とアルミニウム配線４とを積層形成してい
る。このキャパシタによれば、パターンニングされたポ
リシリコン膜７の側面の面積によって、キャパシタの電
極面積が増加するので、キャパシタの占有面積を拡げる
ことなく、大容量のキャパシタを実現することができ
る。Therefore, as a capacitor structure capable of increasing the electrode area without increasing the occupied area of the capacitor, a capacitor structure as shown in FIG.
-24756). In this capacitor, a patterned conductive polysilicon film 7 is formed on the impurity diffusion layer 2, and a silicon nitride film 3 and an aluminum wiring 4 are laminated on the polysilicon film 7. According to this capacitor, the area of the side surface of the patterned polysilicon film 7 increases the electrode area of the capacitor, so that a large-capacity capacitor can be realized without expanding the area occupied by the capacitor.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、このよ
うな構成を有する従来例の場合には、次のような問題が
ある。すなわち、図４および図５に示したキャパシタは
いずれも、第１の電極として不純物拡散層２を用いてい
るので、シリコン基板１の寄生容量の影響を受けやす
く、設計値通りの容量値を得難いという問題点がある。However, the conventional example having such a structure has the following problems. That is, since the impurity diffusion layer 2 is used as the first electrode in each of the capacitors shown in FIGS. 4 and 5, it is easily affected by the parasitic capacitance of the silicon substrate 1 and it is difficult to obtain the capacitance value as designed. There is a problem.
【０００６】本発明は、このような事情に鑑みてなされ
たものであって、キャパシタの占有面積を増大すること
なく大容量のキャパシタを実現でき、しかも基板の寄生
容量の影響を受け難いキャパシタ構造をもった半導体装
置を提供することを目的としている。The present invention has been made in view of the above circumstances, and it is possible to realize a large-capacity capacitor without increasing the occupied area of the capacitor, and the capacitor structure is not easily affected by the parasitic capacitance of the substrate. It is an object of the present invention to provide a semiconductor device having the above.
【０００７】[0007]
【課題を解決するための手段】本発明は、このような目
的を達成するために、次のような構成をとる。すなわ
ち、本発明に係る半導体装置は、半導体基板上に絶縁膜
を介して形成され、その表面部分がパターンニングされ
た第１の電極と、前記第１の電極上に形成された容量絶
縁膜と、前記容量絶縁膜の上に形成された第２の電極
と、を備えたものである。The present invention has the following constitution in order to achieve such an object. That is, a semiconductor device according to the present invention includes a first electrode formed on a semiconductor substrate via an insulating film and having a surface portion patterned, and a capacitive insulating film formed on the first electrode. And a second electrode formed on the capacitance insulating film.
【０００８】[0008]
【作用】本発明によれば、第１の電極の表面部分がパタ
ーンニングされて段差構造になっているので、段差部の
側面部の面積の分だけキャパシタの電極面積が増大し、
キャパシタの素子占有面積を大きくすることなく、大容
量のキャパシタが実現される。しかも、第１の電極と半
導体基板との間には、絶縁膜が介在しているので、半導
体基板の寄生容量の影響を受けることもない。According to the present invention, since the surface portion of the first electrode is patterned to form a step structure, the electrode area of the capacitor is increased by the area of the side surface of the step portion.
A large-capacity capacitor can be realized without increasing the element occupying area of the capacitor. Moreover, since the insulating film is interposed between the first electrode and the semiconductor substrate, it is not affected by the parasitic capacitance of the semiconductor substrate.
【０００９】[0009]
【実施例】以下、図面を参照して本発明の一実施例を説
明する。図１は本発明に係る半導体装置の一実施例の概
略構成を示した断面図である。図中、符号１１はシリコ
ン基板であり、このシリコン基板１１の上に絶縁膜とし
ての例えば、シリコン酸化膜１２が形成されている。シ
リコン酸化膜１２の上に第１の電極としての導電性のポ
リシリコン膜１３が堆積されている。このポリシリコン
膜１３の表面部分は、溝状にパターンニングされてい
る。パターンニングの形状は特に限定しないが、例えば
図２の（ａ）に示すように、格子状の溝構造のものや、
（ｂ）に示すようにストライプ状の溝構造のものがあ
る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing a schematic configuration of one embodiment of a semiconductor device according to the present invention. In the figure, reference numeral 11 is a silicon substrate, and, for example, a silicon oxide film 12 as an insulating film is formed on the silicon substrate 11. A conductive polysilicon film 13 as a first electrode is deposited on the silicon oxide film 12. The surface portion of the polysilicon film 13 is patterned into a groove shape. Although the patterning shape is not particularly limited, for example, as shown in FIG.
As shown in (b), there is a stripe groove structure.
【００１０】パターンニングされたポリシリコン膜１３
の上に、容量絶縁膜としてのシリコン窒化膜１４が堆積
されている。容量絶縁膜としては、この他にシリコン酸
化膜のような絶縁膜や、チタン酸ジルコン酸鉛（ＰＺ
Ｔ）のような強誘電体物質を用いることもできる。容量
絶縁膜としてＰＺＴのような強誘電体物質を用いる場合
には、強誘電体物質の結晶配向性を良くするために、ポ
リシリコン膜１３との間に白金等の金属薄膜を介在させ
るのが好ましい。Patterned polysilicon film 13
A silicon nitride film 14 as a capacitance insulating film is deposited on the above. In addition to this, as a capacitive insulating film, an insulating film such as a silicon oxide film, lead zirconate titanate (PZ
Ferroelectric materials such as T) can also be used. When a ferroelectric substance such as PZT is used for the capacitive insulating film, a metal thin film such as platinum is interposed between the ferroelectric substance and the polysilicon film 13 in order to improve the crystal orientation of the ferroelectric substance. preferable.
【００１１】シリコン窒化膜１４の上に燐ガラス等の層
間絶縁膜１５が堆積され、この層間絶縁膜１５に形成さ
れた各コンタクトホールを介して、Ａｌ−Ｓｉ等からな
る金属配線１６がシリコン窒化膜１４の上に形成され、
また金属配線１７がポリシリコン膜１３に接続してい
る。An interlayer insulating film 15 such as phosphor glass is deposited on the silicon nitride film 14, and metal wiring 16 made of Al--Si or the like is silicon nitrided through each contact hole formed in the interlayer insulating film 15. Formed on the membrane 14,
The metal wiring 17 is connected to the polysilicon film 13.
【００１２】以下、図３を参照して上述した半導体装置
の製造方法を説明する。図３の（ａ）に示すように、シ
リコン基板１１の表面に熱酸化法によりシリコン酸化膜
１２を形成した後、燐等の不純物をドープした導電性の
ポリシリコン膜１３をＣＶＤ（Chemical Vapor Deposit
ion)法で堆積し、フォトエッチング法により所要の形状
にパターンニングする。A method of manufacturing the above-mentioned semiconductor device will be described below with reference to FIG. As shown in FIG. 3A, after a silicon oxide film 12 is formed on the surface of a silicon substrate 11 by a thermal oxidation method, a conductive polysilicon film 13 doped with impurities such as phosphorus is formed by CVD (Chemical Vapor Deposit).
ion) method, and patterning into a desired shape by photo-etching method.
【００１３】図３の（ｂ）に示すように、ポリシリコン
膜１３をフォトレジストで例えばストライプ状にマスキ
ングし、反応性イオンエッチング（ＲＩＥ）法により、
ポリシリコン膜１３の表面部分をパターンニングして段
差構造を形成する。As shown in FIG. 3B, the polysilicon film 13 is masked with a photoresist in a stripe shape, for example, and then reactive ion etching (RIE) is performed.
The surface portion of the polysilicon film 13 is patterned to form a step structure.
【００１４】図３の（ｃ）に示すように、フォトレジス
トを除去した後、ＣＶＤ法によりシリコン窒化膜１４を
堆積する。キャパシタの容量を増大する上で、シリコン
窒化膜１４は、絶縁耐圧が劣化しない範囲で、出来るだ
け薄く形成するのが好ましい。ここでは、１０００オン
グストローム程度の膜厚に設定されている。As shown in FIG. 3C, after removing the photoresist, a silicon nitride film 14 is deposited by the CVD method. In order to increase the capacitance of the capacitor, it is preferable that the silicon nitride film 14 be formed as thin as possible within the range where the withstand voltage does not deteriorate. Here, the film thickness is set to about 1000 Å.
【００１５】図３の（ｄ）に示すように、燐ガラス等の
層間絶縁膜１５をＣＶＤ法で堆積した後、層間絶縁膜１
５にコンタクトホールを形成し、続いてＡｌ−Ｓｉ等の
金属膜をスパッタリング法により被着し、この金属膜を
パターンニングして金属配線１６および１７を形成す
る。As shown in FIG. 3D, after the interlayer insulating film 15 such as phosphor glass is deposited by the CVD method, the interlayer insulating film 1 is formed.
5, a contact hole is formed, subsequently a metal film of Al—Si or the like is deposited by a sputtering method, and the metal film is patterned to form metal wirings 16 and 17.
【００１６】[0016]
【発明の効果】以上の説明から明らかなように、本発明
によれば、第１の電極の表面部分がパターンニングされ
て段差構造になっているので、段差部の側面部の面積の
分だけキャパシタの電極面積が増大し、キャパシタの素
子占有面積を大きくすることなく、大容量のキャパシタ
を実現することができる。しかも、第１の電極と半導体
基板との間には、絶縁膜が介在しているので、半導体基
板の寄生容量の影響を受けることがなく、設計値通りの
容量値をもったキャパシタを容易に実現することができ
る。As is apparent from the above description, according to the present invention, since the surface portion of the first electrode is patterned to form the step structure, only the area of the side surface portion of the step portion is formed. A large-capacity capacitor can be realized without increasing the electrode area of the capacitor and increasing the element occupying area of the capacitor. Moreover, since the insulating film is interposed between the first electrode and the semiconductor substrate, the capacitor having the capacitance value as designed can be easily obtained without being affected by the parasitic capacitance of the semiconductor substrate. Can be realized.
【図１】本発明に係る半導体装置の一実施例の構成を示
した断面図である。FIG. 1 is a sectional view showing a configuration of an embodiment of a semiconductor device according to the present invention.
【図２】第１の電極のパターンニング形状の例を示した
平面図である。FIG. 2 is a plan view showing an example of a patterning shape of a first electrode.
【図３】実施例装置の製造方法の説明図である。FIG. 3 is an explanatory diagram of a method for manufacturing the device according to the embodiment.
【図４】従来の半導体装置の構成を示した断面図であ
る。FIG. 4 is a sectional view showing a configuration of a conventional semiconductor device.
【図５】電極面積の増大を図った従来の半導体装置の構
成を示した断面図である。FIG. 5 is a sectional view showing a configuration of a conventional semiconductor device in which an electrode area is increased.
１１…シリコン基板 １２…シリコン酸化膜（絶縁膜） １３…ポリシリコン膜（第１の電極） １４…シリコン窒化膜（容量絶縁膜） １５…層間絶縁膜 １６…金属配線（第２の電極） １７…金属配線 11 ... Silicon substrate 12 ... Silicon oxide film (insulating film) 13 ... Polysilicon film (first electrode) 14 ... Silicon nitride film (capacitance insulating film) 15 ... Interlayer insulating film 16 ... Metal wiring (second electrode) 17 … Metal wiring
Claims (1)
れ、その表面部分がパターンニングされた第１の電極
と、 前記第１の電極上に形成された容量絶縁膜と、 前記容量絶縁膜の上に形成された第２の電極と、 を備えたことを特徴とする半導体装置。1. A first electrode formed on a semiconductor substrate via an insulating film, the surface portion of which is patterned, a capacitive insulating film formed on the first electrode, and the capacitive insulating film. And a second electrode formed on the semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2451292A JPH05190767A (en) | 1992-01-14 | 1992-01-14 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2451292A JPH05190767A (en) | 1992-01-14 | 1992-01-14 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05190767A true JPH05190767A (en) | 1993-07-30 |
Family
ID=12140229
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2451292A Pending JPH05190767A (en) | 1992-01-14 | 1992-01-14 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05190767A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0870034A (en) * | 1994-05-18 | 1996-03-12 | Applied Materials Inc | Patterned susceptor to reduce electrostatic forces |
| KR20010068729A (en) * | 2000-01-08 | 2001-07-23 | 박종섭 | Manufacturing method for capacitor |
| CN111969111A (en) * | 2020-08-26 | 2020-11-20 | 上海华虹宏力半导体制造有限公司 | Capacitor and manufacturing method thereof |
| CN113270547A (en) * | 2021-05-19 | 2021-08-17 | 上海华虹宏力半导体制造有限公司 | PIP capacitor and manufacturing method thereof |
-
1992
- 1992-01-14 JP JP2451292A patent/JPH05190767A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0870034A (en) * | 1994-05-18 | 1996-03-12 | Applied Materials Inc | Patterned susceptor to reduce electrostatic forces |
| KR20010068729A (en) * | 2000-01-08 | 2001-07-23 | 박종섭 | Manufacturing method for capacitor |
| CN111969111A (en) * | 2020-08-26 | 2020-11-20 | 上海华虹宏力半导体制造有限公司 | Capacitor and manufacturing method thereof |
| CN111969111B (en) * | 2020-08-26 | 2023-04-18 | 上海华虹宏力半导体制造有限公司 | Capacitor and manufacturing method thereof |
| CN113270547A (en) * | 2021-05-19 | 2021-08-17 | 上海华虹宏力半导体制造有限公司 | PIP capacitor and manufacturing method thereof |
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