JPH05190825A - Solid-state image sensor - Google Patents

Abstract

(57) [Summary] [Structure] A diffusion layer is formed using a doped film doped with a dopant as a diffusion source. [Effect] The high-concentration p-type diffusion layer on the photodiode surface
By forming the depth shallower to 0.1 μm or less, it is possible to prevent a decrease in sensitivity (especially, a decrease in blue sensitivity), suppress dark current, and read out charges.

Description

Detailed Description of the Invention

[0001]

[Industrial application] Solid-state image sensor

[0002]

2. Description of the Related Art FIG. 2 shows an example of a cross-sectional structure of a conventional interline CCD image pickup device, which has a fully embedded photodiode in which surface dark current is completely suppressed.
It is a CCD image sensor. As a method of manufacturing this element,
For example, 2 p-type well diffusion layers are formed in 1 Si substrate. Next, the gate oxide film 3 is formed and the gate electrode 4 is formed. Then, using the gate electrode 4 as a mask, only the gate oxide film between the gate electrodes is removed, and the interlayer oxide film 5 and the gate oxide film 3'on the gate electrode 4 are formed again.
Next, the photodiode n-type diffusion layer 6 is formed in the well diffusion layer, and the p-type diffusion layer 7 is formed on the surface of the photodiode 7.

In the prior art, the p-type diffusion layer 7 is formed by the ion implantation method. When ion implantation is used, ion implantation is performed through the thermal oxide film 3 of silicon for the purpose of preventing contamination and crystal defects. In the ion implantation method, in consideration of variations in diffusion layer resistance, after implanting 90% or more of ions into the Si substrate, it is necessary to perform heat treatment to activate the ions and recover the ion implantation damage. To 0.1 μm
It was quite difficult to do the following. The following points due to this deep p-type diffusion layer 7 were not considered.

(1) Sensitivity decrease (especially, blue sensitivity decrease) due to disappearance of photoelectrically converted charges in the deep p-type diffusion layer 7 at a certain lifetime. (2) Dark current (diffuse component) charges generated in the deep p-type diffusion layer 7 cause white spots on the device. (3) The lateral extension of the deep p-type diffusion layer 7 hinders the reading of charges from the buried photodiode.

As a prior art related to the present invention, Japanese Patent Application No. 2-313989 can be cited.

[0006]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
To deal with the problems listed in (1), (2), and (3).
That is, at a high impurity concentration (10 ¹⁷ atoms / cm ³ or more), 0.1
The problem is how to form a shallow p-type diffusion layer of μm or less without giving crystal defects due to ion implantation damage. If this is taken as a countermeasure, the fully-embedded photodiode suppresses the surface dark current and the dark current of (2),
(3) can be improved.

[0007]

[Means for Solving the Problems] High impurity concentration (10 ¹⁷ at
As a means for realizing a shallow p-type diffusion layer having a thickness of 0.1 μm or less at oms / cm ³ or more), a method of forming a diffusion layer using a doped film doped with a dopant as a diffusion source was invented. The following materials and forming methods are used as the forming method of the doped film.

(A) A doped silicon (amorphous and polycrystalline) film is formed by atmospheric pressure and low pressure CVD (chemical vapor deposition) method, sputtering method. (b) A doped oxide film is formed by the CVD method, coating method, and sputtering method.

When the doped silicon film is effectively used as a transparent electrode, it may be used with a thickness of 50 nm or less.

[0010]

[Function] By implementing a shallow diffusion layer of 0.1 μm or less, the problems (1), (2) and (3) can be solved.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a sectional view of a pixel of a CCD image pickup device according to a first embodiment of the present invention. The manufacturing method is the same as in Conventional Example 1 of FIG.
First, the p-well diffusion layer 2, the gate oxide film 3, the gate electrode 4, and the photodiode n-type diffusion layer 6 are formed. Next, using the interlayer oxide film 5 on the gate electrode as a mask, the gate oxide film 3 on the photodiode is removed by dry etching or wet etching, and a doped silicon film or boron (B) doped with boron (B). A silicon oxide film 8 doped with is deposited. Then 950
A p-type diffusion layer 7 is formed by diffusion by using heat treatment at a temperature of ≦ ° C. or instantaneous annealing at a temperature of 1200 ° C. or laser annealing. By forming the p-type diffusion layer 7 doped film 8 as a diffusion source, there is no possibility of causing crystal defects due to the ion implantation damage, enables low temperature and short of diffusion time of diffusion temperature, 10 ¹⁷ (atoms / cm ³⁾
It is possible to form the high-concentration p-type diffusion layer 7 as shallow as 0.1 μm or less.

FIG. 3 shows an example of a pixel section of the CCD image pickup device of the second embodiment. In the manufacturing method, the shallow p-type diffusion layer 7 is formed as in the first embodiment shown in FIG. Next, the doped silicon film is oxidized at a temperature of 900 ° C. or lower to change the doped silicon film into the silicon oxide film 9. By changing to the silicon oxide film 9, it can be changed to a film transparent to visible light regardless of the film thickness of the doped silicon film. At this time, the diffusion process from the doped silicon film can also serve as an oxidation process for changing to the silicon oxide film 9.

FIG. 4 shows an example of a pixel section of the CCD image pickup device of the third embodiment. The manufacturing method was the same as in Example 1 of FIG. 1, after forming a doped silicon film doped with boron (B), heat treatment was performed at a temperature (800 ° C. or less) at which the influence of diffusion can be almost ignored, and the silicon substrate was contacted. The portion 10 is a single crystal. Since the heat treatment is performed at a temperature at which the influence of diffusion can be almost ignored, the p-type diffusion layer (here, 10) can be formed in the silicon substrate with almost no diffusion layer formed.

FIG. 5 shows a second conventional example (Japanese Patent Laid-Open No. 62-206878).
No.). After forming the photodiode 6 and the p-type diffusion layer 7 as in the conventional example of FIG.
2 is formed and electrically connected to the p-type diffusion layer 7. The transparent electrode 12 suppresses shading of signal charges due to potential fluctuations in the large-area p-type well diffusion layer 2. This is because the p-type diffusion layer 7 electrically connected to the p-type well diffusion layer 2 is connected by a transparent electrode, and the p-type well diffusion layer resistance can be effectively reduced.

FIG. 6C of Example 4 in which this measure is taken.
An example of a CD image sensor pixel cross section is shown. In the manufacturing method, the p-type diffusion layer 7 is formed in the photodiode 6 using the doped silicon film 8 as a diffusion source, as in the first embodiment shown in FIG. In the present Example 4, instead of the transparent electrode 12 of the conventional example 2 (FIG. 5), a doped silicon film 8 was used, and the diffusion source of the p-type diffusion layer 7
The feature is that it also serves as a well electrode. To use the doped silicon film 8 as a transparent electrode, the film thickness of the doped silicon film may be set to 50 nm or less so that absorption of blue light (about 500 nm) can be prevented.

FIG. 7 shows an example of a pixel cross section of the CCD image pickup device of the fifth embodiment. In the manufacturing method, the p-type diffusion layer 7 is formed in the photodiode 6 using the doped silicon film 8 as a diffusion source, as in the first embodiment shown in FIG. In Example 5, p
The p-type diffusion layer 7 is formed independently, and the p-type diffusion layer 7 is formed as a clamp diode for sweeping excess charges of the photodiode.
Is also used as a p-type diffusion layer diffusion source.

In the above-mentioned first embodiment, second embodiment, third embodiment, fourth embodiment and fifth embodiment, an example of a film doped with boron (B) as the doped silicon film is shown.
It can be similarly formed by doping impurities such as (P), arsenic (As), antimony (Sb), gallium (Ga), and aluminum (Al).

FIG. 8 shows a third conventional example (JP-A-2-224480). This conventional example shows an example of a cross-sectional view of a MOS type image pickup device, which is a p-type photodiode diffusion layer 21, a p-type reset gate diffusion layer 22, an n-type diffusion layer 23, and an n-substrate 25. Composed of these,
The problem is to reduce the drain conductance of the J-FET. To prevent this, the n-type diffusion layer 23
Should be formed as shallow as possible. This can be dealt with by the embodiment of the present invention.

FIG. 9 shows an example of a pixel cross section of the MOS type image pickup device of the sixth embodiment. The n-type diffusion layer 26 is shallowly formed by using the doped silicon film 24 as a diffusion source, and the surface of the photodiode 21 is simultaneously filled with the n-type diffusion layer. According to the sixth embodiment, it is possible to reduce the drain conductance of the J-FET and at the same time suppress the photodiode dark current.

[0020]

The following effects can be exhibited by forming the high-concentration p-type diffusion layer on the surface of the photodiode to be shallow to 0.1 μm or less. (1) Since the p-type diffusion layer 7 is shallow, it is possible to prevent a decrease in sensitivity (particularly a decrease in blue sensitivity) due to the disappearance of photoelectrically converted charges in the p-type diffusion layer at a certain lifetime. (2) Since the p-type diffusion layer 7 is shallow, it occurs in the p-type diffusion layer,
Dark current (diffuse component) that causes white spots on the device
Can be suppressed. (3) Because of the shallow p-type diffusion layer 7, the lateral spread is small,
Readout of charges from the embedded photodiode is facilitated.

Further, by using it as a transparent electrode,
It is possible to suppress well potential fluctuations and suppress excess charges in the photodiode. Further, when applied to a MOS type image pickup device, the drain conductance of the J-FET can be reduced and at the same time the photodiode dark current can be suppressed.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a photodiode surface dark current suppressing structure according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a conventional example of a photodiode surface dark current suppressing structure.

FIG. 3 is a sectional view of a second embodiment of the present invention of a photodiode surface dark current suppressing structure.

FIG. 4 is a sectional view of a photodiode surface dark current suppressing structure according to a third embodiment of the present invention.

FIG. 5 is a cross-sectional view of a conventional example using a transparent electrode as a well electrode.

FIG. 6 is a cross-sectional view of a fourth embodiment of the present invention which also serves as a well electrode and a dark current suppressing diffusion layer.

FIG. 7 is a cross-sectional view of a fifth embodiment of the present invention which also serves as a dark current suppressing structure and an excess charge suppressing electrode.

FIG. 8 is a sectional view of a conventional example of a MOS type image pickup device.

FIG. 9 is a sectional view of a sixth embodiment of the present invention when applied to a MOS type image pickup device.

[Explanation of symbols]

3 ... Gate oxide film, 4 ... Gate electrode, 6 ... Photodiode, 7 ... P-type diffusion layer, 8 ... Doped silicon film.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Hideyuki Ono 1-280 Higashi Koikeku, Kokubunji, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (72) Haruhiko Tanaka 1-280 Higashi Koikeku, Kokubunji, Tokyo Hitachi Ltd. Central research institute

Claims (7)

[Claims] 1. A photoelectric conversion element having two-dimensionally arranged photoelectric conversion elements on a semiconductor substrate and a means for reading out charges accumulated in the photoelectric conversion element, wherein the photoelectric conversion element is on the semiconductor substrate of the first conductivity type. A solid-state imaging device comprising a first conductivity type reverse conductivity type first impurity layer, a first conductivity type second impurity layer, and a reverse conductivity type third impurity layer formed on the surface of the base. Is formed by a manufacturing method using a doped silicon or a doped silicon oxide film capable of being deposited at 600 ° C. or lower as a diffusion source. 2. The method according to claim 1, wherein the third impurity layer is doped polysilicon and the silicon oxide film is a diffusion source.
A solid-state imaging device formed by a manufacturing method in which heat treatment at 50 ° C. or lower, instantaneous annealing at 1200 ° C. or lower, and laser annealing are performed. 3. The solid-state imaging device according to claim 1, wherein the thickness of the doped polysilicon for forming the third impurity layer is 50 nm or less in order to prevent absorption of blue light (about 500 nm). 4. The solid-state imaging device according to claim 1, wherein the doped polysilicon film serving as a diffusion source for forming the third impurity layer is also used as a gate electrode of a charge reading means. 5. The method according to claim 1, 2 or 3, wherein the potential of the doped polysilicon film serving as a diffusion source for forming the third impurity layer is suppressed so as to suppress the potential fluctuation of the first impurity layer. A solid-state image sensor having the same potential as the first impurity layer. 6. The method according to claim 1, 2 or 3, wherein a doped polysilicon film serving as a diffusion source for forming the third impurity layer is made independent in the photodiode to sweep out excess charges generated in the photodiode. Solid-state image sensor that uses as an electrode. 7. The method according to claim 1, wherein a doped polysilicon film serving as a diffusion source for forming the third impurity layer is formed at a temperature of 900 ° C. or lower at the same time as or after the formation of the third impurity layer. A solid-state image sensor formed by a manufacturing method in which the doped polysilicon film is changed into an oxide film which is a film transparent to visible light by a thermal oxidation step at the temperature of.