JPH05190856A - Semiconductor device and manufacture thereof - Google Patents

Abstract

(57) [Abstract] [Purpose] The present invention provides a thin TFT channel portion and a TFT.
A source / drain portion and a source / drain / offset can be formed in a self-aligned manner with respect to a gate electrode, and a highly reliable lower gate structure TFT transistor with less variation in characteristics can be provided. .. [Configuration] In a TFT transistor having a lower gate structure,
The channel portion is formed thinner than the source / drain portion, the source / drain is formed in self alignment with the gate electrode, and the offset is formed in self alignment. And

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
It relates to the structure of an FT transistor.

[0002]

2. Description of the Related Art At present, one of the characteristics of SRAM widely used in the field of memory is a low standby current which enables battery backup. Conventional SRAM
However, by using a high resistance load type cell and increasing the resistance value of the polysilicon that is the load, the standby current has been kept low. However, if a standby current of 4MSRAM is required to be about the same as that of 1MSRAM, the standby current per cell needs to be reduced to 1/4. Or, since it becomes less than that, it becomes difficult to retain information, and the data retention characteristic deteriorates.

Therefore, a cell that has a low standby current and a sufficient data retention characteristic even when highly integrated has appeared.
This is called a pMOS load type cell. This is a pMOS transistor serving as a load stacked on an nMOS transistor, and has an advantage that higher integration can be achieved as compared with the complete cMOS type.

This pMOS transistor is a TFT in which a source / drain / channel portion is formed of a thin film silicon layer.
It has a (Thin Film Transistor) structure. Further, in SRAMs, a structure called a lower gate structure in which a gate electrode is located below is widely used due to restrictions in memory cell design.

A method of manufacturing the TFT transistor having the lower gate structure will be described with reference to FIG. First, the semiconductor substrate 2
A silicon oxide film 202 is formed at 01 by a CVD method (FIG. 2A), a polysilicon film is formed by a CVD method, impurities are introduced, and then a gate electrode 203 is formed by etching using a positive resist by photolithography. .. (FIG. 2B) Next, after forming a gate oxide film 204 by a CVD method or an oxidation method, a polysilicon film 205 is formed by a CVD method or the like (FIG. 2C), and impurities are ion-implanted using a resist as a mask. Source / drain section 20
6 is formed. (FIG. 2 (d)) At this time, 207 not doped with impurities becomes a channel portion. Finally, after forming a silicon oxide film 208 on the entire surface, a contact hole is formed by wet etching with hydrofluoric acid or hydrofluoric acid and ammonium fluoride to form an aluminum wiring 209.
(Fig. 2 (e))

[0006]

By the way, this TFT
When using as a memory cell of SRAM, first, TFT
There is a reduction in off current as a characteristic required for the above. This directly affects the standby current of the SRAM described above.
As one method of reducing the off current, it is very effective to reduce the film thickness of the channel portion of the TFT.

On the other hand, when the bulk portion (source / drain / channel portion) of the TFT is used as a wiring, a required characteristic is reduction of sheet resistance. The resistance of this wiring part affects the speed of the circuit. In order to secure the sheet resistance that can be used as the wiring, there is a method of increasing the impurity concentration, but a certain thickness is required.
Further, when the source / drain portions are thin, the contact holes when connecting the wiring layers cannot be directly dry-etched, so the lower-layer wiring is used or the wet etching as described in the description of FIG. 4 is performed. I was taking means.

As described above, it is ideal that the channel portion of the TFT is thin and the source / drain portion of the TFT is thick.
Since the channel portions are formed at the same time, the film thickness will be the same.

Further, in the conventional technique, the distance to the source / drain portion of the TFT and the offset length are conventionally varied depending on the photo precision and the alignment precision, and as a result,
The TFT characteristics also varied.

Therefore, the present invention solves these problems, and an object of the present invention is to provide a lower gate structure TFT transistor capable of forming a thin TFT channel portion and a thick TFT source / drain portion. ..

Further, the source / drain portion and the offset can be formed in a self-aligned manner with respect to the gate electrode, and there is provided a lower gate structure TFT transistor with less variation.

[0012]

The semiconductor device of the present invention comprises:
In the TFT transistor having the lower gate structure, the channel portion is thin and the source / drain portions are thick.

In the method for manufacturing a semiconductor device of the present invention, in a TFT transistor having a lower gate structure, a step of forming a first insulating film on a semiconductor substrate, and after forming the first semiconductor film on the first insulating film, Patterning step, forming a second insulating film on the patterned first semiconductor film, and then performing desired patterning, forming a first semiconductor film on the patterned first semiconductor film and second insulating film And a step of performing heat treatment.

Further, it is characterized in that a laser annealing process is performed in the heat treatment process.

[0015]

EXAMPLES The present invention will now be described in detail based on examples.

FIG. 1 is a diagram showing an embodiment of the present invention in the order of steps.

First, a silicon oxide film 102 of 100 to 1 is formed on the entire surface of the semiconductor substrate 101 by a CVD method or thermal oxidation.
After forming 000 nm, a polysilicon film 103 is formed in 20 to 300 nm by LPCVD at 600 to 640 ° C. in a monosilane atmosphere. Subsequently, BF ₂ ⁺ or B ⁺ which is a P-type impurity, or P ⁺ or As ⁺ which is an N-type impurity is dosed at 1 × 10 ¹⁴ to 1 × on the entire surface of the polysilicon film.
After introducing impurities by ion implantation or thermal diffusion at 10 ¹⁶ and energy of 30 to 120 kev, patterning is performed by photolithography and etching. (Fig. 1
(A) Next, a silicon oxide film 104 having a thickness of 10 to 100 nm is formed on the entire surface by thermal oxidation or a CVD method, and then patterned by photolithography and etching. (FIG. 1B) Subsequently, the polysilicon film 103 is formed at a temperature of 600 to 640 ° C. in a monosilane atmosphere by LPCVD.
-300 nm is formed. (FIG. 1C) After that, thermal annealing (700 to 1000 ° C., 30 minutes to 1 hour) or lamp annealing (900 to 1100 ° C., 10 seconds to 30 seconds)
Alternatively, the polysilicon film 103 is formed by laser annealing.
Impurities are diffused into a part of the polysilicon film 105, and TF
A source / drain portion of T is formed. (FIG. 1D) Further, a polysilicon oxide film 106 is formed, a contact is opened by wet or dry etching, and then an aluminum wiring 107 is connected. (FIG. 1E) According to the semiconductor device manufactured by the above process, since the channel portion can be formed thin, the depletion layer spreads over the entire polysilicon portion of the channel portion and the mobility is increased, so that the transistor characteristics are improved. To do.

Further, since the source / drain portions can be formed thick, the sheet resistance of the source / drain portions is reduced, so that the TF
Even if the T bulk layer is used as a wiring layer, a stable memory cell in which the voltage does not drop can be made.

Since the source / drain portion has upper wiring,
It is not necessary to drop it in the lower layer, and there is a margin in the pattern, which is effective for wiring.

When the contact for the upper wiring is opened in the source / drain portion, the dry etching process can be performed, so that there is a margin in the rule around the contact.

[0021] There is an effect.

By adjusting the patterning dimension of FIG. 1A, the source / drain portions can be formed in a self-aligned manner with respect to the gate electrode, so that a transistor with less variation can be formed.

Similarly, since the offset length can be formed in a self-aligned manner with respect to the gate electrode, a transistor with a small variation and a small leak current can be formed.

As a result, when the TFT is used for the SRAM, it is possible to make the one in which the standby current is small and the variation is small.

Further, when the source / drain portions are formed by impurity diffusion between the polysilicon 103 and the polysilicon 105, laser annealing treatment can be performed to reduce crystal defects in the silicon junction portion. As a result, it is possible to form a TFT that has a small leak current, that is, a small standby current when used as an SRAM.

Further, by adjusting the distance between the gate electrode and the source / drain in the pattern of FIG. 1A, the offset lengths on the source side and the drain side can be adjusted separately.

Further, in FIG. 1B, since the silicon oxide film to be the gate film can also be formed by CVD, it can be formed on the glass substrate, so that the range of application is expanded.

Further, in this embodiment, no impurities are introduced into the TFT channel portion, but similar effects can be obtained even if P-type or N-type impurities are introduced.

In this embodiment, the polysilicon film is formed at 600 to 640 ° C. in the monosilane atmosphere.
Similar effects can be obtained even when the film is formed at 450 to 600 ° C. in a monosilane atmosphere. In a disilane atmosphere, 400 to 6
Even if it is formed at 00 ° C., the same effect can be obtained. 50 more
Similar effects can be obtained even if heat treatment is performed at 0 to 900 ° C.

Further, as described above, the same effect can be obtained by forming it on the glass substrate.

Further, in the case where the patterning of the polysilicon film 103 in this embodiment is difficult by ordinary photo, the same effect can be obtained by patterning by excimer laser exposure or EB exposure.

[0032]

According to the present invention, since the channel portion is thin and the source / drain portions are thick, the TFT characteristics are improved and the resistance of the source / drain portions is small, and the lower gate structure TFT in which wiring can be freely provided can be supplied.

Further, since the source / drain portion and the offset can be formed in a self-aligned manner with respect to the gate electrode, it is possible to provide a lower gate structure TFT having a small variation in characteristics.

[Brief description of drawings]

FIG. 1 is a sectional view in order of steps, showing an embodiment of a method for manufacturing a semiconductor device of the present invention.

2A to 2D are cross-sectional views in order of the processes, showing an example of a method for manufacturing a conventional semiconductor device.

[Explanation of symbols]

101, 201
... Semiconductor substrate 102, 104, 106, 202, 204, 208
..Silicon oxide films 103, 105, 203, 205
..Polysilicon film 206..TFT
Source / drain section 207 ・ ・
・ TFT channel part 107, 209
... Aluminum wiring

Claims (3)

[Claims] 1. A semiconductor device comprising a TFT transistor having a lower gate structure, wherein a channel portion is thin and a source / drain portion is thick. 2. In a TFT transistor having a lower gate structure, a step of forming a first insulating film on a semiconductor substrate, a step of performing a desired patterning after forming the first semiconductor film on the first insulating film, and the patterning. Forming a second insulating film on the formed first semiconductor film, and then performing desired patterning,
A method of manufacturing a semiconductor device, comprising: a step of forming a first semiconductor film on the patterned first semiconductor film and a second insulating film; and a step of performing heat treatment. 3. The method of manufacturing a semiconductor device according to claim 2, wherein laser annealing is performed in the heat treatment step.