JPH05190867A - Flash eeprom memory cell - Google Patents

Abstract

PURPOSE: To provide an EEPROM memory cell to be manufactured without sensitively executing positioning. CONSTITUTION: An electrically erasable and programmable read-only memory cell includes a gate insulator layer 52 formed on the surface of a semiconductor layer 50 having a 1st conductive type. A conductive floating gate is formed on the layer 52 and has 1st and 2nd parts 60a, 60b and a gap 82 for substantially separating the 1st and 2nd parts 60a, 60b in the lateral direction. An insulator layer 80 of an intermediate level is formed on the exposed surface of the floating gate. A conductive control gate 90 is formed on the insulator layer 80 formed in the gap so as to be capacitively connected to the floating gate. A 2nd conductive source area 74 and a drain area 76 are formed on the side of an outer lateral margin opposite to the floating gate. This invented EEPROM cell can evade a channel length positioning problem which is raised in an EEPROM manufactured by conventional technology.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to electronic semiconductor devices and more particularly to electrically erasable and programmable memory devices or merged FA devices.
The present invention relates to a MOS device and a manufacturing method thereof that can be produced without being sensitive to alignment.

[0002]

Nonvolatile semiconductor memory devices based on metal-oxide-semiconductor field-effect transistors were first proposed in 1967 (Wiley-Interscien.
published in 1981 by ce (Sze)
Written by "Physics of Semiconductor Devices"
Semiconductor devices, 2nd edition, pp. 496-506.) These devices store information bits in the presence or absence of charge on the floating gate, which charge affects the threshold voltage of the MOSFET. The floating gate is located like this.
MOSFET non-volatile memory devices include JEPROM, E
An EPROM and a flash EEPROM are included.

Flash EEPROM is EPROM
(Electrical avalanche injection) or EEPROM (tunneling) is programmed and erase is performed like EEPROM (tunneling), but the erasing is generally similar to the UV erasing of EPROM, and the entire memory is electrically erased. Limited to erasure. Flash E
Since the EPROM does not erase cells individually, it has a feature that the cell size is smaller than that of a standard EEPROM. Instead, the cell array is entirely erased.

Flash EEPROMs are very sensitive to alignment because they use a merge pass gate structure that turns off the channel when the floating gate is over-erased. One of these flash EEPROM cells
Misalignment between one control gate and the floating gate will either increase or decrease the length of the channel controlled by the control gate and correspondingly decrease the remaining channel length (controlled by the floating gate) Or it will increase and cause variations in the read, write and programming characteristics of the cell. Therefore, an EEPROM or merge FAM that is not sensitive to alignment and can be manufactured
It is desirable to develop an OS device.

[0005]

SUMMARY OF THE INVENTION According to the present invention, an electrically erasable and electrically programmable read-only memory cell is formed on a surface of a semiconductor layer of a first conductivity type. A gate insulator layer is formed on the surface of the semiconductor layer. A conductive floating gate having first and second portions is formed on the surface of the gate insulator layer. The first and second portions of the conductive floating gate are separated by a gap. A source of a second conductivity type opposite to the first conductivity type, on the surface of the semiconductor layer, separated by a channel area, adjacent to outer sides of the first and second portions of the floating gate, respectively. A region and a drain region are formed.

An insulating layer is formed adjacent to at least the inner side surface and the uppermost surface of the first and second portions of the floating gate.

An oxide layer is formed on the exposed surfaces of the first and second portions of the floating gate, on the channel area in the gap, and on the source and drain regions. A conductive control gate is then formed on the insulating oxide covering the floating gate and the channel region in the gap between the first and second portions of the floating gate.

The technical features of the present invention include the conventional EEP.
It includes a structure and a manufacturing method for essentially eliminating the drawbacks and problems of the ROM memory cell. One important aspect is that it is not sensitive to alignment, which provides high quality memory cells with better programming characteristics and less variation than existing cells of the prior art.

Other embodiments of the present invention and their features will become apparent from the detailed description given below with reference to the drawings.

[0010]

The preferred embodiment of the present invention is best understood by referring to FIGS. In the drawings, similar or corresponding parts are designated by the same reference numerals.

FIG. 1 is a schematic functional block diagram of the structure of the EEPROM memory matrix 10. EEPROM array 1
It should be appreciated that 0 may be a module on a larger integrated circuit, or it may incorporate the memory cells described herein as a separate integrated circuit. The array body portion 10 includes, for example, N rows and M rows as an N × M bit array. An array of suitable size is, for example, 8K words of 8 bits per word for a total of 64K bits. For example, 256 lines, 25
Can consist of an array of 6 columns or 128 rows, 51
It can be configured with two rows.

The EEPROM array 10 includes a row decoder 1
A plurality of row lines 12 connected to four, a column decoder,
A plurality of column lines 16 connected to a level shifter and sense amplifier section 18.
Includes and. The row decoder block 14 and the column decoder block 18 are then connected to the control and charge pump (c
charge pump) connected to the circuit block 20. The control and charge pump block 20 and the row decoder block 14 are an input / output interface block sandwiched between the decoder 14 and the charge pump block 20 and wiring outside the chip or module in which the EEPROM array 10 is placed. It is connected to 22. The input / output interface block 22 is also connected to the column decoder block 18.

FIG. 2 is a high-magnification enlarged sectional view of an EEPROM memory cell according to the prior art. The cells, generally designated 24, are conventionally used to construct an array 10 as shown in FIG. The conventional EEPROM cell 24 includes a floating gate 26 and a control gate 28. The floating gate 26 and the control gate 28 are, for example, 40
Thin gate oxides 32a and 32 with thicknesses of 0Å and 100Å
It is insulated and separated from the channel 30 by b.
If the EEPROM cell 24 is of the Fowler-Nordheim type programming scheme, the gate oxide 32 is adjacent to the source region 36 to allow Fowler-Nordheim tunneling (not shown). Thinner in place. The floating gate 26 and the control gate 28 are insulated and separated from each other by an insulating layer 34, and the insulating layer 34 is, for example, an oxide / nitride composite layer in order to provide excellent dielectric properties.

The channel 30 is adjacent to the source region 36, which is shown here as (n +), and the substrate or epitaxial layer 38 in which the cell 24 is formed is of the (p) type. The channel 30 separates the source 36 from the (n +) drain 40.

The conventional cell 24 has a length a of the channel 30.
The conductivity is controlled by the control gate 28 at the portion of, and its conductivity is controlled by the floating gate at the portion of the length b of the channel 30, because they vary depending on the alignment. In addition, alignment is important. If the floating gates 26 are misaligned, the length b will be shorter or longer than the design value, and the length a will undergo the opposite variation. This causes a change in the amount of read current, as well as a change in the programming and erase voltages, between cells on the chip. The present invention solves such alignment problems in the prior art.

Referring now to FIG. 5a, there is shown a plan view of semiconductor substrate 50. 3a-1 and 3a-2 are each essentially the same as line 3 of this FIG. 5a.
FIG. 3 is a cross-sectional view taken along line a-1-3a-1 and line 3a-2-3a-2. FIG. 3a-1 shows a cross section of a region of the cell which will become a future channel, and FIG. 3a-2 shows a cross section of the transistor isolation region. Semiconductor substrate or layer 5
0 is preferably doped in the (p-) form and supplied.
A thick (about 4000 Å) thick separating oxide 51 is grown by conventional methods into selected areas of the substrate 50 surface 54. Thereafter, a pad oxide 53 is grown on the exposed area of the semiconductor surface 54.

Next, as shown in FIG. 3b, a resist pattern 55 is used to connect the length of the array to the heavily doped N + regions which form the source and drain bit lines. An elongated strip is formed. (FIGS. 3b and 3c are taken along the same line as shown in FIG. 3a-2.) A two-step implant is performed: first, 4 × 10 ¹⁴ / cm ² dose of phosphorus. Then, arsenic with a dose of 5 × 10 ¹⁵ / cm ² is implanted. After these implants,
Anneal at 900 ° C. in nitrogen to form a graded junction. The pad oxide 53 is then stripped.

Referring now to FIG. 3c, an oxidation step is then performed to form a thick oxide 57 on the order of 2000Å over the heavily doped n + regions 74 and 76. Next, a thin oxide 52, on the order of 150Å thick, is formed over the lightly doped channel region. Following this, a heavily doped polycrystalline silicon (poly) layer 56 is deposited to a thickness of about 2000Å. The poly layer 56 may be doped in situ with phosphorus to make it highly conductive.

Referring to FIG. 3d, which is a partially cutaway bird's eye view corresponding to FIG. 3c, but with a photoresist layer (not shown), the first poly layer 56 is Pattern on elongated N + oxide into elongated strip shapes separated by grooves running the length of the array. Furthermore, as shown in the plan view of FIG.
A rectangular opening 82 is formed over the central portion of the channel 72, extending over the isolation oxide. In the cross-sectional view of Figure 3d this appears as two elements 60a and 60b.
Both floating gate elements 60a and 60b preferably extend over the channel region 72 to a width on the order of 0.6 μm. Half of the adjacent floating gates 62 are shown, as well as half of the adjacent floating gates 58. It is assumed that the remaining floating gates of array 10 are also made at the same time as the few shown in Figure 3d.

The distance between the inner sides of the floating gate elements 60a and 60b is preferably on the order of 0.8 microns.

At this point, implants can be made in the interstitial region to adjust the threshold voltage of the control gate transistor that is to be produced in this region.

Referring now to FIG. 3e, thermal oxide growth is performed on the exposed surface of the floating gate poly 56 to form an insulating layer 80 between the floating gates 58, 60 and 62 and the control gate 90. , And the gate oxide 8 of the control gate transistor also on the exposed channel region in the gap 82.
The oxide of 4 is grown. This oxide is 300
It is Å or 400 Å. If a thinner insulating dielectric between the floating and control gates is desired,
A thin oxide / nitride stack (typically a combination of 150Å oxide and 250Å nitride) is deposited prior to floating gate patterning and etching. This nitride prevents further increase in the thickness of the dielectric material during the oxidation process.

A first heavily doped polycrystalline silicon layer 90 is deposited over insulating layers 80 and 84 and into gaps or holes 82 to form a control gate as shown. Poly layer 90 should preferably be deposited to a thickness of 3000Å. This poly is then patterned and etched perpendicular to the source and drain bit lines to form word lines 90 as shown in Figure 5c. Subsequent layers, such as deposited and densified boron phosphosilicate (BPSG) layers and metal contacts through the BPSG layers, are conventional and are omitted here for simplicity.

FIG. 4 is a somewhat enlarged detail of FIG. 3e and illustrates the main features of the present invention. The EEPROM cell of the present invention has three regions: a first region which is controlled by the floating gate portion 60a and has a length b1, a central region which has a length a and is controlled by the control gate 90, It has a channel 72 controlled by the floating gate 60b and divided into a third region of length b2. If there is a misalignment in one or the other direction, the gate length, for example b2, decreases, which increases the gate length b1. The length a of the central region stays about the same, so that the total length of the floating gate channel stays at b1 + b2. Therefore, this EEPRO
The operating characteristics of the M cell are the same between cells.

FIG. 5c is a highly magnified schematic plan view of a portion of the EEPROM array 10. 3e is now taken along line 3e-3e essentially as shown. Floating gates 58-62 are shown in dashed lines and preferably have the shape of a completely hollow rectangle. Channel 7 extending over field oxide 51
The upper and lower portions 100 of 2 are floating gate portions 60a and 60
b is connected to form a single conductor. The horizontal margin 102 (as shown in FIG. 5c) of the channel 72 is bounded by a thick (eg 4000Å) field oxide island 51. The margin 106 in the vertical direction or the side surface of the field oxide island 51 is bounded by the margins of the source region 74 and the drain region 76. A (p) type channel stop (not shown) into the area later occupied by the oxide islands 51 intended to electrically isolate the channels 72 from each other.
It is desirable to type in.

Control gate 90 is 90 ° to elongated implanted source and drain regions 74 and 76.
And has upper and lower margins 108 on the same line as the upper and lower margins of the floating gates 58-62. Margins above and below floating gates 58-62 and control gate 90 also extend onto adjacent field oxide islands 51 to enhance capacitive coupling. The control gate 90 corresponds to the column line 16 shown in FIG. 1 as shown in FIG.
Source and drain regions 74 and 76 also correspond to row line 12.

The cell of the present invention reads, similar to a conventional EEPROM cell, such as the cell shown in FIG.
Written and erased.

Although the preferred embodiments of the present invention and their features have been described above in detail, the present invention is not limited to this description, but is limited only by the claims.

With respect to the above description, the following items will be further disclosed. (1) An electrically erasable and programmable read-only memory cell comprising: a gate insulator layer formed on a surface of a semiconductor layer having a first conductivity type; and a conductivity formed on the insulator layer. Floating gate having first and second floating gate portions, having a gap that essentially laterally separates the first and second floating gate portions, and having a top surface A floating gate having a plurality of inner side surfaces and further having a plurality of outer side surfaces distant from the gap; an intermediate level insulator layer formed on the uppermost surface and the inner side surface of the floating gate; A conductive control gate formed on the intermediate level insulator layer and in the gap to capacitively couple with the floating gate; on the surface of the semiconductor layer, a conductive control gate opposite to the first conductive type; 2 conductive type, in front of the floating gate A source region adjacent to the first one of the outer side faces, a second outer side face of the floating gate formed on the surface of the semiconductor layer in the second conductivity type and facing the first outer side face. A drain region adjacent to, a region of the first conductivity type defined below the floating gate and the gap and defined on the surface between the source and drain regions, A memory region, the portion of which has a conductivity controlled by the control gate.

(2) The memory cell according to item 1, wherein
A memory cell in which the first and second portions of the floating gate are conductively coupled to each other.

(3) The memory cell according to item 2,
A memory, wherein the first and second floating gate portions include heavily doped polycrystalline silicon and at least one further portion of the floating gate connecting the first and second portions. cell.

(4) The memory cell according to item 1,
A memory cell in which the floating gate comprises heavily doped polycrystalline silicon.

(5) The memory cell according to item 1, wherein
A memory cell in which the control gate comprises heavily doped polycrystalline silicon.

(6) The memory cell according to item 1, wherein
A memory cell in which the intermediate level insulator layer comprises an oxide / nitride stack of insulator layers.

(7) The memory cell according to item 1,
A memory cell in which the floating gate includes a rectangle surrounding the gap in plan view, and the first and second floating gate portions are connected by the third and fourth floating gate portions to surround the gap.

(8) A memory cell according to item 7,
A memory cell in which the control gate is capacitively coupled to the entire top surface of the floating gate.

(9) The memory cell according to item 1, wherein
The first and second floating gate portions control the conductivity of respective portions of the channel which occupy about 30% of the length of the channel, and the control gate is about 40 of the length of the channel. A memory cell controlling a portion of the channel that occupies a percentage.

(10) The memory cell according to item 1, wherein the source and drain regions are (n) type.

(11) The memory cell according to item 1, wherein the semiconductor layer contains silicon.

(12) An array of electrically erasable and programmable memory cells formed on the surface of a semiconductor layer of a first conductivity type arranged in columns and rows at an angle to the columns: A second conductivity type opposite to the first conductivity type,
A plurality of source and drain regions elongated in the row direction on the surface, the source and drain regions being substantially parallel to each other and spaced apart from each other, one column and the source. A channel region defined in the layer and an intersection with one pair of drain regions, a gate insulator layer formed on the surface over the channel region, and covering the channel region. A conductive floating gate formed on the gate insulator layer and having first and second floating gate portions, a gap essentially laterally separating the first and second floating gate portions, and The floating gate having a top surface and a plurality of outer side surfaces spaced from the gap; an intermediate level insulator layer formed on the top surface and the side surfaces of the floating gate;
An insulated control gate conductor formed adjacent to the floating gate in the last column and the floating gate in the gap in the column, provided for each column of cells;
A memory cell array including.

(13) The array according to item 12,
An array including a plurality of oxide islands formed on the surface between adjacent floating gate channels and between adjacent source and drain pairs.

(14) The array according to item 13,
An array in which a margin between the floating gate and the control gate extends over a lateral margin of the oxide island, thereby enhancing capacitive coupling between the control gate and respective portions of the floating gate.

(15) The array according to item 12,
An array in which each of the floating gates is in the shape of a hollow rectangle.

(16) The array according to item 12,
Each of said floating gates has two floating gate portions for controlling respective portions of respective channel regions formed thereunder, and said floating gate portions connecting the ends of said first and second portions. An array having third and fourth portions of floating gates.

(17) The array according to item 12,
An array further comprising a relatively thick region grown over the surface over the source and drain regions and mounted below the control gate conductor.

(18) A method of making an electrically erasable and programmable read-only memory cell on a surface of a semiconductor layer having a first conductivity type, which comprises a second conductivity type opposite to the first conductivity type. Implanting a conductivity type dopant to form source and drain regions on the surface of the semiconductor layer, forming a gate insulator layer on the surface, and forming a floating gate layer on the gate insulator layer; Etching the floating gate layer to form a floating gate having a hole therein and an outer lateral margin; insulating the floating gate layer with an intermediate level insulator layer; Forming a conductive control gate layer overlying the floating gate insulator layer adjacent to the gate insulator layer.

(19) The method according to the eighteenth aspect, further comprising forming a thick insulator layer prior to the implanting step so that the thick insulator layer is below the outer lateral margin of the floating gate. And forming the conductive control gate layer adjacent to the thick insulator layer.

(20) The method according to item 18, wherein the cell is one of a plurality of cells formed in rows and columns on the surface of the semiconductor layer, further comprising a column direction. Forming a plurality of said control gate layers to be separated into two, one control gate layer for each column of said cells.

(21) The method according to the eighteenth item, wherein the gate insulator is an oxide layer having a thickness of 400Å.

(22) A method according to item 18, wherein the floating gate contains heavily doped polycrystalline silicon.

(23) The method of claim 18, wherein the intermediate level insulator layer comprises an oxide / nitride stack.

(24) A method according to item 18, wherein the conductive control gate layer includes heavily doped polycrystalline silicon.

(25) The method according to the eighteenth item, wherein the source and drain regions are elongated and parallel to each other in the semiconductor layer.

(26) The method according to the eighteenth aspect, further comprising growing a relatively thick oxide region so as to cover the source and drain regions after the implanting step, to form the relatively thick oxide region. A method comprising allowing a region to be formed under the control gate layer.

(27) The electrically erasable and programmable read-only memory cell includes a gate insulator layer formed on the surface of the semiconductor layer having the first conductivity type. A conductive floating gate is formed on the gate insulator layer, the conductive floating gate having first and second portions, and having a gap that substantially laterally separates the first and second portions. ing. An intermediate level insulator layer is formed on the exposed surface of the floating gate. A conductive control gate is formed on the intermediate level insulator layer in the gap so as to be capacitively coupled to the floating gate. A source region and a drain region of the second conductivity type are formed beside the outer lateral margins facing each other of the floating gate. The EEPROM cell of the present invention is a prior art EE
Avoid the problem of channel length alignment, which is a problem with PROM cells.

[Brief description of drawings]

FIG. 1 is a schematic functional block diagram of an EEPROM memory matrix.

FIG. 2 is an enlarged cross-sectional view of a semiconductor layer showing a memory cell according to the prior art.

Figure 3a-1 shows the process steps for manufacturing an EEPROM according to the invention, lines 3a-1-3a- of Figure 5a.
2 is an enlarged cross-sectional view of the semiconductor layer taken along FIG. a-2 is an enlarged cross-sectional view of the semiconductor layer taken along line 3a-2-3a-2 of FIG. 5a showing the process steps of manufacturing an EEPROM according to the present invention. b is EEPRO according to the present invention
Line 3a of FIG. 5a showing the process steps for manufacturing M
2-3a-2 is an enlarged cross-sectional view of the semiconductor layer taken along. 5c is an enlarged cross-sectional view of the semiconductor layer taken along line 3a-2-3a-2 of FIG. 5a showing the process steps of manufacturing an EEPROM according to the present invention. 3a-1, 3a-2, and 3b, which show the steps of manufacturing the cell of the present invention.
FIG. 5c is a bird's-eye view showing a cross-section partially taken along line 3d-3d of FIG. 5b, corresponding to the cross-section of FIGS. 3c and 3e.
5e is an enlarged cross-sectional view of the semiconductor layer taken along line 3e-3e of FIG. 5c showing the process steps of manufacturing an EEPROM according to the present invention.

FIG. 4 is an enlarged detail view of FIG. 3e.

FIG. 5A is a plan view of a memory cell array product. b is FIG.
The top view of the memory cell array product shown by a. c is FIG.
5 is a plan view of the memory cell array corresponding to FIG.

[Explanation of symbols]

 10 EEPROM memory matrix 12 row line 14 row decoder 16 column line 18 column Degoder, level shifter and sense amplifier 20 Control and charge pump circuit 22 Row decoder 24 EEPROM memory cell 26 Floating gate 28 Control gate 30 Channel 32a, 32b Gate oxide 34 Insulation Layer 36 Source region 38 Substrate or epitaxial layer 40 Drain region 50 Semiconductor substrate 51 Isolation oxide 52 Thin oxide 53 Pad oxide 54 Semiconductor surface 55 Resist pattern 56 Poly layer 57 Thick oxide 58 Floating gate 60a, 60b Floating gate element 62 Floating gate 64 Inner side surface 72 Channel 74 n + Source region 76 n + Drain region 80 Insulating layer 82 Rectangular opening 84 Insulating layer 90 Control gate 100 Part 102 Water Flat margin 106 Vertical margin 108 Horizontal top and bottom margins

Claims (2)

[Claims] 1. An electrically erasable and programmable read-only memory cell comprising: a gate insulator layer formed on a surface of a semiconductor layer having a first conductivity type; and a gate insulator layer formed on the insulator layer. A conductive floating gate having first and second floating gate portions, a gap essentially laterally separating the first and second floating gate portions, and a top surface. A floating gate having a plurality of inner side surfaces and further having a plurality of outer side surfaces separated from the gap; and an intermediate level insulator layer formed on the uppermost surface and the inner side surface of the floating gate. A conductive control gate formed on the intermediate level insulator layer and in the gap so as to be capacitively coupled to the floating gate, the conductive control gate being formed on the surface of the semiconductor layer opposite to the first conductivity type. The second conductive type is formed, and the floating gate is formed. A source region adjacent to the first one of the outer side surfaces of the floating gate, the second region of the floating gate formed on the surface of the semiconductor layer in the second conductivity type and facing the first outer side surface. A drain region adjacent to an outer side surface of the floating gate and the first region defined below the floating gate and the gap and defined on the surface between the source and drain regions.
A channel region of the conductivity type, wherein each portion of the channel region has a conductivity controlled by the control gate. 2. A semiconductor layer surface having a first conductivity type,
A method of making an electrically erasable and programmable read-only memory cell: implanting a dopant of a second conductivity type opposite to the first conductivity type to source and drain regions at the surface of the semiconductor layer. Forming a gate insulator layer on the surface, forming a floating gate layer on the gate insulator layer, etching the floating gate layer, having holes therein, and Forming a floating gate having a lateral margin, insulating the floating gate layer with an intermediate level insulator layer, and covering the floating gate insulator layer in the hole adjacent to the gate insulator layer. Forming a conductive control gate layer.