JPH051908B2 - - Google Patents
Info
- Publication number
- JPH051908B2 JPH051908B2 JP59181420A JP18142084A JPH051908B2 JP H051908 B2 JPH051908 B2 JP H051908B2 JP 59181420 A JP59181420 A JP 59181420A JP 18142084 A JP18142084 A JP 18142084A JP H051908 B2 JPH051908 B2 JP H051908B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- current
- load
- pseudo
- opa
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- 238000001514 detection method Methods 0.000 claims description 21
- 230000003321 amplification Effects 0.000 description 5
- 238000003199 nucleic acid amplification method Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
Landscapes
- Testing Electric Properties And Detecting Electric Faults (AREA)
Description
【発明の詳細な説明】
本発明は、各種電子機器用直流電源の特性試験
に好適な擬似電子負荷装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pseudo electronic load device suitable for testing the characteristics of DC power supplies for various electronic devices.
各種電子機器用直流電源の特性試験を行う場
合、従来は、実際の電子機器を負荷として直流電
源に接続する代りに、摺動抵抗器等の純抵抗を擬
似負荷として接続している。このような擬似負荷
を用いるときは、その構成が簡単で、負荷の大き
さを自在に変え得る等の利点があるが、例えば、
電源投入時における出力の立上り特性又は電源遮
断時における出力の立下り特性等を試験する場合
には、実際の電子機器を負荷とした場合と純抵抗
より成る擬似負荷を用いた場合とでは試験結果に
大きな相異を生ずることとなる。 When testing the characteristics of a DC power supply for various electronic devices, conventionally, instead of connecting the actual electronic device as a load to the DC power source, a pure resistance such as a sliding resistor is connected as a pseudo load. When using such a pseudo load, there are advantages such as its simple configuration and the ability to freely change the size of the load.
When testing the output rise characteristics when the power is turned on or the output fall characteristics when the power is turned off, the test results differ depending on whether an actual electronic device is used as the load or when a pseudo load made of pure resistance is used. There will be a big difference between the two.
本発明は、負荷の構成内容及び大きさ(消費電
力)等の変更が容易で、電子機器用直流電源の特
性試験に供した場合、実際の電子機器を負荷とし
た場合とほぼ同等の試験結果の得られる擬似電子
負荷装置を実現することを目的とする。 The present invention makes it easy to change the configuration and size (power consumption) of the load, and when subjected to a characteristic test of a DC power supply for electronic equipment, the test results are almost the same as when an actual electronic equipment is used as the load. The purpose of this study is to realize a pseudo-electronic load device that provides the following characteristics.
第1図は、本発明の一実施例について、その基
本構成を説明するための図で、T+及びT-は直流
電源接続端子、ELは擬似電子負荷回路素子、
DIELは擬似電子負荷回路素子ELの電流検出回路、
COMは比較回路、AMPは誤差増幅器、CONは
電流制御回路、DICONは電流制御回路CONの電流
検出回路で、これらによつて本発明擬似電子負荷
装置が構成される。 FIG. 1 is a diagram for explaining the basic configuration of an embodiment of the present invention, where T + and T - are DC power supply connection terminals, EL is a pseudo electronic load circuit element,
D IEL is the current detection circuit of the pseudo electronic load circuit element EL,
COM is a comparison circuit, AMP is an error amplifier, CON is a current control circuit, and D ICON is a current detection circuit of the current control circuit CON, and these constitute the pseudo electronic load device of the present invention.
端子T+及びT-に直流電源を接続すると、端子
T+及びT-から流入した電流の擬似電子負荷回路
素子ELと電流制御回路CONに分流し、各分流電
流は検出回路DIEL及びDICONで検出され、比較回路
COMにおいて検出回路DIELの検出電流と検出回
路DICONの検出電流との差が検出され、この検出
信号が誤差増幅器AMPを介して電流制御回路
CONに導入され、検出回路DIEL及びDICONの各検
出電流の大きさの比が任意の値となるように電流
制御回路CONの回路インピーダンスの大きさを
変化せしめる。 When connecting a DC power supply to terminals T + and T - , the terminals
The current flowing in from T + and T - is shunted to the pseudo electronic load circuit element EL and the current control circuit CON, and each shunt current is detected by the detection circuits D IEL and D ICON , and the comparison circuit
The difference between the detection current of the detection circuit D IEL and the detection current of the detection circuit D ICON is detected at COM, and this detection signal is sent to the current control circuit via the error amplifier AMP.
The circuit impedance of the current control circuit CON is changed so that the ratio of the magnitudes of the detected currents of the detection circuits D IEL and D ICON becomes an arbitrary value.
擬似電子負荷回路素子ELとして、例えば、ト
ランジスタ・トランジスタ論理回路素子を用いる
ことにより、端子T+及びT-に加えられる直流電
圧と、擬似電子負荷回路素子EL及び電流制御回
路CONに流れる全電流との関係を比例関係では
なく非直線関係ならしめ、又、電流検出回路
DICONの回路構成及び回路定数を適当にして電流
検出比が1/Nとなるようにすれば、擬似電子負
荷回路素子ELをN個並列接続した場合と等価な
擬似電子負荷装置を構成することが出来る。 For example, by using a transistor/transistor logic circuit element as the pseudo electronic load circuit element EL, the DC voltage applied to terminals T + and T - , the total current flowing through the pseudo electronic load circuit element EL and the current control circuit CON, and The relationship between is made non-linear rather than proportional, and the current detection circuit
If the circuit configuration and circuit constants of D ICON are appropriately set so that the current detection ratio is 1/N, a pseudo electronic load device equivalent to the case where N pseudo electronic load circuit elements EL are connected in parallel can be configured. I can do it.
第2図は、本発明の一実施例を示す図で、T+
及びT-は直流電源接続端子、EL1は擬似電子負
荷回路素子で、例えばトランジスタ・トランジス
タ論理回路素子より成る。VCC及びGNDはその直
流電源接続ピン、OPA1及びOPA2は演算増幅器
(OPA1及びOPA2の作動電源接続端子、OPA2の
帰還素子等は省略してある。)、TRは電流制御用
トランジスタ、R1は負帰還抵抗、R2は電流検出
抵抗で、これらによつて本発明擬似電子負荷装置
が構成される。 FIG. 2 is a diagram showing an embodiment of the present invention, in which T +
and T - are DC power supply connection terminals, and EL 1 is a pseudo electronic load circuit element, such as a transistor/transistor logic circuit element. V CC and GND are the DC power supply connection pins, OPA 1 and OPA 2 are operational amplifiers (OPA 1 and OPA 2 operating power supply connection terminals, OPA 2 feedback element, etc. are omitted), TR is for current control. The transistor, R1 is a negative feedback resistor, R2 is a current detection resistor, and these constitute the pseudo electronic load device of the present invention.
演算増幅器OPA1の増幅度A1が十分大であれ
ば、非反転入力端子への接続点aと反転入力端子
への接続点bとは同電位となるから、直流電源接
続端子T+及びT-に直流電圧Vが印加されると、
回路素子EL1に直流電圧Vが加えられる。回路素
子EL1に流れる電流をI1、電流制御用トランジス
タTRに流れる電流をI2、演算増幅器OPA2の増幅
度をA2とし、抵抗R1及びR2の各抵抗値をR1及び
R2を以て表わすと、トランジスタTRに流れる電
流I2は抵抗R2における電圧降下として検出され、
この検出電圧は演算増幅器OPA2及び抵抗R1を介
して演算増幅器OPA1の入力側に負帰還され、演
算増幅器OPA1の出力電圧に応じてトランジスタ
TRの内部インピーダンスが変化し、
I2=R1/R2・I1/A2
なる関係が保たれるように制御が行われる。直流
電源接続端子T+及びT-から負荷側へ流入する全
電流をI0とすると、
I0=I1+I2=I1+R1/R2・I1/A2
=I1(1+R1/R2・I/A2
上式において、1+R1/R2・I/A2=Nとおくと、
I0=I1・N
となる。 If the amplification degree A 1 of the operational amplifier OPA 1 is sufficiently large, the connection point a to the non-inverting input terminal and the connection point b to the inverting input terminal will be at the same potential, so the DC power supply connection terminals T + and T - When a DC voltage V is applied to
A DC voltage V is applied to the circuit element EL1 . The current flowing through the circuit element EL 1 is I 1 , the current flowing through the current control transistor TR is I 2 , the amplification degree of the operational amplifier OPA 2 is A 2 , and the resistance values of the resistors R 1 and R 2 are R 1 and
Expressed by R 2 , the current I 2 flowing through the transistor TR is detected as a voltage drop across the resistor R 2 ,
This detection voltage is negatively fed back to the input side of the operational amplifier OPA 1 via the operational amplifier OPA 2 and the resistor R 1 , and the transistor
Control is performed so that the internal impedance of the TR changes and the relationship I 2 =R 1 /R 2 ·I 1 /A 2 is maintained. If the total current flowing from the DC power supply connection terminals T + and T - to the load side is I 0 , then I 0 = I 1 + I 2 = I 1 + R 1 /R 2・I 1 /A 2 = I 1 (1 + R 1 /R 2 · I/A 2 In the above equation, if 1+R 1 /R 2 ·I/A 2 =N, then I 0 =I 1 ·N.
本実施例においては、回路素子EL1をトランジ
スタ・トランジスタ論理回路素子を以て形成して
あるので、端子T+及びT-に加えられる直流電圧
Vと負荷側を流れる全電流I0との関係が非直線性
を呈し、従来のように純抵抗を用いる場合に比し
実際の電子機器を負荷とした状態に近いものとな
る。又、抵抗R1及びR2の抵抗値、演算増幅器
OPA2の増幅度A2を適宜調整して前記のNを適当
な値となすことにより、回路素子EL1を任意適宜
数、即ち、N個並列接続したものと等価な擬似電
子負荷装置を実現することが出来る。 In this embodiment, since the circuit element EL 1 is formed of a transistor/transistor logic circuit element, the relationship between the DC voltage V applied to the terminals T + and T - and the total current I 0 flowing through the load side is non-linear. It exhibits linearity and is closer to the state in which an actual electronic device is used as a load compared to the conventional case of using pure resistance. Also, the resistance values of resistors R 1 and R 2 , operational amplifier
By appropriately adjusting the amplification degree A 2 of OPA 2 and setting N to an appropriate value, a pseudo-electronic load device equivalent to an arbitrary number of circuit elements EL 1 , that is, N pieces connected in parallel, can be realized. You can.
上記実施例は従来のような純抵抗より成る擬似
負荷に較べれば遥かに実際の電子機器を負荷とし
た状態に近い試験結果が得られるが、実際の電子
機器はトランジスタ・トランジスタ論理回路の
他、例えばダイオード・トランジスタ論理回路、
MOS電界効果トランジスタを主体とする集積回
路、エミツタ結合形トランジスタより成る高速論
理回路、各種メモリ回路、各種集積回路群より成
る大規模集積回路、単独のトランジスタ、ダイオ
ード、抵抗、コンデンサ、コイル等、各種の素子
より成る場合が多く、このような複雑な回路構成
を有する実際の電子機器に較べると、第2図に示
した実施例は擬似負荷として十分には満足すべき
ものといえない。 The above embodiment can obtain test results that are much closer to actual electronic equipment as a load than a conventional pseudo load made of pure resistance, but actual electronic equipment uses transistors, transistor logic circuits, etc. For example, diode transistor logic circuits,
Integrated circuits mainly composed of MOS field effect transistors, high-speed logic circuits composed of emitter-coupled transistors, various memory circuits, large-scale integrated circuits composed of various integrated circuit groups, individual transistors, diodes, resistors, capacitors, coils, etc. The embodiment shown in FIG. 2 cannot be said to be fully satisfactory as a pseudo load when compared with actual electronic equipment having such a complicated circuit configuration.
第3図は、極めて複雑な回路構成より成る実際
の電子機器とほぼ同等の擬似電子負荷装置を実現
し得る本発明の一実施例を示す図で、T+及びT-
は直流電源接続端子、EL1ないしELoはそれぞれ
擬似電子負荷回路素子で、EL1は例えばトランジ
スタ・トランジスタ論理回路素子、EL2は例えば
ダイオード・トランジスタ論理回路素子より成
り、EL3ないしELoもそれぞれ適宜の電子回路素
子より成る。OPA21ないしOPA2o,OPAAD及び
OPANFは演算増幅器、TRは電流制御用トランジ
スタ、R21ないしR2o、R′21ないしR′2o及びRNFは
負帰還抵抗、RDは電流検出抵抗で、これらによ
つて本発明擬似電子負荷装置が構成される。 FIG. 3 is a diagram showing an embodiment of the present invention that can realize a pseudo electronic load device that is almost equivalent to an actual electronic device that has an extremely complicated circuit configuration .
are DC power supply connection terminals, EL 1 to EL o are pseudo electronic load circuit elements, EL 1 is, for example, a transistor/transistor logic circuit element, EL 2 is, for example, a diode/transistor logic circuit element, and EL 3 to EL o are also Each consists of appropriate electronic circuit elements. OPA 21 or OPA 2o , OPA AD and
OPA NF is an operational amplifier, TR is a current control transistor, R 21 to R 2o , R' 21 to R' 2o , and R NF are negative feedback resistors, and R D is a current detection resistor. A load device is configured.
演算増幅器OPA21ないしOPA2nの各増幅度A21
ないしA2oが十分大なるものとし、端子T+及び
T-に直流電源を接続した際に負荷側に流れる全
電流をI0、各負荷回路素子EL1ないしELoに流れ
る電流をI21ないしI2o、各負帰還抵抗R′21ないし
R′2o回路を流れる電流をI′21ないしI′2o、負帰還抵
抗RNFを流れる電流をINF、トランジスタTRに流
れる電流をITR、演算増幅器OPANFの増幅度をANF
とすると、
I′21+I′22+…+I′2o=INF
I21・R21/R′21+I22・R22/R′22+…
+I2o・R2o/R′2o=ANF/RNFITR・RD
ITR=RNF/ANF・RD(I21・R21/R′21
+I22・R22/R′22+…+I2o・R2o/R′2o)
I0=I21+L22+…+I2o+ITR
であるから、
I0=L21(1+RNFR21/ANFRDR′21)
+I22(1+RNFR22/ANFRDR′22)
+…+I2o(1+RNFR2o/ANFRDR′2o)
上式において、
1+RNFR21/ANFRDR′21=N1
1+RNFR22/ANFRDR′22=N2
…
1+RNFR2o/ANFRDR′2o=No
とおくと、
I0=I21N1+I22N2+…+I2oNo
したがつて、N1ないしNoを適当な値に選ぶこ
とにより、負荷回路素子EL1ないしELoがそれぞ
れN1個ないしNo個ずつ並列接続されたと等価の
擬似電子負荷回路を構成することが出来、負荷回
路素子EL1ないしELoをそれぞれ適当な回路素子
を以て形成することにより実際の電子機器に極め
て近い擬似電子負荷装置を構成することが出来
る。 Amplification A 21 of each operational amplifier OPA 21 to OPA2n
or A 2o shall be sufficiently large, and the terminals T + and
The total current flowing to the load side when a DC power supply is connected to T - is I 0 , the current flowing to each load circuit element EL 1 to EL o is I 21 to I 2o , and each negative feedback resistor R' 21 to
The current flowing through the R′ 2o circuit is I′ 21 or I′ 2o , the current flowing through the negative feedback resistor R NF is I NF , the current flowing through the transistor TR is I TR , and the amplification degree of the operational amplifier OPA NF is A NF
Then, I′ 21 +I′ 22 +…+I′ 2o =I NF I 21・R 21 /R′ 21 +I 22・R 22 /R′ 22 +… +I 2o・R 2o /R′ 2o =A NF / R NF I TR・R D I TR =R NF /A NF・R D (I 21・R 21 /R′ 21 +I 22・R 22 /R′ 22 +…+I 2o・R 2o /R′ 2o ) I Since 0 = I 21 + L 22 +…+I 2o +I TR , I 0 = L 21 (1+R NF R 21 /A NF R D R′ 21 ) +I 22 (1+R NF R 22 /A NF R D R′ 22 ) +...+I 2o (1+R NF R 2o /A NF R D R' 2o ) In the above formula, 1+R NF R 21 /A NF R D R' 21 =N 1 1+R NF R 22 /A NF R D R' 22 =N 2 … 1+R NF R 2o /A NF R D R′ 2o =N o , then I 0 =I 21 N 1 +I 22 N 2 +…+I 2o No o Therefore, N 1 or N o By selecting an appropriate value, it is possible to configure a pseudo electronic load circuit equivalent to N 1 to N o load circuit elements EL 1 to EL o connected in parallel, and load circuit elements EL 1 to EL By forming each of o using appropriate circuit elements, it is possible to construct a pseudo electronic load device that closely resembles an actual electronic device.
第1図ないし第3図は、本発明の一実施例を示
す図で、T+及びT-:直流電源接続端子、EL及び
EL1ないしELo:擬似電子負荷回路素子、DIEL及
びDICON:電流検出回路、COM:比較回路、
AMP:誤差増幅器、CON:電流制御回路、VCC
及びGND:直流電源接続ピン、OPA1,OPA2,
OPA21ないしOPA2o,OPAAD及びOPANF:演算
増幅器、TR:電流制御用トランジスタ、R1,
R21ないしR2o,R′21ないしR′2o及びRNF:負帰還
抵抗、R2及びRD:電流検出抵抗である。
Figures 1 to 3 are diagrams showing an embodiment of the present invention, in which T + and T - : DC power supply connection terminals, EL and
EL 1 to EL o : Pseudo electronic load circuit element, D IEL and D ICON : Current detection circuit, COM: Comparison circuit,
AMP: error amplifier, CON: current control circuit, V CC
and GND: DC power supply connection pin, OPA 1 , OPA 2 ,
OPA 21 to OPA 2o , OPA AD and OPA NF : operational amplifier, TR: current control transistor, R 1 ,
R21 to R2o , R'21 to R'2o and RNF : negative feedback resistors, R2 and RD : current detection resistors.
Claims (1)
回路素子の電流検出回路より成る直列回路が任意
数並列接続される直流電源接続端子と、 電流制御回路及びこの電流制御回路の電流検出
回路より成り、前記直流電源接続端子に接続され
る直列回路と、 前記各擬似電子負荷回路素子の電流検出回路の
検出電流の加算電流及び前記電流制御回路の電流
検出回路の検出電流が入力され、前記電流制御回
路の回路インピーダンス制御信号を出力する演算
増幅器回路とを備えたことを特徴とする擬似電子
負荷装置。[Scope of Claims] 1. A DC power supply connection terminal to which any number of series circuits consisting of a pseudo electronic load circuit element and a current detection circuit of this pseudo electronic load circuit element are connected in parallel, a current control circuit, and a current of this current control circuit. a series circuit connected to the DC power supply connection terminal; a summation current of the detection current of the current detection circuit of each of the pseudo electronic load circuit elements; and a detection current of the current detection circuit of the current control circuit. , and an operational amplifier circuit that outputs a circuit impedance control signal of the current control circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59181420A JPS6157862A (en) | 1984-08-29 | 1984-08-29 | Pseudo electronic load device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59181420A JPS6157862A (en) | 1984-08-29 | 1984-08-29 | Pseudo electronic load device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6157862A JPS6157862A (en) | 1986-03-24 |
| JPH051908B2 true JPH051908B2 (en) | 1993-01-11 |
Family
ID=16100453
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59181420A Granted JPS6157862A (en) | 1984-08-29 | 1984-08-29 | Pseudo electronic load device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6157862A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100793718B1 (en) | 2006-08-04 | 2008-01-10 | (주)그린텍시스템 | Electronic load with graphic display |
-
1984
- 1984-08-29 JP JP59181420A patent/JPS6157862A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6157862A (en) | 1986-03-24 |
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