JPH0519338B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a synthesizer tuner, and relates to one in which a clock signal for timing setting is stopped after muting is canceled.

[Conventional technology]

Generally, in a PLL (phase locked loop) synthesizer tuner, as shown in FIG. FM modulated. and,
The output is supplied to an audio amplifier (not shown) via the MPX demodulator 3.

The front end section 1 includes a PLL circuit 4 including a programmable frequency divider, reference starter, phase comparator, etc.
A loop is formed by the low-pass filter 8 and the PLL controller 5 according to the operation input data from the operation unit 7 to the PLL circuit 4.
Data is given to the programmable frequency divider etc. of the PLL circuit 4, thereby making it possible to receive the desired frequency.

The PLL controller 5 has a clock generator 6 that always oscillates at a reference frequency, and uses the clock from the clock generator 6 to control the PLL circuit 4 at the clock timing.
It generates PLL frequency division data to be applied to the PLL and controls the timing of various operations such as scan speed.

[Problem to be solved by the invention]

However, in the conventional PLL synthesizer/tuner, the clock generator 6 continues to oscillate even in the sounding state after the muting output is released, so the frequency of the timing clock is connected to the subsequent stage of the PLL circuit 4. If the cutoff frequency of the low-pass filter 8 is lower than the cutoff frequency of the low-pass filter 8, a problem arises in that the timing clock leaks into the tuning voltage applied to the front end section 1, as shown by the broken line arrow in FIG. That is, the tuning voltage is applied to a voltage-controlled variable capacitance diode (not shown) built in the front end section 1, and is used to perform tuning by tuning to a specific high-frequency signal from the antenna. If the timing clock leaks into this tuning voltage,
This results in modulation of the tuning frequency, which causes deterioration of the SN ratio of the tuner.

SUMMARY OF THE INVENTION An object of the present invention is to stop the clock signal after muting is canceled by controlling the operation of a clock generator that outputs a clock signal for timing setting in conjunction with the muting output.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a PLL that provides tuning data to the front end.
and a PLL controller that controls the PLL circuit and generates PLL operation data, the PLL controller includes a clock generator that oscillates at a reference frequency and a clock generator that generates a clock signal from the clock generator. Generate the PLL data at clock timing
a PLL data generation section, a control means for outputting a muting operation signal and starting the oscillation operation of the clock generator when an operation such as up-down of the reception frequency, band switching, memory call, etc. is performed, and this control means an operation stop signal output means for inputting a clock signal from the clock generator operated by the clock generator and outputting an operation stop signal to the control means when the clock signal reaches a certain set value; The means is characterized in that the output of the muting operation signal is stopped by the operation stop signal, and the oscillation operation of the clock generator is controlled to be stopped.

[Effect]

In the above configuration, when an operation such as raising or lowering the reception frequency is performed, the control means outputs a muting operation signal and the clock generator starts oscillation operation. A clock signal from this clock generator is input to an operation stop signal output means, and when the clock signal reaches a certain set value, an operation stop signal is output. Therefore, the control means uses the operation stop signal to stop the output of the muting operation signal to cancel muting, and also controls to stop the oscillation operation of the clock generator.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 shows in detail the PLL controller 5 and operation section 7 in FIG. Kuji generator,
11 is a clock counter which outputs a reset pulse when its timing clock reaches a certain set number; 12 is an input interface circuit; and 13 is a flip-flop. The input interface circuit 12 operates when a group of switches such as frequency up/down, FM/AM band switching, memory call, etc. are operated on the operation unit 7.
It generates PLL operation data according to those operation input data, and
A set pulse is output at 3. Furthermore, when the flip-flop 13 is set by a set pulse from the input interface circuit 12, it goes high.
The oscillation of the clock generator 6 is started by the muting output of the "L" level, and when the clock generator 6 is reset by the reset pulse from the clock counter 11, the muting output of the "L" level starts the oscillation of the clock generator 6. The oscillation of the regulator 6 is stopped.

Next, the effect will be explained. Now, when a group of switches such as frequency up/down, FM/AM band switching, etc. is operated on the operation unit 7, the input interface circuit 12 generates PLL operation data according to the operation input data, and
A set pulse is output to set the flip-flop 13. Then, the muting output of the flip-flop 13 goes to the "H" level, so the clock generator 6 starts oscillating. When the number of timing clocks from the clock generator 6 reaches a predetermined number, a set pulse is output from the clock counter 11, so that the flip-flop 13 is reset. Then, the muting output of the flip-flop 13 goes to the "L" level, so the clock generator 6 stops oscillating (see FIG. 3).

In this way, the clock generator 6 causes the muting output of the flip-flop 13 to be "H".
It oscillates only during the level, and stops when the muting output is at the "L" level, that is, after the muting is released. Therefore, leakage of the timing clock after canceling muting can be prevented.

〔Effect of the invention〕

As explained above, according to the present invention, when an operation such as up-down of the reception frequency, band switching, memory call, etc. is performed, a muting operation signal is output, the oscillation operation of the clock generator is started, and the clock generator is When the clock signal of the energizer reaches a certain set value, the output of the muting operation signal is stopped by the output of the operation stop signal output means, and the operation of the clock generator is stopped. It is possible to prevent the clock signal from leaking from the clock generator, and as a result, the SN ratio can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the structure of a synthesizer tuner, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is an explanatory diagram of its operation. 6...Clock generator, 7...Operation unit,
11...Clock counter, 13...Flip-flop.

Claims (1)

[Claims] 1. Giving tuning data to the front end
In a synthesizer/tuner comprising a PLL circuit and a PLL controller that controls the PLL circuit and generates PLL operation data, the PLL controller includes a clock generator that oscillates at a reference frequency, and a clock generator that oscillates at a reference frequency. a PLL data generator that generates the PLL data at the timing of the clock; and a PLL data generator that outputs a muting operation signal when an operation such as up-down of the reception frequency, band switching, memory call, etc. is performed, and generates the oscillation of the clock generator. a control means for starting the operation; and a clock signal from the clock generator operated by the control means is input, and when the clock signal reaches a certain set value, an operation stop signal is output to the control means. an operation stop signal output means, and the control means is configured to control the output of the muting operation signal to be stopped by the operation stop signal, and also to stop the oscillation operation of the clock generator. Synthesizer Chiyuna features.