JPH0220930A - Synthesizer tuner - Google Patents

Abstract

PURPOSE:To prevent leak-in a clock signal from a clock generator after muting has been released by stopping a muting operating signal and stopping the clock generator, when a clock signal of the clock generator reaches a set value. CONSTITUTION:When a timing clock from a clock generator 6 reaches a prescribed number, a set pulse is outputted from a clock counter 11, and a flip-flop 13 is reset. Since a muting output of the flip-flop 13 becomes an 'L' level, the clock generator 6 stops an oscillation. In such a way, the clock generator 6 executes the oscillation only while the muting output of the flip-flop 13 is in an 'L' level, and its muting output becomes an 'L' level, that is, becomes a stopped state after muting has been released. In such a way, leak-in of the timing clock after muting has been released can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a synthesizer tuner, and relates to one in which a clock signal for timing setting is stopped after muting is released.

[Conventional technology]

Generally, in a PLL (phase locked loop) synthesizer tuner, a high frequency signal from an antenna is converted into an intermediate frequency by a front end section 1, as shown in Fig. 1, and then amplified by an intermediate frequency amplifier section 2 and subjected to FM modulation. . Then, the output is supplied to an audio amplifier (not shown) through the MPXij [tuning section 3].

The front end section 1 forms a loop with a PLL circuit 4 including a programmable frequency divider, a reference starter 1 phase comparator, etc., and a low-pass filter 8, and operates a PLL controller according to operation input data from an operation section 7 to the PLL circuit 4. 5 provides data to the programmable frequency divider of the PLL circuit 4, thereby making it possible to receive the desired frequency.

The PLL controller 5 has a clock generator 6 that constantly oscillates at a reference frequency, and uses the clock from the clock generator 6 to generate PLL frequency division ratio data to be applied to the PLL circuit 4 at the clock timing. , the timing of various operations such as scan speed, etc.

[Problem to be solved by the invention]

However, with conventional PLL synthesizer tuners,
Since the clock generator 6 continues to oscillate even in the sound generation state after the muting output is canceled, the frequency of the timing clock is lower than the cutoff frequency of the low-pass filter 8 connected to the subsequent stage of the PLL circuit 4. , a problem arises in that the timing clock leaks into the tuning voltage applied to the front end section l as shown by the broken line arrow in FIG. That is, the tuning voltage is applied to a voltage-controlled variable capacitance diode (not shown) built in the front end unit 1, and is used to tune to a specific high-frequency signal from the antenna. If the timing clock leaks into this tuning voltage, it results in modulation of the tuning frequency, which causes deterioration of the SN ratio of the tuner.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to stop the clock signal after muting is canceled by controlling the operation of a clock generator that outputs a clock signal for timing setting in conjunction with the muting output.

[Means to solve the problem]

In order to achieve the above-mentioned object, the present invention provides a synthesizer tuner equipped with a clock generator that outputs a clock signal for timing setting, in which operations such as up/down of reception frequency, node switching, memory call, etc. is set by the operation input when the
A flip-flop that outputs a muting operation signal and starts the oscillation operation of the clock generator in the set state, and a clock signal that counts the clock signal from the clock generator in the set state of this flip-flop. The clock counter outputs a reset signal to the flip-flop when a set value is reached, and the oscillation and stop operations of the clock generator are controlled by the set and reset outputs of the flip-flop. It is characterized by this.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. Second
The figure shows the PLL controller 5 and operation section 7 in FIG.
6 is a clock generator that oscillates a timing clock used for timing control such as scan speed control data transfer, etc., and 11 is a clock generator that generates a reset pulse when the timing clock reaches a certain set number. 12 is an input interface circuit, 1B is a free clock counter that outputs
It's a whirlpool flop. The human power interface circuit 12 operates on the operating section 7, for example, by controlling the frequency knob down.

When a group of switches such as FM-AM band switching or memory call is operated, PLL operation data is generated according to the operation input data, and a set pulse is output to the flip-flop 13. Furthermore, the flip-flop 13 is connected to the human interface circuit 12.
When set by the set pulse from the clock counter 1, the clock generator 6 starts oscillating with a muting output of "H" level, while the clock counter 1
When reset by a reset pulse from 1, r
The oscillation of the clock generator 6 is stopped by the LJ level muting output.

Next, the effect will be explained. Now, when a group of switches such as frequency up/down, FM/AM band switching, etc. is operated on the operation unit 7, the input interface circuit I2 generates PLL operation data according to the operation input data, and also generates a set pulse. The output signal sets the flip-flop 13. Then, the muting output of the flip-flop 13 becomes rHJ level, so
The clock generator 6 starts oscillating. When the number of timing clocks from the clock generator 6 reaches a predetermined number, a set pulse is output from the clock counter 11, so that the flip-flop 3 is reset. Then, the muting output of the flip-flop I3 becomes rLJ level, so the clock generator 6 stops oscillating (see FIG. 3).

In this way, the clock generator 6 oscillates only while the muting output of the flip-flop 13 is at rHJ level, and stops when the muting output is at rLJ level, that is, after muting is released. Therefore, leakage of the timing clock after muting is canceled can be prevented.

〔Effect of the invention〕

As explained above, according to the present invention, the muting operation signal is set by the operation input from the operation unit, and the muting operation signal is output in the set state, and the output of the flip-flop is reset after a predetermined period of time has elapsed. Since the operation of the oscillator is controlled, the operation of the clock generator is stopped when the flip-flop is reset, that is, after muting is canceled, so it is possible to prevent timing clock leakage after muting is canceled. As a result, the SN ratio can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a synthesizer tuner, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG.
The figure is an explanatory diagram of the operation. 6... Clock generator, 7... Operation unit, 11
...Clock counter, 13...Flip-flop. Patent Applicant Pioneer Co., Ltd. Agent Patent Attorney Makoto Kobashi Ukiyoshi

Claims (1)

[Claims] In a synthesizer/tuner equipped with a clock generator that outputs a clock signal for timing settings,
a flip-flop that is set by an operation input when an operation such as up/down of the reception frequency, band switching, memory call, etc. is performed, and outputs a muting operation signal in the set state and starts the oscillation operation of the clock generator; , a clock counter that counts clock signals from the clock generator in the set state of the flip-flop and outputs a reset signal to the flip-flop when the clock signal reaches a certain set value, A synthesizer/tuner characterized in that the oscillation and stopping operations of the clock generator are controlled by the set and reset outputs of the clock generator.