JPH05196698A - Test pattern generator - Google Patents

Abstract

(57) [Summary] [Object] The present invention relates to a test pattern generator for converting a logical address on an algorithmic pattern generator into a physical address to generate a test pattern to be used when testing a semiconductor memory. The purpose is to mix and use different test methods in a pattern. [Structure] The selective conversion unit 12 selects a physical address and data converted from the pattern from the pattern generation unit 11 in accordance with a conversion rule according to a test mode to be used, and outputs it to the device under test 14 as a test pattern. The control unit 13 substantially switches the conversion rule in the selective conversion unit 12 according to the switching of the type of the test mode during the test.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test pattern generator, and more particularly to a test pattern for converting a logical address on an algorithmic pattern generator into a physical address to generate a test pattern for use in testing a semiconductor memory. Regarding the generator.

Many of dynamic random access memories (DARMs) and other semiconductor memories are externally written and read in order to be compatible with the same products of other companies and to be highly integrated to reduce the chip size. The instructed logical address is different from the physical address indicating the actual writing or reading position (cell) of the semiconductor memory.

Therefore, when testing such a semiconductor memory, a logic generated by an algorithmic pattern generator (ALPG) is used so that the addressing order position in the test pattern is not damaged. In order to make the address signal correspond to the physical address, it is necessary to convert the logical address to the physical address by using a scrambler RAM (SCRAM).

In addition to the normal test for sequentially writing the generated test pattern bit by bit and sequentially reading the bit data one bit at a time, the semiconductor memory test has been conducted in recent years for the purpose of improving testability. A so-called test mode test has also been adopted in which the test time is shortened by selectively writing and reading.

Since this test mode test differs from the normal test in the address decoding method, when both are used in the same test pattern in a mixed manner, the address descrambling information (conversion rule) is generated even while the pattern is being generated. It is necessary to switch in real time.

[0006]

2. Description of the Related Art FIG. 7 shows a block diagram of an example of a conventional test pattern generator. In the figure, a test pattern program is input to ALPG1, and a logical address signal and data X are generated in accordance with the test pattern program. The logical address signal and the data X are SCRA which is an address scrambler memory.
After being inputted to M2 and converted into a physical address and data A here, the device under test DUT (here, the semiconductor memory I
C) 3 is input as a test pattern.

[0007]

However, in the above-mentioned conventional apparatus, the SCRAM 2 is of one type, although the normal test and the test mode test described above have different conversion rules for converting a logical address into a physical address. Therefore, the same conversion rule must be used until the end of the test.

On the other hand, the semiconductor memory test includes a normal test and a test mode test as described above. Writing to the semiconductor memory is faster than the test mode test by writing in the test mode test in a short time. The test time can be shortened by applying the test. However, in the above conventional device, since the SCRAM 2 is of one type, writing and reading can be performed only in the same test, and therefore the normal test and the test mode test cannot be mixed.

The present invention has been made in view of the above points,
An object of the present invention is to provide a test pattern generator that solves the above problems by selecting SCRAM for each test.

[0010]

FIG. 1 shows a block diagram of the principle of the present invention for achieving the above object. The present invention is configured to generate a test pattern for the device under test 14 by the pattern generation unit 11, the selection conversion unit 12, and the control unit 13.
Here, the pattern generator 11 generates a pattern composed of a logical address and data according to an input program.
The selective conversion unit 12 selects the physical address and data converted according to the conversion rule according to the test mode using the pattern from the pattern generation unit 11 and outputs the selected physical address and data to the DUT 14 as a test pattern. The control unit 13 substantially switches and controls the conversion rule in the selective conversion unit 12 in accordance with the switching of the type of the test mode during the test of the device under test 14.

[0011]

According to the present invention, the selective conversion unit 12 is controlled by the control signal from the control unit 13 so that the logical address and the data from the pattern generation unit 11 are physically converted by the conversion rule according to the selected test mode among the plurality of test modes. Since the data can be converted into the address and the data, the pattern execution address of the test mode to be switched in the test pattern is stored in the control unit 13 and the conversion rule is switched when the test pattern encounters the cycle. As a result, a test in another test mode can be performed in real time even while the test pattern is being executed.

[0012]

FIG. 2 shows a block diagram of an embodiment of the present invention. In the figure, the same components as those in FIG. 1 are designated by the same reference numerals. In FIG. 2, the ALPG 21 is a pattern generator 1
In the algorithmic pattern generator constituting 1, a test pattern program shown in FIG. 3, which will be described later, is input to generate a pattern composed of a logical address and data.

Also, the first multiplexer (MUX) 2
2, the SCRAMs 23 and 24, and the second multiplexer (MUX) 25 form the selection conversion unit 12, and the register 26 forms the control unit 13. The multiplexers (MUX) 22 and 25 perform a selection operation according to the control signal from the register 26.

The SCRAM 23 is a first address scrambler memory for converting the physical address and data according to the first conversion rule for normal test, and the SCRAM 24.
Is a second address scrambler memory for converting into a physical address and data according to the second conversion rule for the test mode test. The output signal of MUX22 is directly MUX
25 is input to the MUX 25 through the SCRAMs 23 and 24 separately. Further, the DUT 27 is, for example, a 4M DRAM here.

Next, the operation of this embodiment will be described. First, a test pattern program is input to the ALPG 21, and the ALPG 21 generates a logical address and data based on this. Here, as shown in FIG. 3, the above-mentioned test pattern program includes a program part a indicating that the first SCRAM 23 is used, and a DUT (4MDR in this case).
AM) 27, a program section b for instructing to write the checkerboard in all bits based on the test mode test method, a program section c for using the second SCRAM 24, and a checkerboard for all bits of the DUT 27. And a program section d for instructing to read according to the normal test method are combined in time series. The program is executed in the order of a, b, c and d described above.

The register 26 shown in FIG. 2 stores in advance the execution addresses of the program parts a and c. As a result, when the ALPG 21 first executes the program section a, the MUXs 22 and 25 are switched and controlled based on the addresses stored in advance in the register 26 which operates based on the clock synchronized with the execution cycle of the test pattern. Input signal is SCRAM24
The signal supplied from the SCRAM 24 to the MUX 25 is output to the DUT 27. The ALPG 21 performs a pause operation by executing the program section a.

Subsequently, the program section b is executed by the ALPG 21, and the logical address and data to be written into the all-bit checker board are written in A by the test mode test method.
It is generated by the LPG 21. The logical address and the data X are selectively input to the SCRAM 24 by the MUX 22,
Here, the physical address and data A'for the test mode test
After being converted to, it is input to the DUT 27 through the MUX 25 and written. Here, when the DUT 27 is a 4M DRAM, the above test mode test is performed with reference to FIGS.
As indicated by "1" in (A), 4096 bits in the X direction, Y
In the direction 1024-bit memory cell array 41, the data of the value "1" is simultaneously written in the illustrated 8-bit address position. Hereinafter, in the same manner as described above, for example, if the increment in the X address direction is made, 4MDRA is sequentially performed in the order shown by “2”, “3”, and “4” in FIG.
Data is written in each 8-bit position of the M memory cell array 41.

At this time, the odd-numbered order "1", "3"
When the value of the data written in the case of ... Is "1" and the value of the data written in the even-numbered order "2", "4", ... Is "0", the memory cell array 4
A checkerboard as schematically shown in FIG. The SCRAM 24 converts and outputs the physical address and the data so that the data is written to the physical address corresponding to the logical address of the DUT 27.

In this case, since each data is simultaneously written in 8-bit units, the write time (test time) can be greatly shortened as compared with the case of writing the data bit by bit as in the normal test method. .

Subsequently, the ALPG 21 performs a pause operation by executing the program section c shown in FIG.
Since the pattern cycle coincides with the address previously stored in 6, the input signal of the MUX 22 is selectively input to the SCRAM 23, and the signal supplied from the SCRAM 23 to the MUX 25 is output to the DUT 27.
2 and 25 are switch-controlled.

After that, the program section d in FIG.
It is executed by the PG 21 and a logical address for reading data from all bits is generated by the normal test method. This logical address X is sent to SCRAM23 through MUX22.
And is converted into a physical address A for normal testing. The physical address A extracted from the SCRAM 23 is supplied as a read address to the DUT 27 through the MUX 25.

Here, in the above-mentioned normal test, when the DUT 27 is a 4 MRAM as described above, an address is designated bit by bit for each bit of the memory cell array 41 as shown in FIG. 6A, for example, in the order shown. Then, write and read data to test. Although data is read by a normal test here, a 2 × 2 checkerboard as schematically shown in FIG. 6B is written in the memory cell array 41 by the test mode test method as described above. Therefore, the above-mentioned data reading by the normal test method is determined as a non-defective product when "1" and "0" are alternately read, assuming that the increment is made in the X address direction.

The present invention is not limited to the above-mentioned embodiment. For example, the MUX 22 is not provided, and the ALPG2 is not provided.
One output signal may be constantly supplied to both SCRAMs 23 and 24, and the MUX 25 may select one of them. It is also possible to test by changing the condition of the power supply voltage of the DUT 27.

[0024]

As described above, according to the present invention, a test in another test mode can be performed in real time even during the execution of the test pattern. Therefore, a plurality of test modes can be appropriately mixed depending on the characteristics of the device under test. It has features such that it can be tested and can be tested with higher accuracy depending on the device under test.

[Brief description of drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a block diagram of an embodiment of the present invention.

FIG. 3 is a diagram showing an example of a test pattern program used in FIG.

FIG. 4 is a diagram illustrating a relationship between a 4DRAM memory cell array and a write address.

FIG. 5 is a diagram illustrating a test mode test method.

FIG. 6 is a diagram illustrating a normal test method.

FIG. 7 is a block diagram of a conventional example.

[Explanation of symbols]

11 pattern generation unit 12 selective conversion unit 13 control unit 14 device under test 21 algorithmic pattern generator (AL
PG) 22,25 Multiplexer (MUX) 23,24 Scrambler RAM (SCRAM)

Claims (2)

[Claims] 1. A pattern generator (11) for generating a pattern consisting of a logical address and data according to an input program, and a pattern from the pattern generator (11) is converted according to a conversion rule according to a test mode to be used. A selection conversion unit (12) that selects the physical address and data and outputs it as a test pattern to the device under test (14), and according to the switching of the test mode type during the test of the device under test (14). And a control unit (13) that substantially controls switching of the conversion rule in the selective conversion unit (12). 2. The first conversion unit (12) outputs a pattern from the pattern generation unit (11) to any one of a plurality of output transmission lines.
And a first address scrambler memory for receiving a pattern from the first multiplexer (22) via the first output transmission line as an input signal and converting the pattern into a physical address and data according to a first conversion rule. (23) and a second address scramble for receiving the pattern from the first multiplexer (22) through the second output transmission path as an input signal and converting it into a physical address and data according to a second conversion rule. And a second one for selecting one of the physical address and data from the first and second address scrambler memories (23, 24) and outputting it to the device under test (27). A test pattern generator according to claim 1, characterized in that it comprises a multiplexer (25) of