JPH05197628A - Semiconductor memory device - Google Patents

Abstract

(57) [Summary] [Structure] A writable / unwritable information storage element 22 for storing writable information or writable information for the word line 11.
And the word line 11 selected by the row decoder 13
And a write enable / disable determining means 18 for outputting a write enable / disable signal to the write circuit 29 in accordance with the information stored in the write enable / disable information storage element 22 regarding the selected word line 11. A semiconductor memory device in which the write circuit 29 does not output a data signal when storing prohibition information. [Effect] It is possible to prevent erroneous writing of data to a specific memory area (write-protected area) used as a ROM due to a malfunction of the CPU, etc., and reliability is improved. The setting of the write-protected area in the memory area depends on the amount of ROM data to be stored in the write-protected area, etc.
It is flexibly executed in arbitrary units for each at least one word line 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, the present invention relates to a nonvolatile read / write memory (hereinafter referred to as “nonvolatile RWM”) that can be used as a dedicated memory (hereinafter referred to as “ROM”) for reading out a part of the memory area.

[0002]

2. Description of the Prior Art Nonvolatile RWM is
Since the written data can be retained, by storing the data (ROM data) that should be originally stored in the ROM in a part of the memory area of the nonvolatile RWM,
It is possible to use a part of the memory area instead of the ROM. In this case, after the ROM data is stored in the memory area used instead of the ROM, it is necessary to prevent other data from being written in that area.

According to the prior art, the determination as to whether data writing is prohibited or writable in a specific memory area is executed by external control by the CPU based on a program. Therefore, if there is a bug in the program, or if noise occurs during control and the CPU runs away or malfunctions due to it, the memory area used in place of the ROM will be erroneous. Then, the data is written and the ROM data is erased.

Japanese Unexamined Patent Publication No. 3-129446 discloses an area designating means (write enable area register) for generating an area designating signal for designating a write-enabled area and a write-protected area of an EEPROM area in accordance with information from an address bus. ,
EE having a writing area designated by the area designation signal and an area designated by data from the address bus, and discriminating the data writing to the EEPROM when these two areas do not match.
A computer with a built-in PROM is disclosed.

Further, Japanese Patent Laid-Open No. 2-2435 discloses a rewrite prohibition circuit for preventing application of a high voltage required for a rewrite operation to a rewrite prohibition area in order to prohibit rewrite of some memory cells. A semiconductor nonvolatile memory device having the same is disclosed. The operation of the rewrite prohibition circuit is controlled by the potential of the external input terminal connected to the rewrite prohibition circuit.

Further, Japanese Patent Application Laid-Open No. 62-202395 discloses a semiconductor integrated circuit device having a write protection signal input terminal, and a specific method is performed while the write protection signal is input from the write protection signal input terminal. A semiconductor integrated circuit having a decoder that does not output a row selection signal for addressing is disclosed.

Further, Japanese Patent Laid-Open No. 61-271687 discloses a magnetic bubble cassette having a plurality of memory blocks, in which a means for generating a designation signal for designating write or write prohibit for each memory block and a write command are provided. There is disclosed a magnetic bubble cassette which is provided with means for detecting a write-prohibited designation signal when given, and which does not write when the write-prohibited designation signal is detected. The designation of writing and the designation of writing prohibition are executed by switch switching.

[0008]

However, the above-mentioned conventional technique has the following problems.

In the EEPROM built-in computer disclosed in Japanese Patent Laid-Open No. 3-129446, means for comparing a write area specified by an area specifying signal with an area specified by data from an address bus (area determining circuit) ), It is necessary to decode the data from the address decoder and output the address space identification signal. There is a disadvantage that an address decoder for this purpose is required separately from the EEPROM address decoder.

In the semiconductor nonvolatile memory device disclosed in Japanese Patent Application Laid-Open No. 2-2435, since the operation of the rewrite inhibit circuit is controlled by the potential of the external input terminal connected to the rewrite inhibit circuit, writing to a certain address is performed. There is a drawback in that a circuit for determining whether to permit is required outside the semiconductor memory device.

Since the semiconductor integrated circuit device disclosed in Japanese Unexamined Patent Publication No. 62-202395 has a configuration in which a row selection signal is not output for a specific address, writing to a bit selected in a certain cycle is not possible. When it is prohibited, it has a drawback that reading from that bit is impossible.

In the magnetic bubble cassette disclosed in Japanese Patent Laid-Open No. 61-271687, since writing and writing inhibition are designated in block units, it is not possible to designate writing inhibition in smaller units. have.

The present invention has been made in order to solve the above problems, and an object of the present invention is to make a mistake in a specific memory area used in place of a ROM due to a malfunction of a CPU or the like. Another object of the present invention is to provide a highly reliable semiconductor memory device in which writing of data can be surely prevented.

Another object of the present invention is to set the area in which writing is prohibited in the memory area in accordance with the amount of ROM data to be stored in the memory area (write-inhibiting area) used as a ROM. It is to provide a semiconductor memory device that can be flexibly executed in arbitrary units.

[0015]

A semiconductor memory device of the present invention includes a row decoder which receives a row address signal and outputs a row selection signal in accordance with the row address signal, and a row decoder which is connected to the row decoder. A word line for receiving a signal, a column decoder for receiving a column address signal and outputting a column selection signal in response to the column address signal, and connected to the column decoder,
A switching element that receives the column selection signal and opens / closes according to the column selection signal, a writing circuit that outputs a data signal according to external input data, and a writing circuit that is connected to the writing circuit through the switching element. What is claimed is: 1. A semiconductor memory device comprising: a bit line for receiving the data signal from a circuit; and a memory cell connected to the word line and the bit line, further comprising writable information or write inhibit information for the word line. Is connected to the write enable / disable information storage element, the write enable / disable information storage element, and the write circuit, and stores the write enable / disable information storage element for the word line selected by the row decoder in accordance with the information stored by the write enable / disable information storage element. And a write enable / disable determining means for outputting a write enable / disable signal to the write circuit, wherein the write enable / disable information storage element has the write enable / disable information. When 該書 lump circuit a write permission signal output from the 該書 included possibility determining section receives the case of storing only prohibition information, 該書 inclusive circuit by not outputting the data signals, to achieve the above object.

The write enable / disable information storage element is an element capable of assuming two states, a conductive state and a non-conductive state, and the write enable / disable determining means is the write enable / disable for the word line selected by the row decoder. The write enable / disable signal may be output to the write circuit according to the two states of the information storage element.

The write enable / disable determining means is connected between the signal line, the write enable / disable information storage element and the signal line, and when the word line is selected by the row decoder, the selected word line And a potential change means for changing the potential of the signal line according to the two states of the conducting state and the non-conducting state stored in the writable information storage element, and the signal line. And a write enable / disable signal output means for outputting the write enable / disable signal in accordance with the changed potential.

The write enable / disable information storage element may store the write enable information or the write disable information for each of the word lines.

The writable / unwritable information storage element may store the writable information or the writable prohibition information for each of a plurality of word line groups including at least two word lines among the word lines.

Another semiconductor memory device of the present invention is a row decoder which receives a row address signal and outputs a row selection signal in response to the row address signal, and a word which is connected to the row decoder and receives the row selection signal. A line and a column decoder which receives a column address signal and outputs a column selection signal according to the column address signal, and a switching which is connected to the column decoder, receives the column selection signal, and opens / closes according to the column selection signal An element, a write circuit for outputting a data signal according to external input data, a bit line connected to the write circuit via the switching element and receiving the data signal from the write circuit, the word line and the bit A memory cell connected to a line, wherein the column decoder has writable information or write information for the bit line. Write enable / disable information storage element for storing stop information, and write enable / disable determination for changing the output level of the row select signal according to the information stored in the write enable / disable information storage element for the bit line selected by the column decoder. And means.

[0021]

EXAMPLES The present invention will be described below with reference to examples.

The semiconductor memory device of the first embodiment is shown in FIG.
As shown in (a), it has a plurality of memory blocks. As shown in FIG. 7B, each memory block has a plurality of row decoders 13, a plurality of column decoders 14, and a plurality of write circuits 29. Each writing circuit 2
Reference numeral 9 is connected to an input / output buffer (not shown).

Next, referring to FIG. 1, an outline of the structure of the main part of the first embodiment will be described. The semiconductor memory device of this embodiment has a row decoder 13 that outputs a row selection signal in response to a row address signal, a row selection signal line (word line) 11 connected to the row decoder 13, and a column address signal. A column decoder 14 that outputs a column selection signal, a switching element 140 that opens and closes according to the column selection signal, and a terminal 2
A write circuit 29 that outputs a data signal to a common data line (I / O line) 26 in accordance with external input data input to 5
And a bit line 21 connected to the common data line 26 of the write circuit 29 through the switching element 140, and a word line 11 and a memory cell (memory cell) 15 connected to the bit line 21. Although only one memory cell 15 connected to a specific word line 11 and bit line 21 is shown in FIG. 1, in reality, a plurality of word lines 11 and a plurality of bit lines 21 are shown.
A memory cell 15 is formed at each of the intersecting points.

The word line 11 receives a row selection signal from the row decoder 13. That is, the potential of the selected word line 11 is changed by the row decoder 13. The bit line 21 receives a data signal from the common data line 26 of the write circuit 29 when the switching element 140 is opened (ON state) by the column decoder 14. In general, the column decoder 14 and the switching element 140 of this embodiment may be collectively referred to as a “column decoder”, but they are described separately in this specification. The bit line 21 is connected to a sense amplifier (not shown) as in the known semiconductor memory device.

The semiconductor memory device further includes a write enable / disable information storage element 22 for storing write enable information or write disable information for each word line 11, and a write enable / disable status connected to the write enable / disable information storage element 22 and the write circuit 25. The determination means 18 is provided.

The write enable / disable determining means 18 is the row decoder 1
A write enable / disable signal is output to the write circuit 29 via the write enable / disable signal line 23 in accordance with the information stored in the write enable / disable information storage element 22 for the word line 11 selected by 3. The write circuit 29 stops outputting the data signal in response to the write enable / disable signal.

The write enable / disable information storage element 22 of this embodiment
Is an element that can be in two states, a conducting state and a non-conducting state. In the present embodiment, the word line 11 for which writing is prohibited is set to the conductive state, and the word line 11 for which writing is not prohibited is set to the non-conductive state. The writability determination means 18 is
A write enable / disable signal is output to the write circuit 29 according to two states of the write enable / disable information storage element 22 for the word line 11 selected by the row decoder 13.

More specifically, the write enable / disable determining means 18
Is the signal line 27, the write enable / disable information storage element 22 and the potential changing means 20 connected to the signal line 27, and the signal line 27.
And a write enable / disable signal output means 28 connected to the. When the word line 11 to which the potential changing means 20 is connected is selected by the row decoder 13, each potential changing means 20 is in a conductive state stored in the write enable / disable information storage element 11 for the selected word line 11. And the potential of the signal line 27 is changed according to the two states of non-conduction and non-conduction. The write enable / disable signal output means 28 outputs a write enable / disable signal according to the changed potential of the signal line 27. This write enable / disable signal is used as the write enable / disable signal line 23.
Is output to. A means 19 for biasing or precharging the signal line 27 is connected to the signal line 27.

The semiconductor memory device of this embodiment further includes a NAND circuit 31 in which the write enable signal line 24 and the write enable / disable signal line 23 are connected to the input terminal and the output terminal is connected to the write circuit 29.

Next, the circuit configuration of the first embodiment will be described with reference to FIG. The writable / unwritable information storage element 22 of this embodiment is a fuse that can be in two states, a conductive state and a non-conductive state. As described above, in this embodiment, the fuse for the word line 11 for which writing is prohibited is set to the conductive state. The fuse for the word line 11 in which writing is not prohibited is set to the non-conducting state. In order to make the fuse non-conductive, a part of the fuse may be cut using a laser trimmer or the like. When manufacturing a semiconductor memory device including a redundant circuit having a fuse, a step of cutting a part of the fuse is performed, and therefore, a part of the fuse, which is the write enable / disable information storage element 22, is also cut in the step. Therefore, the manufacturing process does not increase.

The potential changing means 20 of this embodiment is a MOSFET whose gate is connected to the word line 11. M
One of the source / drain of the OSFET is connected to one end of a fuse which is the write enable / disable information storage element 22. The other of the source / drain of the MOSFET is connected to the signal line 27. The signal line 27 of the present embodiment is a high level (hereinafter, referred to as the signal line 27 via the resistor 49.
Power supply (not shown) that supplies "H level" potential
It is connected to the. The other end of the fuse is grounded.

When the word line 11 is selected by the row decoder 13 in response to the row address signal transmitted via the row address signal line 10 (when the potential of the word line 11 rises to H level), the selection is performed. Potential change means (MOSFET) connected to the word line 11
20 is turned on, and the channel of the MOSFET becomes conductive. Therefore, when the fuse for the selected word line 11 is conductive, the resistor 49, the signal line 27,
A current flows from the power supply to the ground through the potential changing means (MOSFET) 20 and the fuse. At this time, due to the voltage drop due to the resistor 49, the potential of the signal line 27 is significantly lower than the potential (for example, 5 V) supplied by the power source, and changes to the Low level (hereinafter referred to as “L level”). In other words, the potential of the signal line 27 is pulled down to the L level.

In this way, when the potential of the signal line 27 is lowered to the L level, the L level signal amplified by the two-stage inverter which is the write enable / disable signal output means 28 becomes the NAND circuit 31 as the write enable / disable signal (write disable signal). It is output to one terminal.

As a result, even if the write enable signal of H level passes through the write enable signal line 24, the NAN
Even if it is applied to the other terminal of the D circuit 31, as long as the L level write enable / disable signal is applied to the one terminal of the NAND circuit 31, the external input data (write signal) is transmitted through the common data line 26. It is not output from the writing circuit 29. Thus, external input data is not transmitted to the bit line 21 selected by the column decoder 14 according to the column address signal transmitted through the column address signal line 9. Therefore, the memory cell 1 connected to the selected word line 11 and the selected bit line 21
No data is written to the data of No. 5.

On the other hand, when the word line 11 is selected by the row decoder 13 (when the potential of the word line 11 rises to the H level), if the fuse for the selected word line 11 is in the non-conducting state, the current flows. Does not flow from the power supply to the ground through the fuse, the resistor 49, the potential changing means (MOSFET) 20 and the signal line 27.
At this time, the voltage drop due to the resistor 49 does not occur. Therefore, the potential of the signal line 27 is maintained at the H level.

In this way, when the potential of the signal line 27 is maintained at the H level, the H level signal amplified by the two-stage inverter which is the write enable / disable signal output means 28 becomes the write enable / disable signal (write enable signal) NAND. Circuit 31
It is output to one terminal. As a result, the H-level write enable signal is transferred to the N level via the write enable signal line 24.
When applied to the other terminal of the AND circuit 31, the external input data is output from the write circuit 29 via the common data line 26. In this way, the external input data is transmitted to the bit line 21 selected by the column decoder 14.
Therefore, the data writing is executed to the memory cells connected to the selected word line 11 and the selected bit line 21.

As described above, according to the present embodiment, it is possible to prevent erroneous writing of data to a specific memory area used in place of the ROM due to a malfunction of the CPU or the like, thereby improving reliability. .. In addition, the setting of the area where writing is prohibited in the memory area is executed for each word line according to the amount of ROM data to be stored in the memory area (write-inhibiting area) used as a ROM. It

A resistor 4 is provided between the power supply and the signal line 27.
Instead of 9, a switching element may be provided. In the improved embodiment having a switching element instead of the resistor 49, the switching element is turned on and precharge to the signal line 27 is performed before the selection of the word line 11 is performed. When the word line 11 is selected, the switching element is turned off, and the potential of the signal line 27 can take a value independent of the potential of the power supply. Thus, also in this improved example, the state in which the writability information storage element 22 is stored is detected in accordance with the potential of the signal line 27 in the same manner as the operation of the above-described embodiment.

In this embodiment, in each memory block, the plurality of potential changing means 20 corresponding to each of the plurality of word lines 11 belonging to the memory block are connected to each other via one extended signal line 27. Writability determination means 18
It is connected to the. The numbers of the signal lines 27 and the write enable / disable determining means 18 can be changed to arbitrary values according to the design. Further, the number of write circuits 29 in this embodiment is one for one memory block, but the number may be two or more for one memory block.

In this embodiment, the fuse is "non-conducting".
Corresponds to the storage of "writable information", the "conduction state" of the fuse corresponds to the storage of "write-prohibited information", but the "non-conduction state" of the fuse corresponds to the storage of "write-prohibited information" However, this embodiment may be improved so that the “conduction state” of the fuse corresponds to the storage of the “writable information”. Such improvement can be achieved by replacing the number of stages of the inverter, which is the write enable / disable signal output means 28, with two stages instead of two stages of this embodiment. In the improved example thus obtained, for example, when the potential of the signal line 27 is lowered to the L level, the H level signal amplified by the three-stage inverter that is the write enable / disable signal output means 28 becomes the write enable / disable signal (write enable signal). ) Is output to one terminal of the NAND circuit 31.

FIG. 3A shows a main part (write enable / disable information storage element 22) of the second embodiment of the present invention. The main difference between this embodiment and the first embodiment is that the write enable / disable information storage element 22 in this embodiment is a MOSFET that can have two states having different inversion threshold voltages. .. In the present embodiment, the MOSFETs in the row in which writing is prohibited are set to have a low inversion threshold voltage. The MOSFETs in the rows where writing is not prohibited are set to a state where the inversion threshold voltage is high.
The control of the inversion threshold voltage of the MOSFET is performed by adjusting the doping level (impurity concentration) performed on the channel region of the MOSFET. More specifically, conductivity type impurity ions for increasing the inversion threshold voltage are selectively implanted into the channel region of the MOSFET in which the inversion threshold is to be increased. At the time of this ion implantation, at least the channel portion is covered with an ion implantation mask (typically, a photoresist mask) so that impurity ions are not implanted into the channel region of the MOSFET for which the inversion threshold should be lowered. According to the present embodiment, the threshold voltage of the desired MOSFET can be controlled by the ordinary lithography process and ion implantation process, so that the write enable / disable information storage element 22 stores the write enable / disable information for any word line 11. Can be done easily.

The MOSFET which is the write enable / disable information storage element 22 in this embodiment also serves as the potential changing means 20. That is, the gate of the MOSFET is connected to the word line 11, one of the source / drain is grounded, and the other of the source / drain is connected to the signal line 27.

With such a configuration, when the word line 11 is selected by the row decoder 13 (when the potential of the word line 11 rises to H level), the MOSFET connected to the selected word line 11 is selected. When the inversion threshold is low, the MOSFET channel is conducting.
Therefore, a current flows from the power supply to the ground through the resistor 49, the signal line 27 and the MOSFET, and the potential of the signal line 27 is pulled down.

On the other hand, when the word line 11 is selected by the row decoder 13, the selected word line 1
If the inversion threshold of the MOSFET connected to 1 is high,
The MOSFET channel is not conducting. Therefore, resistor 4
No current flows from the power source to the ground through the signal line 27 and the MOSFET 9, and the potential of the signal line 27 is maintained at the H level. In other words, in order to make the MOSFET non-conductive, even if the gate potential rises to the potential of the selected word line 11 (for example, about 5 volts), the MOSFET is not turned on. M
It is necessary to adjust the inversion threshold of the OSFET.

According to this embodiment, the writability information storage element 22 can be formed by utilizing the process of forming the MOSFET forming the normal circuit of the semiconductor memory device. In comparison, there is an advantage that the manufacturing process is simplified.

FIG. 3B shows the main part of the third embodiment of the present invention. The main difference between this embodiment and the first embodiment is that the write enable / disable information storage element 2 in this embodiment is different.
2 is a floating gate type EEPROM device (FAMO which can take two states, a conducting state and a non-conducting state.
S). In the present embodiment, the elements in the row where writing is prohibited are set to the conductive state (state where the inversion threshold voltage is low). The FAMOS element for the row where writing is not prohibited is set to the non-conducting state (state where the inversion threshold voltage is high). The control of the inversion threshold voltage of the FAMOS is executed by adjusting the potential of the floating gate of the FAMOS. Electrons are injected into the floating gate by grounding the source terminal 222 of the FAMOS and applying a predetermined high voltage to the control gate terminal 221. On the other hand, by grounding the control gate terminal 221 and applying a predetermined high voltage to the source terminal 222, electrons are emitted from the floating gate. By both of the above operations, it is possible to repeatedly change the inversion threshold of FAMOS.

As described above, according to this embodiment, it is possible to change the two states of the writable / non-writable information storage element 22, which are the conducting state and the non-conducting state, as necessary. Therefore, to set or change the write-protected area,
This is flexibly executed according to the amount of ROM data to be stored in the memory area (write-protected area) used as the OM.

FIG. 4 shows a fourth embodiment. The main difference between this embodiment and the first embodiment is that one write enable / disable information storage element 22 stores write enable / disable information for two word lines 11. That is, when the write enable / disable information storage element 22 shown in the figure stores the write inhibit information, the row decoder 1 receives the row address signal transmitted through the row address signal line 10.
When any one of the two word lines 11 shown by 3 is selected (when the potential of the node 101 becomes H level), the write circuit (FIG. 4) is performed similarly to the operation of the first embodiment. Memory cells connected to the selected word line 11 (see FIG. 4) do not generate a data signal.
No data is written to (not shown).

According to this embodiment, there is an advantage that the area occupied by the write enable / disable information storage element 22 on the chip is reduced. Although one writable / unwritable information storage element 22 of this embodiment stores writable / unwritable information about two word lines 11, writable / unwritable information about an arbitrary number of three or more word lines 11 is stored. May be stored. Therefore, the setting of the area where writing is prohibited in the memory area depends on the amount of ROM data to be stored in the memory area (write-inhibiting area) used as a ROM, at least every two word lines, Flexible execution in arbitrary units.

FIG. 5 shows the main part of the fifth embodiment. The semiconductor memory device of this embodiment is different from all the above-described embodiments in that the write enable / disable information storage element 22 for storing the write enable information or write disable information for the bit line 21 and the bit line selected by the column decoder 14 are used. The column decoder 14 is provided with a write enable / disable determining unit 180 that changes the output level of the column select signal according to the information stored in the write enable / disable information storage element 22 for the column 21. For reference, a corresponding portion of the conventional semiconductor memory device is shown in FIG. As shown in FIG. 6, in the conventional semiconductor memory device, each column decoder 14 connected to the column address signal line 9 (only one column decoder is shown in FIG. 6). ) Outputs a column selection signal to the column selection signal line 37 in response to the column address signal. The column selection signal line 37 is connected to the gate of the switching element 140 provided between the data common line 26 and the bit line 21. The main difference between this conventional semiconductor memory device and this embodiment is that the column decoder 14 of this embodiment is
The permission / prohibition information storage element 22 and the write permission / prohibition determination means 18 described above
And are provided. This embodiment will be described below with reference to FIG.

In the semiconductor memory device of this embodiment, a row decoder 13 that outputs a row selection signal according to an address signal, a word line 11 connected to the row decoder 13, and a column selection signal according to a column address signal. A column decoder 14 for outputting to the column selection signal line 37, a switching element 140 connected to the column selection signal line 37, a common data line (I / O line) 26 for transmitting a data signal according to external input data,
The bit line 21 is connected to the common data line 26 via the switching element 140, and the memory cell 15 is connected to the word line 11 and the bit line 21.

The column decoder 14 of this embodiment has a write enable / disable information storage element 22 for storing write enable information or write disable information for four bit line pairs and a write operation for the bit line 21 selected by the column decoder 14. The write enable / disable determining unit 180 that changes the output level of the row selection signal according to the information stored in the enable / disable information storage element 22.

More specifically, the writability information storage element 22 of this embodiment is a fuse, like the writability information storage element 22 of the first embodiment. As the writability information storage element 22, as described above, the fuse, the MOSF
Either ET or EEPROM may be used.

The write enable signal line 24 is connected to the gate of the MOSFET in the write enable / disable determining means 180. One of the source / drain of the MOSFET is connected to a power supply via a fuse (write enable / disable information storage element 22) and a resistor 190. The other of the source / drain is connected to the node 29 in the column decoder 14.
The output of the inverter 280, whose input is connected between the resistor 190 and the fuse, and the node 29 are both NOR
It is connected to the input of circuit 290. This NOR circuit 2
The output of 90 is connected to the column selection signal line 37.

The operation of this embodiment will be described below. During the write cycle, the column address transmitted via the three column address signal lines 9 connected to the illustrated column coder 14 to select the four bit line pairs shown. When all of the signals go to H level, the node 29 in the column decoder 14 goes to L level. At this time, the fuse (writability information storage element 2
When 2) is in the non-conducting state, the input of the inverter 280 is maintained at the H level by the power supply, so that the L level signal is applied to both inputs of the NOR circuit 290. This application applies when the write enable signal transmitted via the write enable signal line 24 is at H level and L level.
Not affected by any of the levels. Therefore, the column selection signal output from the column decoder 14 to the column selection signal line 37 becomes H level. That is, when the H level write enable signal is input to the write circuit (not shown in FIG. 5), the column decoder 14 for the selected bit line 21 outputs the H level signal to the column selection signal line 37. Then, the switching element 140 is turned on. Therefore, data writing is executed to the memory cells 15 connected to the four bit line pairs to be selected.

On the other hand, when the fuse (write enable / disable information storage element 22) is conductive, the write enable signal line 2
When the write enable signal transmitted via signal No. 4 is at the L level, the input of the inverter 280 is maintained at the H level by the power supply, so that the L level signal is applied to both of the two inputs of the NOR circuit 290. It As a result, the column selection signal output from the column decoder 14 to the column selection signal line 37 becomes H level.

When the write enable signal is at the H level, the MOSFET in the write enable / disable determining means 180 is rendered conductive, so that the input of the inverter 280 is pulled down to the potential (L level) of the node 29. When the input potential of the inverter 280 becomes L level, the inverter 280
Output becomes H level. As a result, the column selection signal output from the column decoder 14 to the output node 37 becomes L level. That is, when the H level write enable signal is input to the write circuit (not shown in FIG. 5),
The column decoder 14 for the bit line 21 to be selected outputs an L level signal to the column selection signal line 37 to turn off the switching element 140. Therefore, no data is written to the memory cell 15 connected to the eight bit lines 21 to be selected.

According to this embodiment, when the write enable / disable information storage element 22 of the four bit line pairs to be selected according to the column address signal stores the write inhibit information, the column decoder No column selection signal is output from 14. Therefore, the data signal transmitted via the common data line 26 of the write circuit (not shown in FIG. 5) is not transmitted to the four bit line pairs to be selected.

The write enable / disable information storage element 22 of this embodiment.
Is provided for each column selection signal line 37 connected to each column decoder 14, but a plurality of column selection signal lines 37 are provided.
One writability information storage element 22 may be provided. In addition, the semiconductor memory device of the present embodiment is 1
The column decoder 14 has a configuration capable of connecting a plurality of (8) bit lines 21 to the common data line 26. However, the bit line 2 connected to one column decoder 14
The number of 1 is arbitrary.

According to the present embodiment, it is possible to prevent data from being erroneously written in a specific memory area used in place of the ROM due to a malfunction of the CPU, so that the reliability is improved. In addition, the setting of the area in which writing is prohibited in the memory area depends on the amount of ROM data to be stored in the memory area (write-inhibiting area) used as a ROM, at least for each bit line, Flexible execution in arbitrary units.

Although the write enable / disable information storage element 22 of this embodiment is provided for each node 37 from which the column decoder 14 outputs a column selection signal, it is provided for each group of a plurality of nodes 37. Good.

[0062]

As described above, according to the present invention, it is possible to prevent erroneous writing of data to a specific memory area used in place of a ROM due to a malfunction of a CPU, etc., and improve reliability. To do. In addition, the setting of the area where writing is prohibited in the memory area depends on the amount of ROM data to be stored in the memory area (write-inhibiting area) used as a ROM, at least for each word line or Flexible execution is performed in arbitrary units at least for each bit line.

Further, since the semiconductor memory device in which the RAM and the ROM are mixed in one chip is provided by the relatively simple structure, the mounting area of the computer board can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing an outline of a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a circuit diagram of the first embodiment shown in FIG.

FIG. 3A is a diagram showing a write enable / disable information storage element included in the second embodiment of the present invention, and FIG. 3B is a write enable / disable information storage element included in the third embodiment of the present invention. FIG.

FIG. 4 is a diagram showing an outline of a configuration of a fourth exemplary embodiment of the present invention.

FIG. 5 is a diagram showing a schematic configuration of a fifth embodiment of the present invention.

FIG. 6 is a diagram showing an outline of a portion corresponding to the configuration shown in FIG. 5 in a conventional semiconductor memory device.

FIG. 7A is a diagram showing a memory block included in the first embodiment of the present invention, and FIG. 7B is a diagram showing a schematic plan layout of the memory block.

[Explanation of symbols]

 9 column address signal line 10 row address signal line 11 word line (row selection signal line) 13 row decoder 14 column decoder 15 memory cell 18 write enable / disable determining means 20 potential changing means 21 bit line 22 write enable / disable information storage element 23 write enable / disable signal Line 24 Write enable signal line 25 Terminal 26 Common data line (I / O line) 27 Signal line 28 Write signal output means 29 Write circuit 31 NAND circuit 37 Column selection signal line 49 Resistor 140 Switching element 190 Resistor 280 Inverter 290 NOR circuit

Claims (6)

[Claims] 1. A row decoder for receiving a row address signal and outputting a row selection signal in response to the row address signal, a word line connected to the row decoder for receiving the row selection signal, and a column address signal. A column decoder that outputs a column selection signal according to the column address signal, a switching element that is connected to the column decoder, receives a column selection signal, and opens / closes in accordance with the column selection signal, and receives external input data. And a write circuit that outputs a data signal, and is connected to the write circuit via the switching element,
What is claimed is: 1. A semiconductor memory device comprising: a bit line that receives the data signal from the write circuit; and a memory cell connected to the word line and the bit line. Writable / unwritable information storage element for storing prohibition information, information writable / unwritable information storage element for the word line selected by the row decoder and connected to the writable / unwritable information storage element and the write circuit A write enable / disable determining unit that outputs a write enable / disable signal to the write circuit according to the above, and the write enable / disable output from the write enable / disable determining unit when the write enable / disable information storage element stores the write disable information. A semiconductor memory device, wherein the write circuit does not output the data signal when the write circuit receives the signal. 2. The write enable / disable information storage element is an element capable of assuming two states of a conductive state and a non-conductive state, and the write enable / disable determining means is a device for the word line selected by the row decoder. 2. The semiconductor memory device according to claim 1, wherein the write enable / disable signal is output to the write circuit according to the two states of the write enable / disable information storage element. 3. The write enable / disable determining means is connected between a signal line, the write enable / disable information storage element and the signal line, and is selected when the word line is selected by the row decoder. Potential changing means for changing the potential of the signal line in accordance with the two states of the conductive state and the non-conductive state stored in the write enable / disable information storage element for the word line; 3. The semiconductor memory device according to claim 2, further comprising a write enable / disable signal output unit that outputs the write enable / disable signal according to the changed potential of the signal line. 4. The semiconductor memory device according to claim 1, wherein the write enable / disable information storage element stores the write enable information or the write disable information for each of the word lines. 5. The writability information storage element stores the writable information or the writable prohibition information for each of a plurality of word line groups consisting of at least two word lines among the word lines. The semiconductor storage device according to 1. 6. A row decoder which receives a row address signal and outputs a row selection signal in response to the row address signal, a word line which is connected to the row decoder and receives the row selection signal, and a column address signal. A column decoder that outputs a column selection signal according to the column address signal, a switching element that is connected to the column decoder, receives a column selection signal, and opens / closes in accordance with the column selection signal, and receives external input data. And a write circuit that outputs a data signal, and is connected to the write circuit via the switching element,
A semiconductor memory device comprising: a bit line receiving the data signal from the write circuit; and a memory cell connected to the word line and the bit line, wherein the column decoder can write to the bit line. The output level of the column select signal is changed in accordance with the write enable / disable information storage element for storing information or write inhibit information and the information stored in the write enable / disable information storage element for the bit line selected by the column decoder. A writable / unwritable determination means, and a semiconductor memory device.