JPH05199214A - Frame synchronization method and frame synchronization circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] A frame synchronization circuit for CMI-CRV signals is to reduce the limitation of the device used and realize an economical circuit even if the signal speed is fast. [Structure] A data signal extracted by a CMI decoder from an input signal and a CRV display signal are n-parallel-developed in phase with each other in parallel. An n-parallel output 5a to 5d of an AND output of an n-parallel data signal 1a and an n-parallel CRV display signal 2a. Are encoded by the encoder 6, and the n parallel data signal 1a and the n-1 delayed data signal 4 are encoded.
Encoder outputs 6a and 6b using a as the input of the selector 3
To output the n-parallel data signal 3a synchronized with the frame.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMI (Code Mark Inverter) in an interface section which forms a transmission path.
code code CRV (Code Rule Video)
relation) signal (hereinafter referred to as a CMI-CRV signal).

[0002]

2. Description of the Related Art In a conventional frame synchronization method and frame synchronization circuit for frame synchronization of data, a method and a circuit for frame synchronization by parallel operation with respect to input data are disclosed in, for example, Japanese Patent Laid-Open No. 10206/1975. Sho 6
CMI-CR as described in JP-A-3-294151.
CMI is realized only for signals other than V signals.
-For the CRV signal, for example, Japanese Patent Laid-Open No. 1-109934
As described in Japanese Patent Laid-Open Publication No. 268330 and Japanese Patent Laid-Open Publication No. 268330, a method and circuit for serially synchronizing input data for frame synchronization have been used.

[0003]

SUMMARY OF THE INVENTION The above-mentioned prior art is CMI.
Since it is necessary to synchronize the frame of the CRV signal with the speed of the input signal as it is, there is a problem that the device is limited when the signal speed becomes faster, because it is necessary to use a device that can withstand the speed. An object of the present invention is to convert the speed of an input CMI-CRV signal by serial-parallel conversion and then to perform frame synchronization in parallel operation, thereby reducing restrictions on devices used and realizing an economically advantageous circuit configuration. Therefore, it is to provide a frame synchronization method and a frame synchronization circuit.

[0004]

In order to achieve the above object, a frame synchronization method and a frame synchronization circuit of the present invention include a CMI-CRV signal frame synchronization method and a frame synchronization circuit, the input signal of which is a CMI decoder. A CRV display signal in which only the data signal output from the device and the bit to which CRV is applied are set up, and the data signal and the CRV display signal are serial-parallel converted in the same phase in the preceding stage input to the frame synchronization circuit. In addition, in order to prevent erroneous recognition of the CRV and the CRV inserted to indicate the frame head due to a transmission failure, the extracted data signal (a fixed pattern is inserted at the CRV point at the head of the data signal frame) CR extracted from transmission line
The detection accuracy is improved by taking the logical product of the V display signal, and the CRV display signal (frame signal candidate) is applied to the encoder to detect the phase, and the detected phase is compared with the output phase from the phase holding circuit. Thus, the frame synchronization is monitored and the synchronization frame pattern is detected during hunting.

[0005]

In the frame synchronization method and frame synchronization circuit described above, the CRV display signal in which only the bits to which the CRV is applied is set as the data signal as well as the data signal output from the CMI decoder in order to establish the frame synchronization by the parallel operation. Serial-parallel conversion is performed in the same phase, and the data signal (the frame head of the data signal is not added to the frame head of the data signal is input to the encoder to ensure that this CRV correctly indicates the frame head, not due to the transmission path failure. (Fixed pattern is inserted) and the CRV display signal is ANDed. Further, the finding of the frame head of the input parallel signal is realized by using an encoder, and the encoder detects the frame head of a (1 <a <a <in the n (n> 2 integer) parallel input CRV display signal. (integer of n) outputs a coded signal (hereinafter referred to as a detection phase) that uniquely indicates the position when only one is detected in the nth signal, and based on the detection phase of this encoder N parallel input signals and n branched from the n parallel input signals using the selector
The n parallel signals with frame synchronization are selectively output from a total of 2n-1 data signals of the delay n-1 parallel input signals to the -1 parallel input signal through the delay circuit. The frame synchronization protection circuit consists of a phase holding circuit, a comparator, and a synchronization protection circuit.The encoder output is input to the phase holding circuit and comparator, and the phase holding circuit holds it according to the instructions of the synchronization protection circuit. Either the phase or the input phase is output to the comparator, the comparator compares both inputs from the encoder and the phase holding circuit, and the comparison result is output to the sync protection circuit. According to the result, the frame counter and the phase holding circuit are controlled to implement synchronization protection. In this way, the frame synchronization method and the frame synchronization circuit realize the frame synchronization circuit having the synchronization recovery characteristic equivalent to that of the 1-bit immediate shift system, and the range of devices used is widened and the cost of the CMI-CRV signal can be reduced. A frame synchronization method is realized.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a block diagram of a frame synchronization circuit for achieving frame synchronization after serial-parallel conversion showing an embodiment of a frame synchronization method and a frame synchronization circuit of a CMI-CRV signal according to the present invention. In FIG. 1, 1 is a 4 parallel data signal input terminal, 2 is a 4 parallel CRV display signal input terminal, 3 is a selector, 4 is a delay circuit, 5 is an AND circuit, 6
Is an encoder, 7 is a phase holding circuit, 8 is a comparison circuit, 9 is a frame counter, 10 and 11 are AND circuits, and 12 is a synchronization protection circuit. Four parallel data signals 1a are input to the selector 3 from the input terminal 1 of FIG. 1, and three parallel data signals of the four parallel data signals 1a are input to the selector 3 via the delay circuit 4. On the other hand, 4 parallel data signals 1a input from the input terminal 1
The parallel CRV display signal 2a is logically ANDed by the logical AND circuit 5 to output logical ANDs 5a, 5b, 5 to the encoder 6.
c and 5d are input. The encoder 6 encodes the input signal according to the truth table (FIG. 3) and outputs the phase detection flag 6a and the detected phase 6b to the phase holding circuit 7 and the comparison circuit 8. The phase holding circuit 7 has a holding phase 7a or a detection phase 6b.
Is output to the selector 3 and the comparison circuit 8, and the output of the comparison circuit 8 is logically ANDed by the output of the frame counter 9, the AND circuit 10 and the AND circuit 11 via the inverter, and is input to the synchronization protection circuit 11. .. The synchronization protection circuit 12 sends an operation instruction signal 12a to the phase holding circuit 7 and the frame counter 9 according to the result of the above input. The selector 3 uses the detected phase 6b input from the phase holding circuit 7 to input 4 parallel data signals 1a of the selector and 3 parallel delayed data signals 4a passing through the delay circuits 4 of 3 parallels to generate 4 parallel data signals in frame synchronization. This is a configuration for selectively outputting the combination of 3a.

FIG. 2 is a block diagram of a part of an interface unit including the frame synchronization circuit of FIG. 1 showing an embodiment of the frame synchronization method and the frame synchronization circuit of the CMI-CRV signal according to the present invention. In FIG. 2, the same reference numerals as those in FIG. 1 indicate corresponding parts, and 13 is a transmission line input,
14 is an O / E converter, 15 is a CMI decoder, 16,
Reference numeral 17 is a separation circuit (serial / parallel conversion circuit), and 18 is a frame synchronization circuit. The transmission line input (OPT IN) in FIG.
It is input to the CMI decoder 15 via the / E converter 14, and the CMI decoder 15 receives the data signal 15a from the input signal.
And the CRV display signal 15b are extracted. Data signal 15a
Are converted into 4 parallel data signals 1a via the separation circuit 17 and input to the selector 3 and the frame synchronization circuit 18, and 3 parallel data signals of the 4 parallel data signals 1a are input to the selector 3 via the delay circuit 4. To be done. The frame synchronization circuit 18 outputs a control signal 18a (detection phase 6b or holding phase 7b in FIG. 1) of the selector 3 and a frame signal 18b (phase detection flag 6a and detection phase 6b in FIG. 1),
The data signal 3a from the selector 3 is frame-synchronized.
Is output.

FIG. 3 is an explanatory diagram showing a truth table of the encoder 6 of FIG. In FIG. 3, frame pulse inputs (frame signals on the transmission path side) 5a, 5b, 5c, 5d of logical product outputs input from the logical product circuit 5 of FIG.
7 shows a truth table of the phase detection flag (detection → “1”) 6a and the detected phase (lower and upper bits) 6d of the encoded output of the encoder 6 corresponding to the H and L levels. The encode output of FIG. 3 has the phase detection flag 6a "when only one of the four parallel frame pulse inputs 5a to 5d is at the H level.
The phase detection flag 6a is set to "1" (valid) and the phase detection flag 6a is set to "0" (invalid) when there is no line or when two or more lines are at the H level.
Further, in order to uniquely indicate the number of the frame pulse input when only one is at the H level, the lower and upper two bits are given to the detection phase 6b.

FIG. 4 is an operation flowchart of FIG. 1 (FIG. 2). Next, the operation of the frame synchronization circuit of FIG. 1 (FIG. 2) will be described with reference to the operation flow of FIG. First, when the frame synchronization circuit is in the hunting state of FIG. 4, the synchronization protection circuit 12 issues an operation stop instruction to the frame counter 9 as an operation instruction signal 12a, and issues a phase acquisition instruction to the phase holding circuit 7. .. Further, the encoder 6 is provided with the transmission path side frame signals 5a, 5 of the output of the AND circuit 5.
b, 5c and 5d are input. Here, the candidate of the head of the transmission path side frame is obtained by the CRV display signal,
Since a fixed pattern is inserted at the beginning of the frame of the transmission path side data in order to distinguish from the CRV due to the transmission path failure, the data signal 15a output from the CMI decoder 15 in FIG.
1 is serial-parallel converted by the separation circuit (serial-parallel conversion circuit) 16 and the CRV display signal 15b output from the CMI decoder 15 is serial-parallel converted by the separation circuit 7 in FIG.
The outputs obtained by ANDing the parallel CRV signals 2a by the AND circuit 5 are used as transmission line side frame signal candidates.
The transmission path side frame signals 5a, 5b, 5c and 5d are encoded by the encoder 6 according to the truth table of FIG. 3, the phase is detected, and the phase detection flag 6a and the detected phase 6b of the phase detection data are output. The encoding result of FIG. 3 is that the phase detection flag 6a is enabled when only one frame of the transmission path side frame signals 5a to 5d, which is a candidate of four frame signals of all the input patterns, is detected, The phase detection flag 6a is used when a frame is detected in two or more frame signals and when there is no valid bit.
Is disabled, and when further phase detection is performed, the detection phase 6b is determined so as to uniquely determine the four frame pulses in order to uniquely indicate where of the four inputs is detected.
2 bits are allocated and output.

The detected phase 6b of the encoder 6 is input to the phase holding circuit 7, and the phase holding circuit 7 fetches and outputs the detected phase 6b by the operation instruction signal 12a of the synchronization protection circuit 12 or outputs the held data 7a in the previous state. Although either output is performed, the phase holding circuit 7 outputs the detection phase 6b because the phase acquisition instruction is issued during hunting.
Capture and output. On the other hand, the detection phase 6b of the output of the encoder 6 is also input to the comparison circuit 8 and the comparison circuit 8
Then, the output of the phase holding circuit 7 is compared with the detected phase 6b of the output of the encoder 6 and the comparison result is output. However, if the comparison result is the same, it is an invalid output when it is different from the valid output. Is output to the AND circuit 10 and the AND circuit 11 via the inverter. At the same time, the output of the frame counter 9 is also connected to the AND circuits 10 and 11, and the frame counter 9 performs either the fixed output of "ALL1" or the frame counter operation according to the operation instruction signal 12a of the synchronization protection circuit 12. The output is "ALL1" during hunting. The outputs of the AND circuits 10 and 11 are output to the sync protection circuit 12, and the sync protection circuit 12 determines whether or not pattern detection is performed by the input from the AND circuit 10 during hunting. When it is invalid, the synchronization protection circuit 12 holds the hunting operation state as if it cannot detect the pattern, but when the output of the AND circuit 10 is valid, the synchronization protection circuit 12 considers that the pattern detection is successful, Load the rear protection counter and enter the next rear protection operating state.

When the backward protection state is entered, the sync protection circuit 12
Issues an operation instruction as an operation instruction signal 12a to the frame counter 9, and issues an instruction to stop the phase acquisition and to hold the phase currently acquired to the phase holding circuit 7. As a result, the frame counter 9 causes the synchronization protection circuit 12 to
The phase holding circuit 7 stops capturing the input from the encoder 6 according to the instruction of the synchronization protection circuit 12 and detects the pattern in the synchronization protection circuit 12 according to the instruction of the synchronization protection circuit 12. The phase determined to have been held is held and the held phase 7a is output. When the valid signal of the phase detection flag 6a of the encoder 6 is input to the comparison circuit 8 after the backward protection operation state, the comparison circuit 8 compares this input with the input from the phase holding circuit 7, and if the same, the comparison signal is valid. If the signals are different, invalid signals are output to the AND circuits 10 and 11, respectively. The output from the comparison circuit 8 and the output from the frame counter 9 are input to one AND circuit 10, and a valid output is output if both inputs are synchronized, and an invalid output is output if they are not synchronized. Will be issued. The other AND circuit 1
The signal from the inverter and the output from the frame counter 9 are input to the output from the comparison circuit 8 at 1, and an invalid output is output if both inputs are synchronized, and a valid output is output if they are out of synchronization. become. The synchronization protection circuit 12 monitors the input from the AND circuit 10 and the input from the AND circuit 11, and detects the valid signal from the AND circuit 10 and the AND circuit 1.
The backward protection counter is made to step when the combination of the invalid signal from 1 comes, and when the valid signal comes from the AND circuit 11 before the step of the backward protection counter reaches the number of backward protection stages, the synchronous protection circuit 12 Stops the backward protection operation and returns to the hunting operation state, but if there is no valid signal from the AND circuit 11 until the step of the backward protection counter reaches the backward protection stage number, the synchronous protection circuit 12 finishes the backward protection operation. When it is confirmed that the backward protection operation is completed, the synchronous protection circuit 12 clears the forward protection counter and enters the next forward protection operation state.

In the forward protection operation state, the synchronization protection circuit 12 outputs the operation instruction signal 12a as the frame counter 9
To the phase holding circuit 7 and the phase holding circuit 7 to hold the phase taken in during the backward protection operation. The detection phase 6b output from the encoder 6 is input to the comparison circuit 8, and the comparison circuit 8 compares the detection phase 6b from the encoder 6 with the input signal from the phase holding circuit 7, and the comparison result shows the logical product circuit 10 And an AND circuit 11 via an inverter. On the other hand, the frame counter 9 outputs the operation instruction signal 12a from the synchronization protection circuit 12 to the AND circuit 10 and the AND circuit 11. The synchronization protection circuit 12 receives inputs from the logic circuits 10 and 11, determines that synchronization is maintained as long as the input from the AND circuit 10 continues, clears the front protection counter, and continues the front protection operation. When the input from the logical product circuit 10 is interrupted or the input from the logical product circuit 11 is received, the synchronous protection circuit 12 regards it as a phase mismatch and advances the forward protection counter to judge the number of forward protection stages to end and end. If not, it returns to the pattern detection / phase monitoring state, and if the number of forward protection stages is completed, the synchronization protection circuit 1
No. 2 shifts to the hunting operation state assuming that the state is out of frame synchronization. In the above three states of the hunting operation state, the rear protection operation state, and the front protection operation state, the phase holding circuit 7 outputs the holding phase 7a or the detection phase 6b to the selector 3, and the selector 3 inputs from the separation circuit 16. The 4 parallel data signals 1a and the delayed 3 parallel data signals 4a obtained by passing the adjacent 3 parallel data signals of the 4 parallel data signals 1a through the delay circuit 4 are detected from the first one in the frame according to the information of the detection phase 6b. Up to four data signals are selected and four parallel frame-synchronized data signals 3a are output.

According to this embodiment, in the frame synchronization method and the frame synchronization circuit of the CMI-CRV signal,
The frame synchronization circuit, which has the same synchronization recovery characteristics as the bit immediate shift system, operates in parallel to achieve frame synchronization, which can be realized without depending on the device even if the signal speed becomes faster, and an economically advantageous circuit configuration. it can.

[0014]

According to the present invention, the CMI-CRV signal frame synchronization method and the frame synchronization circuit perform serial-parallel conversion and then form a hunting circuit and a pattern detection / phase monitoring circuit in parallel operation to thereby improve the signal speed. It is possible to deal with the circuit configuration even if the speed becomes faster, and it is possible to alleviate the limitation of the device used and to construct an economically advantageous circuit.

[Brief description of drawings]

FIG. 1 is a block diagram of a frame synchronization circuit showing an embodiment of a frame synchronization method and a frame synchronization circuit for a CMI-CRV signal according to the present invention.

FIG. 2 is a block diagram of a part of an interface unit including a frame synchronization circuit showing an embodiment of the present invention.

FIG. 3 is an explanatory diagram of a truth table of the encoder of FIG. 1.

FIG. 4 is an operation flowchart of FIG. 1 (FIG. 2).

[Explanation of symbols]

1 ... 4 parallel data signal input terminal, 2 ... 4 parallel CRV display signal input terminal, 3 selector, 4 delay circuit, 5 AND circuit, 6 encoder, 7 phase holding circuit, 8 comparison circuit, 9 ... frame counter, 10, 11 ... AND circuit, 12 ... synchronization protection circuit, 15 ... CMI decoder, 16,
17 ... Separation circuit (serial / parallel conversion circuit), 18 ... Frame synchronization circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Hiroyuki Fujita, Inventor Hiroyuki Fujita, 216 Totsuka-cho, Totsuka-ku, Yokohama, Kanagawa Inside the Totsuka Plant, Hitachi, Ltd. No. Japan Telegraph and Telephone Corporation

Claims (6)

[Claims] 1. A frame synchronization method for frame-synchronizing a CMI-CRV signal, wherein a data signal and a CRV display signal are extracted from an input signal, and the data signal and the CRV display signal are in phase and n (n> 2 is an integer). ) Parallel development is performed, and the n-parallel data signal and the n-parallel CRV display signal are logically ANDed,
The n parallel signals of the logical product outputs are encoded, n-1 data signals of the n parallel data signals are delayed, and the n data signals and the n-1 delayed data signals are input to the above. A frame synchronization method characterized by selectively outputting n data signals by encoding output. 2. A frame synchronization method for frame-synchronizing a CMI-CRV signal, wherein a data signal and a CRV display signal are extracted from an input signal, and the data signal and the CRV display signal are in-phase and have an integer of n (n> 2). ) Parallel development is performed, and the n-parallel data signal and the n-parallel CRV display signal are logically ANDed,
The n parallel signals of the logical product outputs are encoded, n-1 data signals of the n parallel data signals are delayed, and the n data signals and the n-1 delayed data signals are input to the above. A frame synchronization method for selectively outputting n data signals by encoding output, wherein only one of n parallel input signals is CRV at the time of encoding.
A frame synchronization method characterized in that it is valid when a display signal is detected, and invalid when there is no display signal or when two or more are detected. 3. A frame synchronization method for a CMI-CRV signal, wherein a data signal and a CRV display signal are extracted from an input signal and the data signal and the CRV display signal are in phase with each other.
(Integer of n> 2) is expanded in parallel and the n parallel data signal and n
The logical product of the parallel CRV display signals is calculated, and n of the logical product output is obtained.
A parallel signal is encoded, and n-1 data signals of the n parallel data signals are delayed, and the n data signals and the n-1 delayed data signals are input to the encoder output to output n data signals. A frame synchronization method for selectively outputting a data signal, and when only one CRV display signal among n parallel input signals is input during the above-mentioned encoding, the input signal is a (1 <a <n (Integer) th signal is uniquely shown to be the frame synchronization method. 4. A CMI decoder for extracting a data signal and a CRV display signal from an input signal in a frame synchronization circuit for frame-synchronizing a CMI-CRV signal, and n (n) of the data signal and the CRV display signal in phase. > 2) an serial-to-parallel conversion circuit that expands in parallel, and the n-parallel data signal and n
A logical product circuit for taking a logical product of the parallel CRV display signals, an encoding circuit for encoding an n parallel signal of the logical product output, and a delay circuit for delaying n-1 data signals of the n parallel data signals, A frame synchronization circuit comprising: a selector circuit which receives the n data signals and the n-1 delayed data signals as inputs, and selectively outputs n data signals by the encode output. 5. A CMI decoder for extracting a data signal and a CRV display signal from an input signal in a frame synchronization circuit for frame-synchronizing a CMI-CRV signal, and n (n) of the data signal and the CRV display signal in phase with each other. > 2) an serial-to-parallel conversion circuit that expands in parallel, and the n-parallel data signal and n
A logical product circuit for taking a logical product of the parallel CRV display signals, an encoding circuit for encoding an n parallel signal of the logical product output, and a delay circuit for delaying n-1 data signals of the n parallel data signals, And a selector circuit which receives the n data signals and the n-1 delayed data signals as inputs and selectively outputs n data signals by the encode output, and the encode circuit is one of n parallel input signals. A frame synchronization circuit characterized by a logic that is valid when only one CRV display signal is detected and invalid when there is no CRV display signal or when two or more are detected. 6. In a frame synchronization circuit for frame-synchronizing a CMI-CRV signal, a CMI decoder for extracting a data signal and a CRV display signal from an input signal, and n (n) in-phase for the data signal and the CRV display signal. > 2) an serial-to-parallel conversion circuit that expands in parallel, and the n-parallel data signal and n
A logical product circuit for taking a logical product of the parallel CRV display signals, an encoding circuit for encoding an n parallel signal of the logical product output, and a delay circuit for delaying n-1 data signals of the n parallel data signals, And a selector circuit which receives the n data signals and the n-1 delayed data signals as inputs and selectively outputs n data signals by the encode output, and the encode circuit is one of n parallel input signals. A frame synchronization circuit having a logic uniquely indicating that the input signal is the a-th (1 <a <n integer) signal when only one CRV display signal is input.