JPH05199217A - Frame synchronization circuit for digital transmission - Google Patents

Abstract

(57) [Summary] [Purpose] To significantly reduce the time for hunting operation and to ensure high reliability in data communication. A pattern detection signal Sh obtained by detecting the same pattern as a frame synchronization signal from a code string is written, and an internal synchronization signal that matches the pattern detection signal from the internal synchronization signal generator 3 by the read pattern detection signal. Storage unit 6 using FIFO memory 6a for outputting Si
And write the pattern detection signal Sh (comparison signal Shm) in the first period Tf corresponding to one frame period after outputting L (for example, L = N−1) mismatch pulses Pk to the storage unit 6 and continuing. Simultaneously with the start of the second period Ts corresponding to one frame period, the comparison signal S stored in the storage unit 6
A control unit 7 for reading hm from the beginning is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization circuit for digital transmission, which detects a frame synchronization signal from a code string received from a transmission line to establish frame synchronization.

[0002]

2. Description of the Related Art In general, a receiver in digital transmission suppresses out-of-sync due to a transmission path error, and when out-of-sync occurs, it is promptly detected and restored to a normal frame synchronization state. Built-in frame synchronization circuit.

FIG. 5 shows a conventional frame synchronization circuit. Note that FIG. 6 shows a timing chart of signals of respective parts in FIG.

A frame synchronization circuit 50 shown in FIG. 5 detects a pattern identical to a frame synchronization signal and outputs a pattern detection signal Sb, a pattern detection section 51, an internal synchronization signal generation section 52 which outputs an internal synchronization signal Sc, A synchronization signal detection unit 53 that outputs a coincidence pulse Pg when the position of the pattern detection signal Sb coincides with the position of the internal synchronization signal Sc, and outputs a disagreement pulse Pf when there is a disagreement, and counts a predetermined number of consecutive disagreement pulses Pf. Out of sync signal Sd
And a sync protection circuit 54 that stops the output of the out-of-sync signal Sd after counting a predetermined number of consecutive coincidence pulses Pg, an internal sync signal in accordance with the states of the coincidence pulse Pg, the non-coincidence pulse Pf and the out-of-sync signal Sd. It comprises a NAND circuit 55 for controlling the generator 52 and an RS flip-flop 56.

Therefore, the frame synchronization circuit 50 operates as follows. First, the code string (received data) D shown in FIG. 6A is input to the input side of the pattern detection unit 51. The code string D is a continuous time-series signal of a unit frame including a data portion Da and a frame synchronization pattern portion (frame synchronization signal) Db. The pattern detection unit 51 uses the code string D
From the same pattern bit “110
0 "is detected, and the pattern detection signal Sb shown in FIG.
Is applied to the input side of the synchronization signal detection unit 53. In addition, the internal synchronization signal generator 52 has an internal synchronization signal S shown in FIG.
c is provided to the synchronization signal detection unit 53. Sync signal detector 5
3 detects whether or not the position of the pattern detection signal Sb coincides with the position of the internal synchronization signal Sc, and outputs a coincidence pulse Pg shown in FIG. The non-matching pulse P shown in FIG.
Output f.

On the other hand, the synchronization protection circuit 54 performs a front protection operation and a rear protection operation. The forward protection operation is for executing the hunting operation when the synchronization loss occurs and the operation is continued to some extent, and specifically, the continuous disagreement pulse Pf.
Is counted, and if, for example, six mismatch pulses Pf are counted, the out-of-synchronization signal Sd is output. In the case of FIG. 6, the hunting operation starts from the mismatch pulse Pfs, and the out-of-synchronization signal Sd is output. The backward protection operation is for confirming that the synchronous recovery is surely performed after the hunting operation is completed. Specifically, the continuous match pulses Pg are counted, and for example, two match pulses Pg are counted. If so, the output of the out-of-sync signal Sd is stopped.

On the other hand, the hunting operation is performed as follows. First, the internal synchronization signal generator 52 has a built-in counter, and as shown in FIG. 6E, the counter is reset at the same time as the output of the internal synchronization signal Sc and set at the same time as the output of the next pattern detection signal Sb. To be done. Then, the counter counts only the unit frame period To and then outputs the next internal synchronization signal Sc. Also, it is reset at the same time as this output. If the above hunting operation is repeatedly executed, the pattern detection signal Sb that coincides with the position of the internal synchronization signal Sc, that is, the true pattern synchronization signal can be detected, and the synchronization signal detector 53 outputs the coincidence pulse Pg. To do. Therefore, it is possible to return to the frame synchronization state, and at this point the hunting operation ends. Then, the processing based on the backward protection operation is performed.

[0008]

However, since the above-described conventional frame synchronization circuit 50 serially determines whether or not the pattern detection signal detected from the unit frame is a true frame synchronization signal, it is particularly necessary to When there are many pattern detection signals in a frame, the number of frames required for the hunting operation reaches more than one hundred tens of frames, and it takes a considerable time to recover the synchronization, resulting in erroneous data communication. There was a serious loss.

The present invention solves the problems existing in the prior art as described above, and particularly, the frame synchronization for digital transmission which can greatly shorten the time of hunting operation and ensure high reliability in data communication. The purpose is to provide a circuit.

[0010]

According to the present invention, as shown in FIG. 1, in constructing a frame synchronization circuit 1 for digital transmission, which detects a frame synchronization signal from a code string received from a transmission line to establish frame synchronization, The pattern detection signal S by detecting the same pattern as the frame synchronization signal from the code string
The pattern detection unit 2 that outputs h, the internal synchronization signal generation unit 3 that outputs the internal synchronization signal Si, and the coincidence pulse Pj when the position of the pattern detection signal Sh coincides with the position of the internal synchronization signal Si. And the sync signal detection unit 4 that outputs a mismatch pulse Pk when there is a mismatch, and the sync loss signal S when N consecutive mismatch pulses Pk are counted.
The sync protection circuit 5 that outputs m and stops the output of the out-of-sync signal Sm when counting M consecutive continuous pulses Pj and the pattern detection signal Sh are written, and the internal synchronization is performed by the read pattern detection signal. The storage unit 6 that uses the FIFO memory 6a that outputs the internal synchronization signal Si that matches the pattern detection signal from the signal generation unit 3 and 1 after outputting L (for example, L = N-1) mismatch pulses Pk. The pattern detection signal Sh (comparison signal Shm) in the first period Tf corresponding to the frame period is written in the storage unit 6 and, at the same time as the start of the second period Ts corresponding to the subsequent one frame period, the comparison stored in the storage unit 6 is started. It is characterized by including a control unit 7 for reading the signal Shm from the beginning. In this case, the position of the pattern detection signal Sh in the comparison signal Shm is converted into relative addresses A1, A2, A3, A4, A5 ... And stored in the storage unit 6. The storage unit 6 also includes a memory empty detection unit 6c that detects that the FIFO memory 6a has become empty (address value 0) at the time of reading.

[0011]

According to the frame synchronizing circuit 1 of the present invention, the code string (received data) D is input to the input side of the pattern detecting section 2 from the transmission line. The pattern detection unit 2 detects the same pattern as the frame synchronization signal from the code string D, and applies the pattern detection signal Sh obtained from this to the input side of the synchronization signal detection unit 4 and the control unit 7.

The internal sync signal generator 3 also outputs an internal sync signal Si to the input side of the sync signal detector 4. The sync signal detection unit 4 detects whether or not the position of the pattern detection signal Sh matches the position of the internal sync signal Si, outputs a match pulse Pj when they match, and outputs a match pulse Pj when they do not match. The pulse Pk is output.

On the other hand, the synchronization protection circuit 5 performs a front protection operation and a rear protection operation. Forward protection operation is out of sync,
This is for performing a hunting operation when it continues to some extent, and counts consecutive unmatched pulses Pk, and outputs an out-of-synchronization signal Sm when N unmatched pulses Pk are counted. The backward protection operation is for confirming that the synchronous recovery is surely performed after the end of the hunting operation. When the continuous coincidence pulses Pj are counted and M coincidence pulses Pj are counted, the out-of-synchronization signal Sm is obtained. Stop the output of.

On the other hand, the hunting operation is performed as follows. First, the storage unit 6 stores the pattern detection signal Sh (comparison signal Shm) in the first period Tf corresponding to one frame period after outputting L mismatch pulses Pk. At this time, the position of the pattern detection signal Sh is set to the relative address A.
It is converted into 1, A2, A3 ... And stored in the storage unit 6. Then, simultaneously with the start of the second period Ts corresponding to the subsequent one frame period, the comparison signal Shm stored in the storage unit 6 is read from the beginning. The comparison signal Shm read from the storage unit 6 is input to the internal synchronization signal generation unit 3, and the internal synchronization signal generation unit 3 provides the synchronization signal detection unit 3 with the internal synchronization signal Si that matches the comparison signal Shm. Therefore, the position of the pattern detection signal Sh provided from the pattern detection unit 2 and the comparison signal Shm provided from the internal synchronization signal generation unit 3 to the internal synchronization signal generation unit 3 at the same time when the second period Ts starts. The positions are sequentially compared, and the position of the pattern detection signal Sh and the comparison signal S are compared.
If the positions of hm match, the pattern detection signal Sh at that time is detected as a true pattern synchronization signal. That is,
The coincidence pulse Pj is output from the synchronization signal detector 3 and the frame synchronization state can be restored. At this point, the hunting operation ends, and the processing based on the backward protection operation is performed. Incidentally, when the true pattern synchronization signal is not detected, the same processing is repeated.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, preferred embodiments according to the present invention will be described in detail with reference to the drawings.

First, the structure of a frame synchronization circuit according to an embodiment of the present invention will be described with reference to FIG.

Reference numeral 2 is a pattern detecting section whose input side is connected to a transmission line, and is provided with a pattern detector 2a. The output side of the pattern detector 2a is connected to the input side of the synchronization signal detecting section 4 and is connected to the memory control section 7a in the control section 7 via the shift register 2b.

Reference numeral 3 denotes an internal synchronizing signal generator which utilizes an up / down counter. The output side of the internal sync signal generator 3 is connected to the input side of the sync signal detector 4, and the internal sync signal generator 3 is further connected to the up / down counter controller 7 b of the controller 7.

The output side of the sync signal detector 4 is connected to the sync protection circuit 5 and the up / down counter controller 7b. The output side of the synchronization protection circuit 5 is connected to the up / down counter controller 7b and the memory controller 7a.

On the other hand, reference numeral 6 denotes a storage unit, which includes a FIFO memory 6a, an up-counter 6b connected to the FIFO memory 6a, and a memory empty detection unit 6c for detecting that the FIFO memory 6a is empty (address value 0). Equipped with. The output side (output port) of the FIFO memory 6a is connected to the input side (input port) of the internal synchronization signal generator 3, and the FIFO memory 6a and the up counter 6b are connected to the memory controller 7a. Also, the FIFO
The output side of the memory 6a is connected to the memory empty detection unit 6c, and the output side of the memory empty detection unit 6c is connected to the memory control unit 7c.
a and the counter controller 7b.

Next, the operation of the frame synchronization circuit 1 shown in FIG. 2 will be described with reference to FIGS. 3 and 4.

First, the code string (received data) D shown in FIG. 3A is input to the input side of the pattern detector 2a from the transmission line. Note that Da is a data part, and Db is a frame synchronization pattern part (frame synchronization signal). The pattern detector 2a detects the same pattern bit (usually "1100") as the frame synchronization signal from the code string D, and shifts the pattern detection signal Sh shown in FIG. It is given to the memory control unit 7a in the control unit 7 via the register 2b.

Further, the internal synchronizing signal generator 3 is shown in FIG.
The internal synchronization signal Si shown in is output and applied to the input side of the synchronization signal detector 4. The synchronization signal detector 4 uses the internal synchronization signal S
It is detected whether or not the position of the pattern detection signal Sh coincides with the position of i, and if coincident, the coincidence pulse Pj shown in FIG. The mismatch pulse Pk shown in G) is output.

Next, the front protection operation, the hunting operation, and the rear protection operation will be described. The forward protection operation is for executing the hunting operation when the synchronization is lost and continues for some time.
Is counted, and if N (usually 6) mismatch pulses Pk are counted, an out-of-synchronization signal Sm is output (step 3).
1, 32, 35, 36). In the case of FIG. 3, the mismatch pulse P
The hunting operation starts from ks, and the out-of-synchronization signal Sm shown in FIG. Further, the backward protection operation is for confirming that the synchronous recovery is surely performed after the end of the hunting operation, and counts consecutive coincidence pulses Pj,
When M (usually 2) coincidence pulses Pj are counted, the output of the out-of-synchronization signal Sm is stopped (steps 39 and 4).
0, 41, 31).

On the other hand, the hunting operation is performed as follows. First, L (L = N−1) mismatch pulses Pk,
That is, the pattern detection signal Sh (the comparison signal Sh) in the first period Tf corresponding to one frame period after outputting five
m) is stored in the FIFO memory 6a (step 33,
34). The comparison signal Shm is shown in FIG. On this occasion,
The position of the pattern detection signal Sh is relative address A1, A
2, converted into A3 ... and stored. That is, the up counter 6b in the storage unit 6 is activated and the comparison signal S
Each time the pattern detection signal Sh in hm is detected, the initial value of the up counter 6b is set to 1, and thereby the relative address A1 ... Is generated. Further, the pattern detection signal Sh detected at the same time is used as a write enable signal of the FIFO memory 6a, and the generated relative addresses A1 ... Are written in the FIFO memory 6a (FIG. 3 (D)).

Then, at the same time as the start of the second period Ts corresponding to the subsequent one frame period, the FIFO shown in FIG.
The comparison signal Shm stored in the memory 6a is read from the beginning (step 37). In this case, the mismatch pulse Pk output from the synchronization signal detector 4 is used as a read enable signal, and the relative address A1 is read from the FIFO memory 6a.
Is read out and set as the initial value of the up / down counter in the internal synchronization signal creating section 3, and the internal synchronization signal Si is generated when the count value of the down counter at this time becomes 1. Therefore, the internal synchronization signal generation unit 3 gives the internal synchronization signal Si that matches the comparison signal Shm to the synchronization signal detection unit 4 (see FIG. 3F). This allows
For the internal synchronization signal generator 3, the position of the pattern detection signal Sh provided by the pattern detector 2 and the position of the comparison signal Shm provided by the internal synchronization signal generator 3 are determined at the same time when the second period Ts starts. When the positions of the pattern detection signal Sh and the position of the comparison signal Shm coincide with each other in sequence, the pattern detection signal Sh at that time is detected as a true pattern synchronization signal (step 38). That is, the coincidence pulse Pj is output from the synchronization signal detector 3 and the frame synchronization state can be restored. At this point, the hunting operation ends, and subsequently, the processing based on the backward protection operation is performed (steps 39, 40, 41). If the true pattern synchronization signal is not detected, the FIFO memory 6a
Since the address value of 0 is output, the memory empty detection unit 6c
This is detected by, and the same processing is repeated by rewriting to the FIFO memory 6a (step 3).
8, 42, 43).

The embodiment has been described in detail above.
The present invention is not limited to such an embodiment,
The detailed circuit configuration, numerical values, etc. can be arbitrarily changed without departing from the scope of the present invention.

[0028]

As described above, the frame synchronizing circuit according to the present invention writes the pattern detection signal obtained from the code string, and the read pattern detection signal causes the internal synchronization signal generator to match the internal pattern detection signal. A storage unit that outputs a synchronization signal, and a pattern detection signal (comparison signal) in a first period corresponding to one frame period after outputting L non-matching pulses are written in the storage unit and that corresponds to the following one frame period. At the same time as the start of the two periods, a control unit for reading the contrast signal stored in the storage unit from the beginning is provided, so that the time of the hunting operation can be greatly shortened and high reliability in data communication can be ensured. Has a remarkable effect.

[Brief description of drawings]

FIG. 1 is a block circuit diagram of a frame synchronization circuit according to the present invention,

FIG. 2 is a block circuit diagram embodying a frame synchronization circuit according to the present invention;

FIG. 3 is a time chart of signals in each part of FIG.

FIG. 4 is a flowchart showing an algorithm of a front protection operation, a hunting operation, and a rear protection operation,

FIG. 5 is a block circuit diagram of a frame synchronization circuit according to a conventional technique,

FIG. 6 is a time chart of signals in each part of FIG.

[Explanation of symbols]

 1 frame synchronization circuit 2 pattern detection unit 3 internal synchronization signal generation unit 4 synchronization signal detection unit 5 synchronization protection circuit 6 storage unit 6a FIFO memory 6c empty memory detection unit 7 control unit A1 ... Relative address Sh pattern detection signal Si internal synchronization signal Pj Matching pulse Pk Mismatching pulse Sm Out-of-sync signal Shm Contrasting signal Tf First period Ts Second period

Claims (5)

[Claims] 1. A frame synchronization circuit for digital transmission, which detects a frame synchronization signal from a code string received from a transmission line to establish frame synchronization, detects the same pattern as the frame synchronization signal from the code string, and outputs a pattern detection signal. Outputs a pattern detection unit, an internal synchronization signal generation unit that outputs an internal synchronization signal, and outputs a match pulse when the position of the pattern detection signal matches the position of the internal synchronization signal, and when they do not match, does not match A sync signal detection unit that outputs a pulse and an out-of-sync signal when N consecutive disagreement pulses have been counted, and a succession coincidence pulse M
A sync protection circuit that stops the output of the out-of-sync signal when counting the number, and a pattern detection signal is written, and the internal sync signal that matches the pattern detection signal is output from the internal sync signal generator by the read pattern detection signal. And a pattern detection signal (comparison signal) in the first period corresponding to one frame period after outputting L number of mismatch pulses to the storage unit, and starting the second period corresponding to the following one frame period. At the same time, a frame synchronization circuit for digital transmission, comprising a control unit for reading the comparison signal stored in the storage unit from the beginning. 2. The frame synchronization circuit for digital transmission according to claim 1, wherein L = N-1 is set. 3. The frame synchronization circuit for digital transmission according to claim 1, wherein the position of the pattern detection signal in the comparison signal is converted into a relative address and stored in the storage unit. 4. The frame synchronization circuit for digital transmission according to claim 1, wherein the storage section uses a FIFO memory. 5. The frame synchronization circuit for digital transmission according to claim 1, wherein the storage section includes a memory empty detection section that detects that the FIFO memory has become empty at the time of reading.