JPH05199272A - Demodulator - Google Patents

Abstract

PURPOSE:To avoid a problem of reduction in synchronization width due to an effect of pseudo synchronization by detecting it that a carrier is in the pseudo synchronization state and stepping out the carrier forcibly, locking the synchronization again and repeating it till the normal synchronization state is reached. CONSTITUTION:Since an output h1 of an error correction word asynchronization detection circuit 17 is at a high level, an output h2 of a carrier asynchronization detection circuit 19 goes to a low level, an output h3 of an inversion circuit 14 goes to a high level, an output of an AND circuit 13 goes to a high level and an input h4 of an intermittent reset generating circuit 22 goes to a high level in the pseudo synchronization state, a high level and a low level are inputted to a flip-flop circuit 15 for each prescribed time. On the other hand, the h1, h2 go both to a low level, the h3 goes to a high level and an output of the intermittent reset generating circuit 22 is fixed to a low level in the normal synchronization state. Thus, since a low level is inputted to the flip-flop circuit 15 in the normal synchronization state, the normal operation is implemented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demodulator used in a 2 ^N- value quadrature amplitude modulation system or a 2 N-phase modulation system.

[0002]

2. Description of the Related Art A 16Q embodiment of a conventional demodulation device provided with a digitized carrier wave synchronizing circuit and an error correcting circuit.
An example of AM is shown in FIG. The modulated wave a inputted from the input end is branched into two and inputted to the multipliers 1 and 2. On the other hand, the output k1 of the carrier wave voltage controlled oscillator 20 becomes two carrier wave signals k1 and k2 having a π / 2 radian phase difference from each other by the π / 2 phase shifter 21, is input to the multipliers 1 and 2, and is synchronously detected. Baseband signal b
1 and b2 are obtained. The baseband signals b1 and b2 are band-limited by the low-pass filters 3 and 4 for roll-off band limitation, and then amplified to the optimum amplitude value by the baseband amplifiers 5 and 6 to be converted into the AD converter 7 and 8 is input. On the other hand, the clock reproducing circuit 9 reproduces the clocks g1 and g2 as timing signals from the baseband signals d1 and d2, and the AD converters 7 and 8 identify the baseband signals d1 and d2. AD converter 7
The output digital signals of 8 and 8 are the in-phase (Pch) side data signals e1 and e2, and the quadrature (Qch) side data signals f1 and f2, which are input to the error correction circuit 10 together with the recovered clock g3 and after error correction. Output signal l
1, l2, l3, and l4, and the output clock g5, which is output from the demodulator. Here, the digital output signal e1 is the first bit (MSB) of the in-phase component (Pch).
, And becomes a Pch output signal which is the identification result of the four-valued demodulated baseband signal d1 together with the second bit e2. Also,
The digital output signal e3 is an error signal representing the deviation from the true value signal point at the third bit of Pch. The digital output signal f1 has the first bit (MS) of the quadrature component (Qch).
B), which is the Qch output signal of the discrimination result of the four-valued demodulated baseband signal d2 together with the second bit f2. Further, f3 is an error signal representing the deviation from the true value signal in the third bit of Qch. On the other hand, the digital signals e1 and f
A phase control signal is created using 3, f1 and e3 to synchronize the carrier. That is, the exclusive OR circuits 11 and 12 take an exclusive OR of the first bit e1 of Pch and the error signal f3 of Qch and the first bit f1 of Qch and the error signal e3 of Pch, respectively, and subtract the result. The phase control signal i3 can be obtained by taking each difference in the device 16. Furthermore, the loop filter 18
Thus, the phase control signal i1 from which the noise component is removed becomes the phase control signal i1 and the carrier wave voltage controlled oscillator 20 is controlled to obtain the reproduced carrier wave k1.

As described above, in the conventional quadrature amplitude demodulator using the digitized carrier wave synchronizing circuit, in order to secure a certain synchronization pull-in range, false lock (for example, in the case of 2 ^N- value quadrature amplitude modulation). Is the carrier frequency f _CARR to 1 / n of the clock frequency f _CLK (n =
Pseudo sync points are generated at frequencies apart from 2 ^{N '} , N ^' : 1, 2, 3 ... N). ) Called pseudo-synchronization, it may not be possible to secure the required carrier synchronization range especially when the clock frequency is low. FIG. 3 illustrates the relationship of the reproduced carrier frequency when the input carrier frequency is changed in the case of pseudo synchronization. In FIG. 3, m1, n1, p1
And g1 are frequencies for pulling in pseudo synchronization, m2 and P2 are frequencies for pulling from pseudo synchronization to normal synchronization, and n2.
And g2 indicate frequencies outside the normal sync holding range and out of normal sync. When the input carrier frequency is raised from a sufficiently low position, it is first pulled into pseudo synchronization centered on f _CARR -f _clk / n at m1. Then, at m2, the pseudo synchronization is pulled into the normal synchronization. When the input carrier frequency is lowered from a sufficiently high place, first, at P1, f _CARR + f _clk /
Pull in pseudo-sync around n. Then, at P2, the pseudo synchronization is pulled into normal synchronization. That is, pull-in range of the case of FIG. 3 is a f _CARR + P2~f _CARR -m2, is narrower than the actual pull-in range for the pseudo sync.

[0004]

As described above, in the conventional apparatus, pseudo synchronization is required to secure the synchronization pull-in range, so that the carrier synchronization range required especially when the clock frequency is low cannot be secured. was there.

An object of the present invention is to solve the above drawbacks and to provide a demodulation device capable of ensuring a required sync pull-in range without being affected by pseudo sync.

[0006]

According to the present invention, in a demodulator having a carrier synchronizing circuit and an error correcting circuit, a carrier arriving at the carrier synchronizing circuit is in a synchronous state and the error correcting circuit corrects the error. Means for detecting that the carrier word is in the pseudo-synchronous state when it is in the asynchronous state, and a state in which the carrier synchronization circuit is in the stopped state and the oscillating state over the time period from the pseudo-synchronous detection to the normal synchronous state. And a means for alternately repeating the two states.

Here, the demodulator may be a 2N-phase demodulator. Further, the demodulator may be a 2 ^N- value quadrature amplitude demodulator.

[0008]

When the pseudo-synchronous state is set, the word of the error correction circuit is in the asynchronous state and the carrier synchronizing circuit is in the synchronous state. When the pseudo-synchronous state is set, the carrier synchronization is once removed and brought into the normal synchronization. This expands the carrier synchronization pull-in range.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an embodiment in which the present invention is applied to a 16-value quadrature amplitude demodulator. In FIG. 1, the circuit having the same reference numeral as that of the conventional example of FIG. 2 has the same configuration and function. In this embodiment, an error correction word asynchronous detection circuit 17, a carrier wave asynchronous detection circuit 19, an intermittent reset generation circuit 22, a flip-flop circuit 15, an AND circuit 13 and an inversion circuit 14 are added to this conventional example. .

In this embodiment, as shown in FIG. 1, multipliers 1 and 2 which are carrier wave synchronizing circuits, a carrier wave voltage controlled oscillator 20, a π / 2 phase shifter 21, low-pass filters 3 and 4, an amplifier. 5 and 6, AD converters 7 and 8, clock recovery circuit 9, exclusive OR circuits 11 and 12, subtractor 16
In addition, the loop filter 18 and the error correction circuit 10 are provided, and as a feature of the present invention, the carrier wave arriving at the carrier wave synchronization circuit is in a synchronous state and the error correction word of the error correction circuit is asynchronous. Error correction word asynchronous detection circuit 17 and carrier asynchronous detection circuit 19 which are means for detecting the pseudo synchronization state when the state is in the state, and the carrier synchronization circuit for the time period from the pseudo synchronization detection to the normal synchronization state. An inverting circuit 14, an AND circuit 13, an intermittent reset generating circuit 22 and a flip-flop circuit 15 which are means for alternately repeating the above state 2 into two states, a stopped state and an oscillating state.

Next, the operation of this embodiment will be described. During pseudo synchronization, data is not correctly identified because it is synchronization with different frequencies. That is, the error correction word is asynchronous and the carrier wave is synchronous. At this time, if the synchronization of the carrier wave is once removed and pulled into the normal synchronization, the carrier wave pull-in range can be expanded. Here, the output of the error correction word asynchronous detection circuit 17 is high level when word asynchronous, low level when word synchronous, the output of the carrier asynchronous detection circuit 19 is high level when carrier asynchronous, low level when carrier synchronous, and the flip-flop circuit 15 When the reset terminal input is high level, the output is fixed and the output is fixed at low level. When the reset terminal input is low level, normal operation is performed. Further, the intermittent reset generation circuit 22 keeps the high level and the low level constant when the input is high level. Alternately output every time, and always output low level when the input is low level. If it is in the pseudo-synchronous state, the output h1 of the error correction word asynchronous detection circuit 17 becomes high level, the output h2 of the carrier asynchronous detection circuit 19 becomes low level, and further the h3 becomes high level by the inverting circuit 14, and the AND circuit 13 outputs Both inputs go high. Since the input h4 of the intermittent reset generation circuit 22 becomes high level, the high level and the low level are alternately input to the flip-flop circuit 15 at regular time intervals. On the other hand, in the normal synchronization state, both h1 and h2 are low level, and the inverting circuit 14 sets h3 to high level, and the AND circuit 1
The output h4 of 3 goes low. Then, the output of the intermittent reset generation circuit 22 is fixed to the low level. As a result, high level and low level are alternately input to the flip-flop circuit 15 in the pseudo-synchronized state. Therefore, when the level is high, the flip-flop circuit 15 is reset, carrier synchronization is lost, and low level is obtained. At the time of, it becomes a normal operation and tries to synchronize the carrier wave. This is repeated until the carrier wave is in normal synchronization, and once in normal synchronization state, the flip-flop circuit 15
Since a low level is input to, normal operation is performed.

As described above, according to the present embodiment, when the carrier wave is in the pseudo-synchronized state, the carrier wave is forcibly desynchronized and the pull-in is performed again. Then, this is repeated until the normal synchronization state is reached. As a result, the carrier synchronization pull-in range limited by the pseudo synchronization can be expanded. In particular, a sufficient synchronization pull-in range can be secured even in a carrier recovery circuit for demodulating a multilevel quadrature amplitude modulation wave having a low clock frequency.

Although the 16-valued quadrature amplitude modulation method has been described in the above embodiment, it can be applied to other multi-valued quadrature amplitude modulation method and multi-valued phase modulation method, and the same effect as the above embodiment can be obtained. In this case, the configuration is the same as that of this embodiment except that the number of output signal data is changed.

[0014]

As described above, the present invention detects that a carrier wave is in a pseudo-synchronized state from the error correction word asynchronous signal and the carrier wave synchronous signal, and in that case, the carrier wave is forcibly desynchronized. Since the pull-in is performed again and this is repeated until the normal synchronization state is achieved, the problem of the reduction of the synchronization width due to the influence of pseudo-synchronization of the carrier can be eliminated, and a sufficient carrier synchronization pull-in range can be secured.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block configuration diagram showing a configuration of a conventional example.

FIG. 3 is a diagram showing a relationship between a reproduction carrier frequency and an input carrier frequency.

[Explanation of symbols]

1, 2 Multiplier 3, 4 Low-pass filter 5, 6 Amplifier 7, 8 AD converter (AD) 9 Clock recovery circuit (CLK SYNC) 10 Error correction circuit (FEC) 11, 12 Exclusive OR circuit 13 AND circuit 14 Inversion circuit 15 Flip-flop circuit (FF) 16 Subtractor 17 Error correction word asynchronous detection circuit (WORD
DET) 18 Loop filter 19 Carrier asynchronous detection circuit (CARR DE
T) 20 Carrier wave voltage controlled oscillator (VCO) 21 π / 2 Phase shifter (π / 2) 22 Intermittent reset generation circuit (PLS GEN)

Claims (3)

[Claims] 1. A demodulator including a carrier synchronization circuit and an error correction circuit, wherein a carrier arriving at the carrier synchronization circuit is in a synchronous state and an error correction word of the error correction circuit is in an asynchronous state. Means for detecting that the carrier is in the pseudo-synchronous state, and the state of the carrier synchronization circuit can be alternately repeated into two states, the stopped state and the oscillating state, over the time period from the detection of the pseudo-synchronous state to the normal synchronous state. And a demodulating device. 2. The demodulator according to claim 1, wherein the demodulator is a 2N-phase demodulator. 3. The demodulator according to claim 1, wherein the demodulator is a 2 ^N- ary quadrature amplitude demodulator.