JPH05199430A - Video signal receiver - Google Patents

Abstract

(57) [Abstract] [Purpose] A device for receiving a video signal having a pulse separation stage 6, in which a sync pulse does not change its width and has a time delay with respect to an original sync signal of the video signal. Not provide equipment. [Configuration] The pulse separation stage 6 has a pulse shaping stage 16,
This pulse shaping stage 16 is connected after the amplitude separator 11, and the pulse shaping stage 16 forms a synchronizing pulse 15 whose starting edge 17 and ending edge 18 are temporally located in the original synchronizing signal 12. It is provided for.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The invention relates to a video signal receiving device having a pulse separation stage as claimed in the preamble of claim 1.

[0002]

2. Description of the Related Art Such a device is disclosed, for example, in the book "Television Reception Techniques", Third Edition, by Peter Zastrow, 198.
It is listed in the Frankfurt publishing company for 0 years. On pages 229 to 238 thereof, the principle of an amplitude separator which can remove the image content and possible disturbance signals from the original synchronization signal of the video signal is shown.

A problem with these known amplitude separator circuits is that the time course of the original synchronization signal remains unchanged. As a result, the sync signal prepared by the amplitude separator circuit is always delayed in time with respect to the original sync signal by the signal selection in the amplitude separator. Due to the short pre and after travants compared to the original sync signal during the image blanking interval, the line sync pulses provided by the known amplitude separator circuit are additionally variable in their width as well. Not desirable.

[0004]

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a device for receiving a video signal having a pulse separation stage, the sync pulse of which the width does not change and the original sync signal of the video signal. It is to provide a device that does not have a time delay.

[0005]

This problem is solved according to the invention by the features of claim 1.

An embodiment of the invention is the subject of claim 2 and the following.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in more detail below with reference to four drawings.

FIG. 1 shows an apparatus for receiving a video signal by a television receiver, which is for receiving a receiving section 10 for receiving and amplifying the video signal and for separating an original synchronization signal 12 from the video signal. 1 and a video signal processing stage 13 for processing the video signal according to the norm of the sync pulse which can be generated from the original sync signal. For simplicity, the audio paths in the television receiver are not shown in FIG.

The receiving section 10 has an antenna 1, to which a tuner 2 is connected, and thereafter, an image intermediate frequency amplifier 3 is connected. An FBAS (Farb-Bild-Austast-Synchron) signal can be taken out from the output end of the image intermediate frequency amplifier 3. This signal is on the one hand a video amplifier 4
On the one hand, and on the other hand to said pulse separation stage 6.
A BAS (Bild-Austast-Synchron) signal can be taken from the output of the pulse separation stage 6 which will be explained in more detail later. The pulse separation stage 6 also serves to filter out the color components from the FBAS signal. Preferably, the pulse separation stage 6 additionally serves also to remove high disturbance frequencies from the FBAS signal. The output end of the video amplifier 4 is connected to the picture tube 5. In addition, the television receiver according to FIG. 1 has a deflection device 7 which is connected to the output of the pulse separation stage 6 and serves for horizontal and vertical deflection of the video signal produced at the output of the video amplifier 4. ..
That is, the video signal processing stage 13 comprises a video amplifier 4, a deflection device 7 and a picture tube 5.

In the known devices for the reception of video signals with a pulse separation stage, it was customary to provide the pulse separation stage with an amplitude separator, possibly with a disturbing blankout. The amplitude separator serves to prepare a line sync pulse and an image sync pulse for image deflection from the original sync signal of the video signal, that is, from the original image sync signal and the original line sync signal. For simplicity, only the preparation of the line sync pulse will be explained below, but
This does not mean a limitation.

In the known amplitude separator circuit, the time delay of the synchronizing pulse at the output end of the amplitude separator circuit is inevitably caused by the signal selection in the amplitude separator circuit as compared with the original synchronizing signal of the video signal at the input end of the amplitude separator circuit. Occurs. Additionally, because the sync pulses at the output of the amplitude separator circuit are usually short equalized signals (also called pre- and after-travant) in the video signal, their width is reduced to the original line sync at the input of the amplitude separator circuit. Different depending on whether the signal is located or the equalization sync signal is located. However, this is problematic due to the time correct processing of the video signal.

According to the invention, therefore, a pulse shaping stage is connected after the amplitude separator circuit, the pulse shaping stage having the start and end edges temporally aligned with the original synchronization signal of the video signal. It is provided to form the positioning sync pulse.

To make it easier to understand, referring to FIG. 2, the FBAS signal is shown during the switching from the first half image to the second half image (assuming a 625 line television system). .. The switching from the first half image 1H to the second half image 2H takes place at the center of the 313rd image line. Half-image switching is indicated by the image-switching pulse 30 immediately preceding the half-image switching. Reference numeral 12 is a line synchronization signal, and reference numeral 31 is an equalization synchronization signal of the FBAS signal. The line duration is indicated by H in FIG. The equalization synchronization signal 31 has a half line spacing H.
It occurs at / 2. Without these equalization synchronization signals 31, called pre-trabant before the image-switching pulse 30 and after-trabant after the image-switching pulse 31, the image-switching cannot start exactly at the line center or at the start of the line. Will. Unlike the original line sync signal, which has a width of about 6 μs, the equalization sync signal 31 is about 2,
It has a smaller width of 3 μs.

The pulse separation stage 6 according to the invention comprises FBAS
A synchronizing pulse 15 is generated which is correctly positioned in time with respect to the synchronizing signals 12, 31 of the signal. In order to guarantee this correctness in time, one has to start from the shortest synchronization signal in time and thus also from the equalization synchronization signal 31.
The equalization sync signal 31 then defines the time window in which the sync pulse 15 to be generated from the pulse separation stage 6 has to be located. The time window of the equalization synchronization signal 31 is indicated by TA in FIG. The start edge 17 and the end edge 18 of the sync pulse 15 must be located in this time window TA.

FIG. 3 shows a block circuit diagram of the pulse separation stage according to the present invention. The pulse separation stage 6 comprises a pulse shaping stage 16 connected after the amplitude separator 11. In the pulse shaping stage 16, the start edge 17 and the end edge 18 are temporally the original synchronization signal 1 of the FBAS signal.
It is provided to form the sync pulse 15 located in 2, 31.

In a preferred embodiment of the invention, the pulse separation stage 6 is connected before the amplitude separator 11 and is provided for forming a BAS signal with high disturbance frequencies removed. It has a band pass filter 19.
The low pass filter 19 has a time delay t between the BAS signal at its output and the FBAS signal at its input.
Give rise to 1. Low-pass filter 19 from BAS signal
The pulse supplied to the pulse shaping stage 16 is obtained in the amplitude separator 11 connected after the pulse. The required sync pulse 1 from this pulse in the pulse shaping stage 16
5 is generated. The time delay t1 in the low-pass filter 19 is chosen so that the pulse at the output of the amplitude separator 11 has a defined delay with respect to the original sync signal of the video signal. The delay t1 is in all cases smaller than the time window TA of the original synchronization signal, preferably the time window TA.
Must be chosen to be less than half of. The pulse at the output of the amplitude separator 11 is temporally shortened by the pulse shaping stage 16 so that the end edge 18 of the sync pulse 15 is also located in the time window TA of the original sync signal. This is done in a particularly simple manner by means of a non-aftertriggerable monoflop, as will be explained in more detail in connection with FIG. It has been found to be expedient to choose the holding time t2 of the monoflop so that the following conditions are met: t2 <ts-2t1 where: t1 = lowpass filter delay t2 = monoflop Hold time ts = shortest time window of original sync signal (equalization time of image blanking interval in video signal)

FIG. 4 shows a possible embodiment of the pulse separation stage 6 of FIG. 3 by means of a concrete circuit arrangement. The amplitude separator 11 is connected to the −input terminal 110, the base terminal to the input terminal 110, and the collector terminal to the positive potential 20 via the first load 118.
Is connected to the reference potential 21 via the first current source 112, and the second emitter terminal is connected to the second potential.
Npn multi-emitter transistor 111 connected to the reference potential 21 via the current source 113, and the -emitter terminal connected to the first emitter terminal of the npn multi-emitter transistor 111, and the base terminal and collector terminal. Positive potential 2 via the first load 118
First npn transistor 114 connected to 0
-The base terminal is connected to the base terminal of the first npn transistor 114, the emitter terminal is connected to the second emitter terminal of the npn multi-emitter transistor 111, and the collector terminal is the third npn transistor. Second npn transistor 11 connected to positive potential 20 through 117 and second load 119
5, a capacitor 11 connected between the base terminal of the second npn transistor 115 and the reference potential 21.
6 and a second npn transistor 11 at the −emitter terminal
5 is connected to the collector terminal, and is connected to the positive potential 20 through the second load 119 at the collector terminal,
In addition, the third npn transistor 1 which is connected to its own collector terminal through the third load 120 at the base terminal
17, a third load 120 connected between the capacitor 116 and the collector terminal of the third npn transistor 117, and a positive potential 20 via the second load 119.
And an output terminal connected to.

The first load 118, the second load 119 and the third load 120 are configured as current mirror circuits with pnp multicollector transistors in this embodiment of the amplitude separator. The first load 118 has its emitter terminal connected to the positive potential 20, its base terminal connected to its first collector terminal and to the collector terminal of the first npn-Makci collector transistor 111, and also to the second The first pnp connected to the collector terminal of the first npn transistor 114 at the collector terminal of
It has a multi-collector transistor 180. The second load 119 has its emitter terminal connected to the positive potential 20, its base terminal connected to its first collector terminal and to the collector terminal of the third npn transistor 117, and also to its second collector. It is formed by a second pnp multi-collector transistor 181 connected at its terminal to the output terminal 121. The third load 120 is
The emitter terminal is connected to the base terminal and the first collector terminal of the second pnp multi-collector transistor 181, and the base terminal and the first collector terminal are connected to the base terminal of the third npn transistor 117. , A third collector terminal connected to the base terminal of the first npn transistor 114 and the base terminal of the second npn transistor 115 at the second collector terminal.
It is formed by the np multi-collector transistor 182.

The pulse shaping stage 16 of FIG. 4 is realized by a non-after-triggerable monoflop. Here, the non-after-triggerable mono-flop means a mono-flop whose first pulse of the pulse train always determines the switching time of the mono-flop. The mono-flop shown in FIG. 4 includes: -an input terminal 160; -a first resistor 161;
A connection point of the second resistor 162 and the third resistor 163, which includes the second resistor 162, the third resistor 163, and the fourth resistor 164 connected between the positive potential 20 and the reference potential 21. A series circuit connected to the input terminal 160 with
A fourth npn whose base terminal is connected to the input terminal 160, whose collector terminal is connected to the positive potential 20 and whose emitter terminal is connected to the reference potential 21 via the third current source 166. The transistor 165 and the reference potential 21 at the −base terminal via the second capacitor 169.
Connected to the emitter terminal of the fourth npn transistor 165 at the emitter terminal, and the first resistor 161 and the second resistor 162 at the collector terminal.
Fifth npn transistor 1 connected to the connection point of
67, and-the fifth npn transistor 16 at the base terminal
It is connected to the base terminal of 7 and the
A sixth npn transistor 168, which is connected to the emitter terminal of the npn transistor 167, and is also connected at the collector terminal to the positive potential 20 via the fourth load 170, and-on the one hand, the third resistor 163 and A fifth load 170 connected between the connection point of the fourth resistor 164 and the base terminal of the sixth npn transistor 168 on the other hand, -a fourth load 170 and a sixth resistor 173, And an output terminal 174 connected therebetween.

The fourth load 170 is a pnp transistor 1
It is configured as a current mirror circuit having 71 and 172. The emitter terminals of both pnp transistors 171 and 172 are connected to the positive potential 20. The base terminals of both transistors 171 and 172 are connected to each other and at the same time to the collector terminal of the pnp transistor 171 and the collector terminal of the npn transistor 168. The collector terminal of the pnp transistor 172 is, on the one hand, the output terminal 174 of the monoflop,
On the other hand, it is connected to the reference potential 21 via the resistor 173.

The low-pass filter 19 shown in FIG. 4 is connected to the -input terminal 190 and the input terminal 190 at the -base terminal, and the seventh resistor 192 and the current source 19 at the emitter terminal.
Is connected to the positive potential 20 via a series circuit with 3,
Also, at the collector terminal, the third capacitor 195 and the eighth capacitor
Of the first pnp transistor 191 connected to the reference potential 21 via the resistor 194 of the first source, the −emitter terminal connected to the connection point of the current source 193 and the seventh resistor 192, and the collector terminal connected to the reference potential 21. The ninth resistor 199 and the tenth resistor 2 which are connected to each other between the positive potential 20 and the reference potential 21 at the base terminal.
9th resistor 199 and 10th resistor 2 in series circuit with 00
The second pnp transistor 196 connected to the connection point with 00, the −base terminal connected to the collector terminal of the first pnp transistor 191, the collector terminal connected to the reference potential 21, and A third pnp transistor 197, which is connected to the positive potential 20 via another current source 198 at the emitter terminal, and-a third pnp
It has an output terminal 201 connected to the emitter terminal of the transistor 197.

[Brief description of drawings]

1 is a principle diagram of an apparatus for receiving a video signal having a pulse separation stage.

FIG. 2 is an image synchronizing signal at the time of switching from a first half image to a second half image in a television signal having 625 lines.

FIG. 3 is a principle diagram of a pulse separation stage according to the present invention.

FIG. 4 is a circuit device capable of the pulse separation stage of FIG.

[Explanation of symbols]

 6 pulse separation stage 10 reception section 11 amplitude separator 12 original synchronization signal 13 video signal processing stage 15 synchronization pulse 16 pulse shaping stage 17 start edge 18 end edge 19 low pass filter 20 positive potential 21 reference potential

Claims (9)

[Claims] 1. A receiving part (10) for receiving and amplifying a video signal and an original synchronization signal (1) from the video signal.
A pulse separation stage (6) having an amplitude separator (11) for separating 2) and a video signal processing for processing the video signal according to the norm of the sync pulse (15) that can be generated from the original sync signal (12) A video signal receiving device having a stage (13), the pulse separating stage (6) having a pulse shaping stage (16), the pulse shaping stage (16) being connected after the amplitude separator (11), A pulse shaping stage (16) is provided for forming a sync pulse (15) whose start edge (17) and end edge (18) are temporally located in the original sync signal (12). A video signal receiving device characterized by the above. 2. The FBAS signal is scheduled as a video signal, and the pulse separation stage (6) comprises an amplitude separator (1).
1. A low-pass filter (19) connected before 1) and arranged to form a BAS signal from which high disturbance frequencies have been removed from the FBAS signal. The described device. 3. Device according to claim 1, characterized in that a monostable multivibrator (monoflop) is provided as the pulse shaping stage (16). 4. Device according to claim 1, characterized in that the pulse shaping stage (16) is provided with a non-triggerable monoflop. 5. An amplitude separator (11) is connected to the input terminal (110) and to the input terminal (110) at the base terminal,
The collector terminal is connected to the positive potential (20) through the first load (118), and the first emitter terminal is connected to the first potential (20).
Connected to the reference potential (21) via the current source (112) of the second current source (112) and the second current source (1) at the second emitter terminal.
Np connected to the reference potential (21) via 13)
an n-multi-emitter transistor (111) connected to the first emitter terminal of the npn-multi-emitter transistor (111) at the emitter terminal, and a first load (11) at the base terminal and the collector terminal.
8) the first n connected to a positive potential (20)
a pn transistor (114), -the base terminal of which is connected to the base terminal of the first npn transistor (114) and the emitter terminal of which is connected to the second emitter terminal of the npn multi-emitter transistor (111), The collector terminal has a third np
n-transistor (117) and second load (119)
A second npn connected to a positive potential (20) via
A transistor (115), a capacitor (116) connected between the base terminal of the second npn transistor (115) and the reference potential (21), and a second npn transistor (115) at the emitter terminal.
It is connected to the collector terminal of the
Third npn transistor (117) connected to the positive potential (20) through the load (119) of the same and also connected at its base terminal to its own collector terminal through the third load (120). A third capacitor connected between the capacitor (116) and the collector terminal of the third npn transistor (117).
Device according to one of claims 1 to 4, characterized in that it has a load (120) of: and an output terminal connected to a positive potential (20) via a second load (119). .. 6. A first load (118) and a second load (1)
Device according to claim 5, characterized in that at least one of 19) and the third load (120) is configured as a current mirror circuit. 7. The pulse shaping stage is configured as a non-after-triggerable mono-flop, and also comprises: an input terminal (160), a first resistor (161), a second resistor (162) and a third resistor.
Resistance (163), positive potential (20) and reference potential (21)
A second resistor (162) and a third resistor (163) consisting of a fourth resistor (164) connected between
A series circuit connected to the input terminal (160) at the connection point of, and-connected to the input terminal (160) at the base terminal,
A fourth npn transistor (165) connected at the collector terminal to the positive potential (20) and at the emitter terminal to the reference potential (21) via the third current source (166), The base terminal is connected to the reference potential (21) through the second capacitor (169), and the emitter terminal is connected to the fourth potential (21).
Of the npn transistor (165) is connected to the emitter terminal of the first resistor (161) at the collector terminal.
And a fifth npn transistor (167) connected to the connection point of the second resistor (162), and-a base terminal connected to the base terminal of the fifth npn transistor (167) and an emitter terminal. A sixth npn transistor (168) connected to the emitter terminal of the fifth npn transistor (167) and to the positive potential (20) at the collector terminal via the fourth load (170); , The third resistance (163) and the fourth resistance (1
A fifth load (170) connected between the connection point of 64) and the base terminal of the sixth npn transistor (168) on the other hand, a fourth load (170) and a sixth resistance 7. Device according to one of claims 1 to 6, characterized in that it has an output terminal (174) connected to (173). 8. The fourth load (170) is configured as a current mirror circuit, and the output terminal (174) is, on the one hand, connected to the reference potential (21) via a sixth resistor (173). Device according to claim 7, characterized in that it is connected to the output of a current mirror circuit, which on the other hand forms the fourth load (170). 9. A low pass filter (19) is provided for removing high disturbance frequencies from the video signal and for filtering out color information, and also-an input terminal (190) and a base terminal. Is connected to the input terminal (190) with
A seventh resistor (192) and a current source (19
3) is connected to a positive potential (20) through a series circuit, and the collector terminal has a third capacitor (195)
And a reference potential (21) through the eighth resistor (194)
First pnp transistor (191) connected to
-The emitter terminal is connected to the connection point of the current source (193) and the seventh resistor (192), the collector terminal is connected to the reference potential (21), and the base terminal is connected to the positive potential ( 20) and a reference potential (21) connected between a ninth resistor (199) and a tenth resistor (20).
0), and a second pnp connected to the connection point between the ninth resistor (199) and the tenth resistor (200) in the series circuit.
A transistor (196),-the base terminal of which is connected to the collector terminal of the first pnp transistor (191), the collector terminal of which is connected to the reference potential (21) and the emitter terminal of which is another current A third pnp transistor (197) connected to a positive potential (20) via a source (198), and an output terminal (201) connected to the emitter terminal of the third pnp transistor (197). Device according to one of the claims 1 to 8, characterized in that it comprises: