JPH05199532A - Digital color encoder - Google Patents

Abstract

(57) [Summary] [Object] To provide a digital color encoder capable of digital quadrature balanced modulation with a simple circuit configuration, without being restricted by a sample rate clock, a CCD having a different number of pixels, and an NTSC / PAL system. A microcomputer for calculating a constant for quadrature balanced modulation, a memory for storing the constant, a multiplier for multiplying the color difference signal by the constant, and modulated color difference signals RY and B-
It is composed of an adder for adding Y and a bandpass filter of 3.58 MHz.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to balanced modulation for video cameras.

[0002]

2. Description of the Related Art FIG. 7 is a block diagram of a digital color encoder disclosed in Japanese Patent Publication No. 58-715. In the figure, 15, 16, 17, and 18 are A / D converters,
19 is a frequency multiplication circuit, 20, 21 and 22 are multipliers, 2
3, 24, 25, 26, 27 are adders, 28, 29, 3
0, 31 are multipliers, 32, 33, 34, 35 are 1-digit shift registers, 36, 37, 38 are shift registers, 3
Reference numerals 9 and 40 are adders, and 41 is a modulated color signal output terminal.

Next, the operation will be described. The carrier color signal of the NTSC system color television signal is formed by two vector synthesis in which the color difference signals RY and BY are balanced-modulated as shown in FIG. Figure 96 is 90 each
The carrier color signal is constructed by vector composition of four vectors having a phase difference of degrees, and these four vectors have amplitudes for the color difference signal components of RY and BY, respectively, as is clear from FIG. The respective algebraic sums of the two become zero, and the respective vector sums match the respective vector diagrams in the conventional balanced modulation shown in FIG.

The luminance signal is sampled by the A / D converter 15 using a sampling frequency of 4 fsc which is 4 times the fsc of the color sub-carrier frequency and converted into a digital signal.
On the other hand, the R, G, and B signals have a frequency of fsc by the A / D converter 16, the A / D converter 17, and the A / D converter 18, and each phase has the above-mentioned frequency of 4 fsc.
It is converted into a digital signal using four-phase sampling pulses synchronized with the sampling pulses of. The digital signals of the R, G and B signals are respectively multiplied by a multiplier 20, a multiplier 21 and a multiplier 2.
2 lead to 0.010011,0.10011,0.000 as shown in FIG.
Digital multiplication by 11 binary numbers is performed, and at the outputs of these multipliers, 0.30, 0.59, 0.
A digital operation is performed so as to have a gain of 11, and a luminance signal is formed by the adder 23.

Further, the luminance signal formed as described above and the digital signals of the R, G and B signals are added by the adder 24, the adder 25, the adder 26 and the adder 27 to obtain the digital color difference signal BY. , R−Y, −B + Y, −
Form R + Y. Next, the digital color difference signals of BY and -B + Y are 1 /
The digital color difference signals of R-Y and -R + Y multiplied by 2.03 are multiplied by 1 / 1.14 by the multiplier 30 and the multiplier 31, and further the 1-digit shift register 32, the 1-digit shift register 33, 1
The digit shift register 34 and the one digit shift register 35
Gives a gain of 1/2.

Of the digital color difference signals adjusted to the amplitude shown in FIG. 9 by the above digital operation, the BY signal is directly led to the adder 39, and -B + Y, RY, -R + Y.
Each color difference signal is guided to the shift register 36, the shift register 37, and the shift register 38, and a phase delay of 2 clocks, 3 clocks, and 1 clock is given by a clock pulse of 4 fsc at a rate of 1 clock 1/4 fsc. Then, it is led to the adder 39, and -R + Y, -B + Y, R at ¼ fsc intervals based on the BY signal.
A four-phase carrier color signal corresponding to each vector of FIG. 9 in which the arrangement of the digital color difference signals of the Y signal is repeated is formed, and the addition output is guided to the adder 40 to be added to the digital luminance signal, As an addition output, a signal obtained by sampling a standard system color television signal at a sampling frequency of 4 fsc and digitizing it is obtained from the output terminal 42.

[0007]

Since the conventional digital color encoder is constructed as described above, the orthogonal balanced modulation cannot be performed unless digital conversion is performed at an integral multiple of the color sub-carrier frequency fsc. There was a point.

The above circuit configuration is compatible with the NTSC system and is P
The AL method also has a problem that a separate circuit must be provided.

Since the digital conversion is performed at an integral multiple of the color sub-carrier frequency fsc, there is a problem that the number of pixels of the CCD for photoelectric conversion is limited.

The present invention has been made to solve the above problems, and an object thereof is to obtain a digital color encoder with a simple circuit configuration.

[0011]

A digital color encoder according to the present invention comprises a multiplier for multiplying a color difference signal by a constant for balanced modulation, a memory for outputting a constant for balanced modulation, an address generator, and a modulator. The color difference signal is provided with an adder and a bandpass filter, and the color difference signal is multiplied by a constant output from the memory to perform balanced modulation.

A multiplier for multiplying the color difference signal by a constant for balanced modulation; a memory for outputting a constant for balanced modulation;
An address generator, a microcomputer that outputs a constant for balanced modulation to the memory, an adder that adds the modulated color difference signals,
It is provided with a band pass filter, writes a constant for balanced modulation from the microcomputer in the memory, and multiplies the color difference signal by the constant output from the memory for balanced modulation.

Furthermore, a multiplier for multiplying the color difference signal by a constant for balanced modulation, a memory for outputting a constant for balanced modulation, an address generator, and a microcomputer for outputting a constant for balanced modulation to the memory, Equipped with an adder for adding the modulated color difference signals and a band pass filter, the microcomputer writes a constant for constant modulation for four horizontal scanning lines into the memory, and the color difference signal is multiplied by the constant output from the memory. Balance modulation.

[0014]

The digital color encoder according to the present invention,
The digital data for each pixel is multiplied by the constant output from the memory.

In the digital color encoder according to the present invention, the digital data for each pixel is multiplied by the constant calculated by the microcomputer and output from the memory.

Furthermore, the digital color encoder according to the present invention multiplies the digital data for each pixel by the data output from the memory, which is switched line by line.

[0017]

EXAMPLES Example 1. FIG. 1 is a block diagram showing a digital color encoder according to an embodiment of the present invention.
In the figure, 1 is a CCD, 2 is a process circuit, and 3 is A /
D converter, 4 drive circuit, 5 timing generator (hereinafter referred to as TG), 6 process circuit, 7 multiplier, 8 multiplier, 9 adder, 10 BPF, 11 memory, 12 address A generator, 13 is a digital luminance signal output terminal, and 14 is a digital modulation color signal output terminal.

A description will be given below with reference to the drawings. The video signal photoelectrically converted by the CCD 1 is C by the process circuit 2.
Performs signal processing such as DS and AGC. Drive circuit 4 is TG5
A drive pulse for driving the CCD is generated by the sensor reading clock input from the. The video signal output from the process circuit 2 is digitally converted by the A / D converter 3 at the sensor reading clock frequency. After that, the digital video signal is subjected to signal processing such as color separation, white balance, and matrix by the process circuit 6, and the process circuit 6 outputs a digital luminance signal and a digital color difference signal.

FIG. 2 is a diagram showing constants for balanced modulation according to the present invention. A is a color difference signal output from the process circuit and is digital data for each pixel at an interval of 1 / (sensor reading clock) because it is digitally converted at the sensor reading clock frequency. B is a color subcarrier and has a frequency of fsc (3.58 MHz). Sampling frequency between pixels, that is, at the time of digital conversion is 3.58
If the Nyquist frequency of MHz is satisfied, the color subcarrier constants k1, k2, k corresponding to 1 of each pixel
By multiplying by 3 ..., Modulation can be performed at fsc (3.58 MHz). Also, C is π compared to the color subcarrier of B
It is a color subcarrier of frequency fsc with a phase delay of / 2.

Color difference signal R output from process circuit 6
-Y is a constant k output from the memory 11 by the multiplier 7.
1, k2, k3 ... Are multiplied and modulated at a frequency of fsc. Further, the color difference signal BY is stored in the memory 1 by the multiplier 8.
.., which is output from 1 and is multiplied by s1, s2, s3 ..., And is modulated at a frequency of fsc whose phase is delayed by π / 2 as compared with the above-described modulated color difference signal RY. The address circuit 12 specifies the address of the data in the memory 11.

FIG. 3 is a diagram showing the relationship between the phase of the NTCS color subcarrier and the line and field. NT
In the SC system, the phase of the color subcarrier is inverted every line as shown in FIG. Further, as shown in FIG. 3, the phase of C is delayed by π / 2 from that of B for each field. Therefore,
As shown in FIG. 2, the color difference signal R-Y is multiplied by constants k1, k2, k3 ... In n lines (N fields),
+1 line (N field), k'1, k'2, k '
The constants of 3 ... The next field (N
In the (+1 field), as shown in FIG. 2D, the constant of the color subcarrier whose phase is delayed by π compared with FIG. 2B is multiplied. The color difference signals BY are s1, s2, s for n lines (N fields).
The constants of 3 ... Are multiplied, and in the n + 1 line (N field), the constants of s'1, s'2, s'3 ... Further, as in the color difference signal RY, in the N + 1 field, as shown in FIG. 2E, the constant of the color subcarrier whose phase is delayed by π compared with FIG. 2C is multiplied.

As described above, the color difference signal modulated at the frequency of fsc is added by the adder 9 to the color difference signal RY and the color difference signal BY, and is passed through the BPF 10 having the frequency characteristic of 3.58 MHz. The balanced color-modulated color difference signal is obtained and output from the digital color difference signal output terminal 14.

Example 2. FIG. 4 is a block diagram showing a digital color encoder according to another embodiment of the present invention. In the figure, 1 to 10 and 12 to 14 are the same as those in the first embodiment, and their explanations are omitted. 42 is a RAM and 43 is a microcomputer.

A description will be given below with reference to the drawings. The process up to the output of the digital luminance signal and the digital color difference signal from the process circuit 6 in the figure is the same as in the first embodiment, and the description thereof is omitted.

Since the A / D converter 3 performs digital conversion with the sensor reading clock output from the TG 5, the number of pixels of the CCD is different, so that the sampling rate of the digital data is naturally different depending on the CCD having the different sensor reading clock. different. The microcomputer 43 calculates a constant for modulation output from the RAM 42, which is multiplied by the multiplier 7 and the multiplier 8 according to the sensor reading clock of the CCD used, and outputs it to the RAM 42. As shown in FIG. 5, when the CCD of A is used, k1 and k
, K3 ..., When using B CCD, s1, s
2, s3 ... Are output from the microcomputer 43. RAM42
Stores the data output from the microcomputer 43, and according to the address of the address generator, the multiplier 7 and the multiplier 8
Output to.

The multipliers 7 and 8 multiply the digital color difference signal by the data output from the RAM 42, and the adder 9 adds the color difference signal RY and the color difference signal BY.
A balanced color-modulated color difference signal is obtained by passing through the BPF 10 having a frequency characteristic of 3.58 MHz, and is output from the digital color difference signal output terminal 14.

Also in the PAL system, similarly to the above, if the microcomputer 43 calculates a constant for balanced modulation by the sensor reading clock of the CCD used in the camera system and outputs it to the RAM 42, the quadrature balanced modulation in the PAL system is also obtained. It goes without saying that it is possible.

Example 3. FIG. 4 is also used in this embodiment.
In the figure, 1 to 10, 12 to 14, 42, and 43 are the same as those in the second embodiment, and the description thereof is omitted.

A description will be given below with reference to the drawings. The process up to the output of the digital luminance signal and the digital color difference signal from the process circuit 6 in the figure is the same as in the first embodiment, and the description thereof is omitted.

Since the A / D converter 3 performs digital conversion with the sensor reading clock output from the TG 5, the C having a different number of pixels with a different sensor reading clock is used.
Naturally, the sampling rate of digital data differs depending on the CD. The microcomputer 43 calculates a constant for modulation output from the RAM 42, which is multiplied by the multiplier 7 and the multiplier 8 according to the sensor reading clock of the CCD used,
The constants A, B, C and D shown in FIG. 6 are output to the RAM 42 for four lines. The RAM 42 stores the data output from the microcomputer 43. The data stored by the RAM 42 is shown in FIG.

In the line B shown in FIG. 3, the color difference signal R
6Y is modulated by the data shown in FIG. 6A, and the color difference signal BY is modulated by the data shown in FIG. 6B.
On the next line n + 1 (FIG. 3C), the address generator 12 calls the color difference signal RY the constant data shown in FIG. 6C in the RAM 42 and outputs it from the RAM 42. The color difference signal BY is shown in FIG.
The data of the constant shown in (4) is called and output from the RAM 42. As described above, in the N field, the color difference signal R
-Y is the constant data of A shown in FIG. 6 and the constant data of C is output from the RAM 42 for each line, and the color difference signal BY is the constant data of B shown in FIG. The constant data is output from the RAM 42 for each line.

In the N + 1 field, the color difference signal RY in the line B shown in FIG. 3 is the constant data shown in FIG. 6B, and the color difference signal BY is shown in FIG. 6C.
The data of the constants shown in is output from the RAM 42. That is, in the N + 1 field, the color difference signal R-Y is the constant data of B shown in FIG. 6 and the constant data of D is output from the RAM 42 for each line, and the color difference signal B-Y is shown in C of FIG. The constant data and the constant data of A are output from the RAM 42 for each line.

6A, 6B, 6C and 6D also in the PAL system.
It goes without saying that the combination can be modulated by designating the combination by the address generator 12.

[0034]

As described above, according to the invention of claim 1,
With a simple circuit configuration, quadrature balanced modulation can be performed even if the clock rate for digital conversion and the clock rate for digital data are not integral multiples of the color subcarrier frequency fsc. PA
The same configuration can be applied to any of the L systems.

As described above, according to the second aspect of the present invention, the quadrature balanced modulation is performed with a simple circuit configuration even if the clock rate for digital conversion and the clock rate of digital data are not integral multiples of the color subcarrier frequency fsc. Can perform NTSC / PAL for any CCD
Any of the methods can be supported without rewriting the memory.

As described above, according to the invention of claim 3, the quadrature balanced modulation is performed with a simple circuit configuration even if the clock rate for digital conversion and the clock rate of digital data are not integral multiples of the color subcarrier frequency fsc. Can perform NTSC / PAL for any CCD
Any of the methods can be supported without rewriting the memory. In addition, the data capacity of the memory can be significantly reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a digital color encoder according to an embodiment of the present invention.

FIG. 2 is a diagram showing constants for quadrature balanced modulation.

FIG. 3 is a diagram showing a relationship between a phase of a color subcarrier and lines and fields.

FIG. 4 is a block diagram showing a digital encoder according to another embodiment of the present invention.

FIG. 5 is a diagram showing constants for quadrature balanced modulation corresponding to CCDs having different numbers of pixels.

FIG. 6 is a diagram showing constants for quadrature balanced modulation.

FIG. 7 is a block diagram showing a conventional digital color encoder.

FIG. 8 is a vector diagram showing a carrier color signal of a color television signal.

FIG. 9 is a vector diagram showing a 4-phase carrier color signal used in a digital color encoder.

[Explanation of Codes] 1 CCD 2 Process Circuit 3, 15-18 A / D Converter 4 Driving Circuit 5 Timing Generator 6 Process Circuit 7, 8 20-22, 28-31 Multiplier 9, 23-27 39, 40 Adder 10 band pass filter 11 memory 12 address generator 13 digital luminance signal output terminal 14 digital modulation chrominance signal output terminal 19 frequency * multiplication circuit 32-35 1 digit shift register 36-38 shift register 41 digital signal output terminal 42 RAM 43 microcomputer

Claims (3)

[Claims] 1. In balanced modulation of a video camera, a multiplier for multiplying a color difference signal by a constant for balanced modulation, a memory for outputting a constant for balanced modulation, an address generator, and a modulated color difference signal are added. A digital color encoder including an adder and a bandpass filter, wherein the color difference signal is multiplied by a constant output from a memory to perform balanced modulation. 2. In balanced modulation of a video camera, a multiplier for multiplying a color difference signal by a constant for balanced modulation, a memory for outputting a constant for balanced modulation, an address generator, and a constant for balanced modulation to the memory. Equipped with a microcomputer that outputs a signal, an adder that adds the modulated color difference signals, and a bandpass filter.The microcomputer writes a constant for balanced modulation to the memory, and the color difference signal is multiplied by the constant output from the memory to balance A digital color encoder characterized by modulation. 3. In balanced modulation of a video camera, a multiplier for multiplying a color difference signal by a constant for balanced modulation, a memory for outputting a constant for balanced modulation, an address generator, and a constant for balanced modulation to the memory. It is equipped with a microcomputer that outputs the signal, an adder that adds the modulated color difference signals, and a bandpass filter. The microcomputer writes the constants for balanced modulation for four horizontal scanning lines into the memory, and the color difference signals from the memory. A digital color encoder characterized in that the output constant is multiplied to perform balanced modulation.