JPH0520121U - Malfunction prevention device for micro computer system - Google Patents

Abstract

(57) [Abstract] [Purpose] Avoid runaway of the auxiliary CPU. A microcomputer system having a main CPU and an auxiliary CPU, wherein a reset circuit 4 is provided in the auxiliary CPU 2.
Reset signal (L level)
Is monitored by the main CPU 1 and, if it is output a predetermined number of times or more within a predetermined time, a continuous reset signal (L level) is given in order to give up the recovery of the auxiliary CPU 2 and stop its use.
Is output to the auxiliary CPU 2 via the AND circuit 5.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a malfunction prevention device for a microcomputer system, and more particularly to a malfunction prevention device for a microcomputer system including two CPUs, a main CPU and an auxiliary CPU.

[0002]

[Prior Art]

 2. Description of the Related Art A microcomputer system mounted on an automobile has two CPUs, a CPU (main CPU) for controlling an engine and a CPU (auxiliary CPU) for diagnosing a misfire or diagnosing an oxygen sensor abnormality. is there. Further, as shown in FIG. 4, from the main CPU 1 and the auxiliary CPU 2, when they are functioning normally, a program run (P-RUN) signal which is inverted at a predetermined cycle is output from the first reset circuit 3 and the first reset circuit 3. 2 is output to each of the two reset circuits 4, and the first reset circuit 3 and the second reset circuit 4 monitor the cycle of these program run signals, and when the cycle is not a predetermined cycle, the CPU concerned On the assumption that the runaway has occurred, a reset signal (L level signal) of a fixed time width is output to the CPU 1 or 2 for resetting, the function of the CPU is restored by resetting, and the program run is executed. The signal cycle is made to return to normal (see Japanese Utility Model Laid-Open No. 63-20246).

[0003]

[Problems to be solved by the device]

 However, in such a conventional malfunction prevention device, as shown in FIG. 5, when an abnormality occurs in the cycle of the program run signal from the auxiliary CPU 2 for resetting, the first reset signal causes If the CPU does not return to normal, the second reset signal is output at a predetermined interval, and the reset signal is output intermittently until the CPU returns to normal. Between the reset signal and the reset signal, the CPU in a runaway state is activated, which naturally causes an abnormal output and deteriorates system reliability.

The present invention has been made in view of such conventional problems, and an object thereof is to provide a malfunction preventing device for a microcomputer system capable of further improving the reliability of the system.

[0005]

[Means for Solving the Problems]

 In order to achieve the above object, the present invention is a micro computer system including a main CPU and an auxiliary CPU, wherein a program run signal that is periodically output during normal operation of both CPUs is input and the program is executed. A first reset circuit for the main CPU and a second reset circuit for the auxiliary CPU, which outputs a reset signal having a constant time width to the CPU when the run signal is abnormal and resets the CPU, Forced continuous monitoring of the generation of a reset signal by the second reset circuit to the main CPU and forcibly outputting a continuous reset signal to the auxiliary CPU when the reset signal is output a predetermined number of times or more within a predetermined time. The configuration is such that reset means is provided.

[0006]

[Action]

 According to the above configuration, the forced continuous reset means provided in the main CPU monitors the generation of the reset signal by the second reset circuit, and when the reset signal is output a predetermined number of times or more within a predetermined time, the auxiliary The recovery of the CPU is abandoned, and the auxiliary CPU is forced to output a continuous reset signal. As a result, it is possible to avoid the inconvenience caused by the operation of the auxiliary CPU in an abnormal state during the generation of the reset signal which is intermittently output with a constant time width. In the case of an auxiliary CPU that is not related to the main control of the system, for example, for diagnosis, even if the operation is stopped, the basic control of the system is not hindered.

[0007]

【Example】

 An embodiment of the present invention will be described below with reference to FIGS. The system of the present embodiment will be described with reference to FIG. A main CPU (for engine control, for example) 1 and an auxiliary CPU (for diagnosis for misfire, etc.) 2 are built in one control unit. When it is operating normally, the main CPU 1 periodically outputs a program run signal to the first reset circuit, and the first reset circuit 3 monitors the cycle, and when there is an abnormality, it outputs a fixed time width. The reset signal is output to the main CPU 1 to recover the main CPU.

On the other hand, the auxiliary CPU 2 also periodically outputs a program run signal to the second reset circuit 4 when it is operating normally. The reset signal output port A of the second reset circuit 4 is connected to the reset terminal B of the auxiliary CPU 2 via the AND circuit 5. In addition, in order to monitor the generation of the reset signal (L level), the reset signal output port A of the second reset circuit 4 is connected to the input port C 1 of the main CPU 1 and the output of the main CPU 1 is output to enable forced reset. The port D 1 is connected to the reset terminal B of the auxiliary CPU 2 via the AND circuit 5.

The main CPU 1 receives the reset signal from the second reset circuit 4 at its input port C, and when the reset signal is detected a predetermined number of times or more within a predetermined time, the forced continuous reset means outputs the signal. A continuous L level signal is output from the port D through the AND circuit 5 to the reset terminal B of the auxiliary CPU to stop its operation. The routine as the forced continuous reset means will be described with reference to the flowchart of FIG.

In step 1 (denoted as S1 in the figure; the same applies hereinafter), it is determined whether or not a reset signal is input from the second reset circuit 4 to the input port C 1 of the main CPU 1, and when it is input (YES in YES). When) Go to step 2. In step 2, the count value n for reset signal measurement is incremented by 1 (see FIG. 3), and in step 3, it is determined whether the value is 1 or not. To start.

Next, in step 5, it is determined whether or not a predetermined time has elapsed from the timer value. If the predetermined time has not elapsed (NO), in step 6, the count value n is equal to or greater than the predetermined value. If NO, the auxiliary CPU 2 assumes that the runaway CPU 2 is not continuously running out of control, and this routine is ended, but if YES, the reset signal is output a predetermined number of times or more within a predetermined time. Since this has been output, in order to give up the recovery of the auxiliary CPU 2 and stop its use, proceed to step 7 and forcibly output a continuous L level reset signal (see FIG. 3) to the AND circuit 5. Output to the auxiliary CPU 2 via the auxiliary CPU 2 to stop the use of the auxiliary CPU 2 and terminate this routine.

On the other hand, if the result of the determination by the CPU 5 is YES, the process proceeds to step 8, the count value is returned to 0 for the next time, and the timer is reset in step 9 to end the routine.

[0013]

[Effect of the device]

 As described above, according to the present invention, when the program run signal from the auxiliary CPU is abnormal, a reset signal having a constant time width is intermittently output to recover the function. If the function recovery of the auxiliary CPU, which requires the output of a reset signal, cannot be expected, give up the function recovery and force the main CPU to send a continuous reset signal to the auxiliary CPU so that the auxiliary CPU is not used. Since the output is performed, it is possible to avoid using the auxiliary CPU in an abnormal state while the intermittent reset signal is generated.

[Brief description of drawings]

FIG. 1 is a system diagram showing an embodiment of the present invention.

FIG. 2 is a flowchart showing the control contents of the present embodiment.

[Fig. 3] Time chart showing signals during runaway

FIG. 4 is a system diagram showing a conventional example.

FIG. 5 is a time chart showing signals during a conventional runaway.

[Explanation of symbols]

 1 main CPU 2 auxiliary CPU 4 second reset circuit 5 AND circuit

Claims (1)

[Scope of utility model registration request] 1. A microcomputer system comprising a main CPU and an auxiliary CPU, each of which inputs a program run signal that is periodically output during normal operation of both CPUs, and a predetermined period of time when the program run signal is abnormal. Output a width reset signal to the CPU
Reset circuit for main CPU and auxiliary C
A second reset circuit for PU, wherein the main CPU monitors the generation of a reset signal by the second reset circuit, and when the reset signal is output a predetermined number of times or more within a predetermined time, the auxiliary CPU A malfunction preventing device for a microcomputer system, comprising: a forced continuous reset means for forcibly outputting a continuous reset signal.