JPH052019B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a phase-locked oscillator that is often used in communication devices, etc., and in particular, the present invention relates to a phase synchronized oscillator that is often used in communication devices, etc., and in particular maintains the frequency before the failure even after the reference input signal of the oscillator becomes a failure. The present invention relates to a phase-locked oscillator that can be used as a phase-locked oscillator.

[Conventional technology]

An example of a conventional phase synchronized oscillator is shown in FIG. 3 and will be described.

As shown in FIG. 3, the conventional phase-locked oscillator compares the phase output of the reference input signal applied to the input terminal 100 and the output signal of the voltage-controlled oscillator 5, and applies a voltage proportional to this phase difference to the above-mentioned voltage. Phase comparator circuit 1 that provides a control voltage to voltage controlled oscillator 5
It consists of

[Problem that the invention seeks to solve]

In the conventional phase-locked oscillator described above, if a failure occurs in the reference input signal applied to the input terminal 100, the phase difference between the two signals applied to the phase comparator circuit 1 generally becomes undefined. As a result, the control voltage applied from the phase comparator circuit 1 to the voltage controlled oscillator 5 also becomes unstable, causing the problem that the output frequency of the voltage controlled oscillator 5 differs greatly from the frequency before the failure occurred in the reference input signal. Ta.

In order to compensate for the above-mentioned problems in conventional phase-locked oscillators, it is known that the voltage-controlled oscillator 5 has an added function that allows the voltage-controlled oscillator 5 to generate its center frequency when the reference input signal becomes an obstacle. .

However, even in conventional phase oscillators with such a function, the center frequency of the voltage controlled oscillator 5 and the output frequency when the reference input signal is normally applied are different, so the above problem cannot be essentially solved. I couldn't do it.

[Means for solving problems]

The phase synchronized oscillator according to the present invention includes a voltage controlled oscillator, a counting circuit that adds or subtracts a given clock signal according to a control signal, and converts the output signal of this counting circuit into a voltage to be controlled by the voltage controlled oscillator. A digital-to-analog conversion circuit that provides a voltage, a phase comparison circuit that generates a voltage according to the phase difference between the output signal of the voltage controlled oscillator and a reference input signal, and control of the output voltage of the phase comparison circuit and the voltage controlled oscillator. A voltage comparison circuit that compares voltages and provides a control signal to the counting circuit; a clock generation circuit that generates a clock signal; a fault detection circuit that detects a fault in the reference input signal; and a logic circuit whose other input is a clock signal from the clock generation circuit, blocks the clock signal in accordance with the output signal of the fault detection circuit, and supplies a clock signal to the counting circuit. This is what I did.

[Effect]

In the present invention, even if the reference input signal becomes a failure, its output frequency is maintained at the value before the failure occurred in the reference input.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram showing one embodiment of a phase-locked oscillator according to the present invention.

In the figure, 100 is an input terminal to which a reference input signal is applied, and 200 is an output terminal from which an output signal is obtained.

1 is a phase comparison circuit that compares the phases of the reference input signal from the input terminal 100 and the output signal of the voltage controlled oscillator 5 and generates a voltage according to the phase difference; 2 is the output voltage of this phase comparison circuit 1; This voltage comparison circuit compares the control voltage of the voltage controlled oscillator 5 and provides a control signal to a counting circuit, which will be described later.This voltage comparison circuit 2 is configured to generate two logic levels according to the voltage difference between the two. There is. For convenience, when the output voltage of the phase comparison circuit 1 is higher than the control voltage of the voltage controlled oscillator 5, a logic level "1" is generated, and when it is lower than the control voltage, a logic level "0" is generated. shall occur.

Reference numeral 3 denotes a counting circuit which adds or subtracts the applied clock signal according to the control signal applied from the voltage comparator circuit 2, and is constituted by an up-down counter or the like. In this embodiment, when a logic level "1" is given as a control signal, addition counting is performed, and when a logic level "0" is given, subtraction counting is performed.

4 is a digital-to-analog conversion circuit (hereinafter referred to as a D/A conversion circuit) that converts the digital signal that is the output signal of this counting circuit 3 into an analog voltage and provides a control voltage to the voltage controlled oscillator 5; 6 is a counting circuit; A clock generation circuit generates a clock signal to be applied to the circuit 3, and 7 is a fault detection circuit that detects a fault in the reference input signal.This fault detection circuit 7 has a logic level of "1" when there is no fault in the reference input signal. Outputs logic level “0” in fault condition.
is configured to output. 8 has the output signal of this fault detection circuit 7 as one input, the clock signal from the clock generation circuit 6 as the other input, blocks the clock signal in accordance with the output signal of the fault detection circuit 7, and sends a clock signal to the counting circuit 3. As mentioned above, this logic circuit 8 is a logic circuit that gives
The clock signal from the clock generation circuit 6 and the output signal from the fault detection circuit 7 are used as two input signals, and in this embodiment, it is a simple AND circuit. As a result, when the reference input signal is normal, the clock signal from the clock generation circuit 6 is given to the counting circuit 3, but when the reference input signal is in a faulty state, it is blocked by the logic circuit 8 and the clock signal is sent to the counting circuit 3. is not given a clock signal.

Next, the operation of the embodiment shown in FIG. 1 will be explained.

First, the operation when the reference input signal is normal will be explained.

When the reference input signal applied to the input terminal 100 is normal, the fault detection circuit 7 generates a logic level "1", so the clock signal from the lock generation circuit 6 is sent to the counting circuit 3 via the logic circuit 8. Given.

The phase comparator circuit 1 generates a voltage corresponding to the phase difference between the input and output signals of the phase synchronized oscillator shown in FIG. Further, this voltage is always compared with the control voltage of the voltage controlled oscillator 5 by the voltage comparator circuit 2.

As a result of this voltage comparison, if the output voltage of the phase comparison circuit 1 is higher than the control voltage of the voltage controlled oscillator 5, the voltage comparison circuit 2 outputs a logic level "1", so the counting circuit 3 performs addition counting. . As a result, the counting result output of the counting circuit 3 increases, so
The control voltage of the voltage controlled oscillator 5, which is the output of the D/A conversion circuit 4 that converts this signal into an analog voltage, also increases.

Conversely, when the output voltage of the phase comparator circuit 1 is lower than the control voltage of the voltage controlled oscillator 5, the voltage comparator circuit 2 outputs logic level "0", so the counting circuit 3 performs subtraction counting,
The output voltage of the D/A conversion circuit 4 decreases.

As a result of the above, in the phase synchronized oscillator of the present invention, the output voltage of the phase comparison circuit 1 and the control voltage of the voltage controlled oscillator 5 are controlled to be always equal to each other.
Except for a slight quantization error, the operation is equivalent to that of a conventional phase synchronized oscillator in which the output voltage of the phase comparison circuit 1 is directly given as the control voltage of the voltage controlled oscillator 5.

Next, the operation when a failure occurs in the reference input signal applied to the input terminal 100 will be described.

When the above state occurs, the fault detection circuit 7 immediately detects the fault and generates a logic level "0". As a result, the clock signal from the clock generation circuit 6 is blocked in the logic circuit 8 and is not applied to the counting circuit 3. Therefore, the output signal of the counting circuit 3 retains the value before the failure occurred in the reference input signal. Therefore, the output voltage of the D/A conversion circuit 4 that converts this signal into an analog voltage, that is, the control voltage of the voltage controlled oscillator 5, also maintains the value before the failure occurred in the reference input signal, so the voltage controlled oscillator The output frequency of No. 5 remains unchanged at the value before the failure occurred in the reference input signal.

As explained above, the phase-locked oscillator of the present invention performs the same operation as a conventional phase-locked oscillator when the reference input signal is normal, and when a failure occurs in the reference input signal, it operates as before the failure. Frequency can be maintained.

Note that, in order to facilitate the explanation of the operation, the embodiment shown in FIG. Although the case where the present invention is applied has been shown, the present invention can also be applied to a phase-locked oscillator having a loop filter, so this case will be described below.

FIG. 2 is a block diagram showing another embodiment of the present invention, showing a phase-locked oscillator having a loop filter.

In FIG. 2, the same reference numerals as in FIG. 1 indicate corresponding parts, and 9 is a loop filter inserted between the phase comparator circuit 1 and the voltage comparator circuit 2.

The output signal of the phase comparator circuit 1 is given to the voltage comparator circuit 2 via this loop filter 9, so if the reference input signal is normal, voltage control is performed in the same way as explained for FIG. The control voltage of the oscillator 5 is controlled to be equal to the output voltage of the loop filter 9.

Therefore, the phase-locked oscillator shown in FIG. 2 exhibits the same operating characteristics as a phase-locked oscillator having a conventional loop filter. Furthermore, even if a failure occurs in the reference input signal, the output voltage of the loop filter 9 before the failure occurs in the reference input signal is maintained, as in the case shown in FIG. 1 above, so the output frequency changes. do not.

As is clear from the embodiment shown in FIG. 2, the phase-locked oscillator of the present invention has a D/A conversion circuit so that the signal is equal to the control voltage of the voltage-controlled oscillator in the conventional phase-locked oscillator. Since the phase synchronization oscillator is controlled and its value is held by a digital signal, no restrictions are placed on the characteristics or presence or absence of the phase comparator circuit and loop filter that constitute the phase synchronized oscillator. Therefore, various characteristics when the reference input signal is normal can be made equivalent to those of a conventional phase-locked oscillator.

〔Effect of the invention〕

As explained above, according to the present invention, with a simple circuit configuration, when the reference input signal is normal,
It has the same characteristics as a conventional phase-locked oscillator, and even if a failure occurs in the reference input signal, it maintains the output frequency synchronized with the reference input signal before the failure, and it minimizes output frequency changes when the reference input fails. Since it can be made small, the practical effect is extremely large.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of a phase-locked oscillator according to the present invention, FIG. 2 is a block diagram showing another embodiment of the present invention, and FIG. 3 is a block diagram showing an example of a conventional phase-locked oscillator. It is. 1... Phase comparison circuit, 2... Voltage comparison circuit, 3
...Counting circuit, 4...D/A conversion circuit, 5...Voltage controlled oscillator, 6...Clock generation circuit, 7...
Fault detection circuit, 8...Logic circuit.

Claims (1)

[Claims] 1. A voltage controlled oscillator, a counting circuit that adds or subtracts a given clock signal according to the control signal, and a digital-to-analog converter that converts the output signal of this counting circuit into a voltage and provides a control voltage to the voltage controlled oscillator. a phase comparator circuit that generates a voltage according to the phase difference between the output signal of the voltage controlled oscillator and a reference input signal; and a counting circuit that compares the output voltage of the phase comparator circuit with the control voltage of the voltage controlled oscillator. a voltage comparator circuit that provides a control signal to the
A clock generation circuit that generates a clock signal, a failure detection circuit that detects a failure in the reference input signal, and an output signal of the failure detection circuit as one input, and a clock signal from the clock generation circuit as the other input. A phase synchronized oscillator comprising: a logic circuit that blocks the clock signal in response to an output signal of the fault detection circuit and provides a clock signal to the counting circuit.