JPH0520218A - Parity error notification method - Google Patents

Abstract

(57) [Summary] [Object] The present invention relates to a parity error notification method in a data processing system comprising a first device having a microprocessor and a local memory and a second device having a buffer memory, and a second method. It is an object of the present invention to prevent two interrupts from occurring in the first device due to the failure of the buffer memory of the first device. A second device includes a buffer control circuit that performs a parity check when transferring data in a buffer memory to the first device and outputs a parity error signal to the first device. The interrupt inhibiting circuit outputs an interrupt request to an interrupt handler that generates an interrupt to the microprocessor of the first device, and inputs a parity error signal of data sent from the second device. It is configured to suppress the generation of an interrupt request due to the generation of the parity error signal from the second device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parity error notification system in a system including a device having a buffer memory for transferring data with another device, a processor and a device having a local memory.

In the case of transmitting and receiving data between systems connected via a line of a network (LAN or the like), it is provided with a device which is connected to the network and temporarily stores the transmitted and received data in a buffer memory, this device, a processor and a local memory. A system composed of such devices is used in the field of information processing such as exchanges. In such a system, if a parity error occurs when a device connected to a network receives data and transfers it to a local memory, the processing becomes complicated, and its solution is desired.

[0003]

2. Description of the Related Art FIG. 5 is a system configuration diagram of a conventional example, and FIG. 6 is a processing flow in a conventional microprocessor.

In FIG. 5, the device A is connected to a host device (left side) such as a terminal device (not shown), and the device B is also connected.
And a processor bus (address line and control line), a DMA bus (data line), and an interrupt line. The device B is connected to another system (lower device) via a line (a line forming a network).

In the device A, 40 is a microprocessor (MPU), and 41 is an interrupt handler (IR) which generates an interrupt to the microprocessor in response to each interrupt request.
H), 42 are ROMs for storing microprograms, 4
3 is a local memory (LM), 44 is a DMAC (dynamic memory access controller), 45, 4
6 is a parity generation / parity check circuit (PG / P
C) and D / R are driver / receiver.

In the device B, 50 is an interrupt generation circuit (I
RG), 51 is a buffer memory (BFM), 52 is a buffer memory control circuit (BFMCTL), 53 and 54 are P
G / PC and D / R are driver / receivers.

In this configuration, the local memory 43 of the device A is used as a working memory of the microprocessor 40, and the buffer memory of the device B (hereinafter, BFM).
51) is used for temporary storage for data transfer with other lower-level devices via the network, and is a system that satisfies one function by connecting the devices A and B (for example, an information processing system). Make up.

The local memory 43 of the device A is B of the device B.
Data is mutually transferred between the FMs 51. Here, a case where the device B transfers the data received from the network to the local memory 43 of the device A will be described.

The data accumulated in the BFM 51 is DMAC'ed.
When transferring to the local memory 43 under the control of 44, B
A parity check is performed in the FM control circuit 52. At this time, when the BFM control circuit 52 detects a parity error, the interrupt generation circuit 50 is notified, and the interrupt generation circuit 50 supplies the interrupt handler 41 of the device A with the interrupt handler 41 to the microprocessor 40. An interrupt is generated.

On the other hand, when the data is transferred from the BFM 51 of the device B to the local memory 43, when the device A receives the data from the DMA bus, the PG / PC 46 performs a parity check. At this time, if a parity error occurs, an interrupt request is issued to the interrupt handler 41,
In response to the request, the interrupt handler 41 issues an interrupt to the microprocessor 40.

Therefore, due to a failure inside the BFM 51, B
When a parity error occurs during reading from the FM 51, an interrupt is generated from the device A via the interrupt generation circuit 50 and the interrupt handler 41, and a parity error is detected for the same data in the PG / PC 46 of the device A as well. Then, an interrupt is generated via the interrupt handler 41.

FIG. 6 shows a processing flow by the firmware of the microprocessor at this time. The processing of FIG.
First, when an interrupt occurs due to a parity error detection or the like in the BFM control circuit 52 of the device B, it starts.
The microprocessor analyzes the cause of this interrupt (Fig. 5).
S1), the cause of the interrupt is cleared (S2), and it is determined whether there is another interrupt (S3). That is, when there are a plurality of interrupts, the interrupt causes are cleared for all of them, and then it is judged whether or not there is one kind of interrupt (S4).
The suspicious range of the fault is specified from all the interrupt causes (S5), and the suspicious range is notified to the maintenance person (S6). In the case of only one type, the maintainer is also notified of the suspicious range corresponding to the interrupt. In the configuration of FIG. 5 described above, an interrupt based on a parity error generated by an internal failure of the BFM of the device B and an interrupt based on a parity error generated in the device A sequentially occur.

[0013]

According to the above-mentioned conventional method, the data transferred from the device B to the device A is BF
Two types of interrupts (an interrupt from the interrupt generating circuit 50 of the device B and an interrupt of a parity error of the device A) occur in the microprocessor 40 due to one error factor of the internal failure of M. However, there is a problem that the processing of the firmware after the occurrence of the interrupt becomes complicated as shown in FIG.

It is an object of the present invention to provide a parity error notification system which prevents two interrupts from occurring in the first device of the transfer destination due to the failure of the buffer memory of the second device of the data transfer source. To do.

[0015]

FIG. 1 is a block diagram showing the principle of the present invention. In FIG. 1, 1 is a first device including a microprocessor, 10 is a microprocessor, 11 is a memory, 12 is an interrupt handler, 13 is an interrupt inhibit circuit, and 14
Is a parity check circuit, 2 is a second device, 20 is an interrupt generation circuit, 21 is a buffer memory, and 22 is a buffer memory control circuit.

The present invention includes a first microprocessor including a microprocessor.
The parity error signal generated in the second device prevents the parity error signal generated in the first device from being input to the interrupt handler that generates an interrupt in the device.

[0017]

When the data received from another device (not shown) is stored in the buffer memory 21 of the second device 2 and the data is DMA-transferred to the memory 11 of the first device 1 under the control of the buffer memory control circuit 22, the buffer The memory control circuit 22 performs a parity check. Buffer memory 2
When the failure occurs in 1, the parity error is detected and the interrupt signal is input to the interrupt generation circuit 20. Then, an interrupt request is generated from the interrupt generation circuit 20, and the first device 1
Input to the interrupt handler 12 of. The interrupt handler issues an interrupt to the microprocessor 10 in response.

On the other hand, the transferred data is stored in the memory 11 of the first device and at the same time the parity check circuit 1
It is checked in step 4, and if a parity error occurs, it is input to the interrupt suppression circuit 13. This interrupt inhibit circuit 13 has a second
A parity error signal is supplied as a control input from the buffer memory control circuit 22 of the device.

Therefore, the buffer memory 21 of the second device
If a failure occurs in the buffer memory control circuit 2
A parity error signal is generated from 2 and the interrupt suppression circuit 13
Is suppressed, the interrupt request generated from the parity check circuit 14 is not supplied to the interrupt handler 12. For this reason, an interrupt that occurs due to the same factor of the failure of the buffer memory 21 does not occur twice for the microprocessor.

[0020]

FIG. 2 is a block diagram of the embodiment, FIG. 3 is an operation waveform of a main part of the embodiment, and FIG. 4 is a processing flow in a microprocessor of the embodiment.

In FIG. 2, reference numerals 40 to 4 in the apparatus A
Reference numerals 50 to 54 and D / R in 6 and the device B correspond to the devices or circuits having the same reference numerals shown in FIG. In FIG. 2, reference numeral 47 represents an interrupt inhibiting circuit provided by the present invention. A parity error detection signal (indicated by PERR) from the BFM control circuit 52 of the device B is supplied to the interrupt inhibiting circuit 47 as a control signal.
As a result, when the BFM control circuit 52 of the device B detects a parity error, the PG / PC (parity generation
Even if a parity error detection signal is generated from the parity check circuit) 46, the supply to the interrupt handler 41 is suppressed.

The operation will be described with reference to the operation waveforms in FIG. When an error occurs inside the buffer memory (BFM), when data is transferred from the buffer memory (BFM) 51 of the device B to the local memory 43 of the device A under the control of the DMAC 44, the data is read from the BFM 51 as shown in a of FIG. Data is generated and sent to device A via the DMA bus.

At this time, when the BFM control circuit 52 detects a parity error, a parity error detection signal (PERR) as shown in b of FIG. 3 is generated ("H" level), and the interrupt inhibiting circuit 47 is generated by its rising edge. The gate (including inside) is closed.

On the other hand, the data transferred to the device A via the DMA bus is subjected to a parity check by the PG / PC 46, and the result output indicates the detection of the parity error as shown in FIG. Then, the output of the interrupt suppression circuit 47 (normally "H") is shown in FIG. 3 because the gate of the interrupt suppression circuit 47 is closed as described above. As shown in FIG. 4d, it does not become “L”, and the interrupt by the PG / PC 46 does not occur.

Next, a transmission line (DMA) between the device A and the device B
If an error occurs in the transmission line only when the error occurs in the bus), the gate of the interrupt suppression circuit 47 remains open, and the result output of the parity check of the PG / PC 46 of the device A becomes “L”. Then, the output of the interrupt inhibiting circuit 47 also becomes "L" and an interrupt occurs.

The processing flow in the microprocessor of the embodiment is shown in FIG. 4, and when an error occurs in the BFM 51, the interrupt signal generated by the parity error detection of the BFM control circuit 52 of the device B is transmitted via the IRG 50. Reach the IRH 41 of the device A, and generate an interrupt from the IRH 41 to the microprocessor 40. With this, the interrupt cause analysis is performed (S1 in FIG. 4). Next, when the cause of the interrupt is cleared (at step S2), the maintenance personnel is notified of the suspicious range (at step S3), and the process is terminated. This content can be simplified as apparent from comparison with the processing flow of the conventional example (see FIG. 6).

[0027]

As described above, according to the present invention, it is possible to reduce the number of kinds of interrupts to the microprocessor of the transfer destination due to one factor of the failure of the buffer memory of the transfer source, so that the processing by the firmware can be simplified. it can. Further, when a parity error occurs in the transfer destination device (device A), the suspicious range can be easily identified. That is, it can be seen that the cause is different from the error in the buffer memory of the device B.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a configuration diagram of an embodiment.

FIG. 3 is an operation waveform of a main part of the embodiment.

FIG. 4 is a processing flow in the microprocessor of the embodiment.

FIG. 5 is a system configuration diagram of a conventional example.

FIG. 6 is a processing flow in a conventional microprocessor.

[Explanation of symbols]

 1 First Device 10 Microprocessor 11 Memory 12 Interrupt Handler 13 Interrupt Suppression Circuit 14 Parity Check Circuit 2 Second Device 20 Interrupt Generation Circuit 21 Buffer Memory 22 Buffer Memory Control Circuit

Claims (1)

Claim: What is claimed is: 1. A data processing system comprising: a first device having a microprocessor and a local memory; and a second device having a buffer memory. To an interrupt handler that includes a buffer memory control circuit that performs a parity check when transferring data to the first device and outputs a parity error signal to the first device, and that generates an interrupt to the microprocessor of the first device An interrupt inhibiting circuit for outputting an interrupt request and inputting a parity error signal of data sent from the second device is provided, and the interrupt inhibiting circuit generates an interrupt request when the parity error signal from the second device is generated. A parity error notification method characterized by suppressing the occurrence of