JPH05206178A - Semiconductor chip - Google Patents

Semiconductor chip

Info

Publication number
JPH05206178A
JPH05206178A JP3303675A JP30367591A JPH05206178A JP H05206178 A JPH05206178 A JP H05206178A JP 3303675 A JP3303675 A JP 3303675A JP 30367591 A JP30367591 A JP 30367591A JP H05206178 A JPH05206178 A JP H05206178A
Authority
JP
Japan
Prior art keywords
semiconductor chip
back surface
bubbles
mounting
brazing material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP3303675A
Other languages
Japanese (ja)
Inventor
Toshimichi Kurihara
俊道 栗原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3303675A priority Critical patent/JPH05206178A/en
Publication of JPH05206178A publication Critical patent/JPH05206178A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/30Die-attach connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117Shapes of semiconductor bodies

Landscapes

  • Die Bonding (AREA)

Abstract

(57)【要約】 【目的】半導体チップをマウントするとき、ろう材に発
生する気泡をなくす。 【構成】半導体チップ1の裏面3の周辺が薄くなるよう
にテーパー加工を施してから、裏面メタライズ4を形成
する。 【効果】半導体チップをマウントするとき、半導体チッ
プ裏面のメタライズ面や厚膜めっきとマウント面との間
のろう材に気泡が発生し難くなる。たとえ発生しても数
回スクラブすることにより、容易に気泡を除去すること
ができる。半導体チップの接着強度が確保でき、熱放散
が良くなって半導体チップの信頼度が向上する。
(57) [Summary] [Purpose] When mounting a semiconductor chip, eliminate bubbles generated in the brazing material. [Structure] The backside metallization 4 is formed after tapering is performed so that the periphery of the backside 3 of the semiconductor chip 1 becomes thin. [Effect] When mounting the semiconductor chip, bubbles are less likely to be generated in the brazing material between the metallized surface on the back surface of the semiconductor chip and the thick film plating and the mounting surface. Even if it occurs, the bubbles can be easily removed by scrubbing several times. The adhesive strength of the semiconductor chip can be secured, the heat dissipation is improved, and the reliability of the semiconductor chip is improved.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体チップに関し、特
に半導体チップの裏面加工に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip, and more particularly to backside processing of a semiconductor chip.

【0002】[0002]

【従来の技術】従来の半導体チップは図3(a)に示す
ように、半導体チップ1の裏面3に金などの裏面メタラ
イズ4が施されている。表面2と裏面3とは互に平行な
平面になっている。
2. Description of the Related Art In a conventional semiconductor chip, as shown in FIG. 3A, a back surface 3 of a semiconductor chip 1 is provided with a back surface metallization 4 such as gold. The front surface 2 and the back surface 3 are planes parallel to each other.

【0003】また図4に示すように、半導体チップ1の
裏面3に金などの裏面厚膜めっき4aが施されているも
のがある。この場合も表面2と裏面3とは互に平行な平
面になっている。
As shown in FIG. 4, there is a semiconductor chip 1 whose back surface 3 is plated with a back surface thick film plating 4a such as gold. Also in this case, the front surface 2 and the back surface 3 are planes parallel to each other.

【0004】[0004]

【発明が解決しようとする課題】従来の半導体チップ
は、一枚の平面ウェーハから切り出されるので、図3
(b)に示すように、マウントろう材5を用いてマウン
ト面6にマウントするとき、半導体チップ1の下に気泡
7が発生する。この気泡7の有無を検査することや、気
泡7を除去することは容易ではない。
Since the conventional semiconductor chip is cut out from one flat wafer, the semiconductor chip shown in FIG.
As shown in (b), when the mounting surface 6 is mounted using the mounting brazing material 5, bubbles 7 are generated under the semiconductor chip 1. It is not easy to inspect for the presence of the bubbles 7 or remove the bubbles 7.

【0005】図4に示すように、裏面厚膜めっき4aを
形成した場合は裏面3の周辺部に電界集中によるめっき
の過剰成長が避けられない。そのため裏面めっき4aが
半導体チップ裏面3の周辺部で盛り上がるので気泡がさ
らに生じ易くなっている。
As shown in FIG. 4, when the back surface thick film plating 4a is formed, overgrowth of plating due to electric field concentration is inevitable in the peripheral portion of the back surface 3. Therefore, the back surface plating 4a rises in the peripheral portion of the back surface 3 of the semiconductor chip, so that bubbles are more likely to be generated.

【0006】気泡の発生により半導体チップの接着強度
が下がる。また半導体チップ表面で発生する熱がマウン
ト面に逃げ難くなり、過熱して半導体チップの信頼度が
下がるという問題があった。
The generation of bubbles reduces the adhesive strength of the semiconductor chip. In addition, there is a problem that the heat generated on the surface of the semiconductor chip does not easily escape to the mount surface and overheats to lower the reliability of the semiconductor chip.

【0007】[0007]

【課題を解決するための手段】本発明の半導体チップ
は、裏面の周辺部が薄くなるようにテーパー加工され、
メタライズや厚膜めっきが施されているので、ろう材を
用いてマウントするときに周辺部がマウント面に対して
所定の角度で接触するように設計されている。
The semiconductor chip of the present invention is tapered so that the peripheral portion of the back surface is thin,
Since the metallization and the thick film plating are applied, it is designed so that the peripheral portion comes into contact with the mounting surface at a predetermined angle when mounting using a brazing material.

【0008】[0008]

【実施例】本発明の第1の実施例について説明する。EXAMPLE A first example of the present invention will be described.

【0009】図1(a)に示すように、半導体チップ1
の裏面3の周辺部が薄くなるようにテーパー加工されて
いる。そのうえに裏面メタライズ4が形成されている。
As shown in FIG. 1A, the semiconductor chip 1
The back surface 3 is tapered so that the peripheral portion thereof is thin. A back surface metallization 4 is formed on top of this.

【0010】この半導体チップ1が、図1(b)に示す
ように、ろう材5によってマウント面6にろう付けされ
る。このとき半導体チップ1の裏面3が傾斜しているの
で、気泡が発生し難いうえ逃げ易くなる。
The semiconductor chip 1 is brazed to the mount surface 6 with a brazing material 5 as shown in FIG. 1 (b). At this time, since the back surface 3 of the semiconductor chip 1 is inclined, bubbles are less likely to be generated and the bubbles easily escape.

【0011】そのため通常のマウント工程で半導体チッ
プ1をマウント面6に押えつけながら、水平方向に数回
動かす(スクラブする)ことにより、容易に気泡を除去
することができる。
Therefore, air bubbles can be easily removed by moving (scrubbing) the semiconductor chip 1 in the horizontal direction several times while pressing the semiconductor chip 1 against the mounting surface 6 in a normal mounting process.

【0012】本実施例のテーパー加工はフォトレジスト
をマスクとしてエッチングすることにより形成すること
ができる。
The taper processing of this embodiment can be formed by etching using a photoresist as a mask.

【0013】例えば0.4mm角の半導体チップにおい
て、ろう材の厚さ70μmの場合、テーパーの角度は約
10°が適切であると考えられる。
For example, in a 0.4 mm square semiconductor chip, when the brazing material has a thickness of 70 μm, it is considered appropriate that the taper angle is about 10 °.

【0014】つぎに本発明の第2の実施例について説明
する。
Next, a second embodiment of the present invention will be described.

【0015】本実施例においては図2(a)に示すよう
に、半導体チップ1の裏面3は平面ではなく、所定の曲
率をもった曲面で構成されている。その上には裏面厚膜
めっき4aが形成されている。
In this embodiment, as shown in FIG. 2A, the back surface 3 of the semiconductor chip 1 is not a flat surface but a curved surface having a predetermined curvature. Backside thick film plating 4a is formed on it.

【0016】そのため過剰成長による厚膜めっき4aに
おいて周辺部の盛り上りは発生しないので、裏面3に沿
った曲面になっている。
Therefore, in the thick film plating 4a due to overgrowth, no swelling occurs in the peripheral portion, so that the curved surface is along the back surface 3.

【0017】この半導体チップ1をマウントした状態を
図2(b)に示す。裏面厚膜めっき4aとろう材5とが
所定の角度で接するので、ろう材の気泡を防止すること
ができる。
FIG. 2B shows a state in which the semiconductor chip 1 is mounted. Since the back surface thick film plating 4a and the brazing material 5 are in contact with each other at a predetermined angle, it is possible to prevent bubbles of the brazing material.

【0018】[0018]

【発明の効果】半導体チップ裏面の周辺部が薄くなるよ
うにテーパー加工されている。そのため半導体チップを
マウントするとき半導体チップ裏面のメタライズ面や厚
膜めっきとマウント面との間のろう材に気泡が発生し難
くなる。たとえ発生しても数回スクラブすることによ
り、容易に気泡を除去することができる。
According to the present invention, the periphery of the back surface of the semiconductor chip is tapered so as to be thin. Therefore, when the semiconductor chip is mounted, bubbles are less likely to be generated in the metallized surface on the back surface of the semiconductor chip or in the brazing material between the thick film plating and the mounting surface. Even if it occurs, the bubbles can be easily removed by scrubbing several times.

【0019】半導体チップの接着強度が確保でき、熱放
散が良くなって半導体チップの信頼度が向上する。
The adhesive strength of the semiconductor chip can be secured, the heat dissipation is improved, and the reliability of the semiconductor chip is improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例を示す断面図である。FIG. 1 is a sectional view showing a first embodiment of the present invention.

【図2】本発明の第2の実施例を示す断面図である。FIG. 2 is a sectional view showing a second embodiment of the present invention.

【図3】(a)は従来の半導体チップを示す断面図であ
る。(b)は(a)をマウントした状態を示す断面図で
ある。
FIG. 3A is a sectional view showing a conventional semiconductor chip. (B) is sectional drawing which shows the state which mounted (a).

【図4】従来の半導体チップを示す断面図である。FIG. 4 is a cross-sectional view showing a conventional semiconductor chip.

【符号の説明】[Explanation of symbols]

1 半導体チップ 2 表面 3 裏面 4 裏面メタライズ 4a 裏面厚膜めっき 5 ろう材 6 マウント面 7 気泡 1 semiconductor chip 2 front surface 3 back surface 4 back surface metallization 4a back surface thick film plating 5 brazing material 6 mounting surface 7 air bubbles

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 裏面の周辺部が薄くなるように、テーパ
ー加工された半導体チップ。
1. A semiconductor chip that is tapered so that the peripheral portion of the back surface is thin.
JP3303675A 1991-11-20 1991-11-20 Semiconductor chip Withdrawn JPH05206178A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3303675A JPH05206178A (en) 1991-11-20 1991-11-20 Semiconductor chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3303675A JPH05206178A (en) 1991-11-20 1991-11-20 Semiconductor chip

Publications (1)

Publication Number Publication Date
JPH05206178A true JPH05206178A (en) 1993-08-13

Family

ID=17923882

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3303675A Withdrawn JPH05206178A (en) 1991-11-20 1991-11-20 Semiconductor chip

Country Status (1)

Country Link
JP (1) JPH05206178A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009054893A (en) * 2007-08-28 2009-03-12 Panasonic Electric Works Co Ltd Light emitting device
JP2012243922A (en) * 2011-05-19 2012-12-10 Mitsubishi Electric Corp Light-emitting device and method for manufacturing light-emitting device
JP2015050366A (en) * 2013-09-03 2015-03-16 ウシオ電機株式会社 Semiconductor laser device
JP2019149469A (en) * 2018-02-27 2019-09-05 トヨタ自動車株式会社 Semiconductor module
JP2019153749A (en) * 2018-03-06 2019-09-12 トヨタ自動車株式会社 Semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009054893A (en) * 2007-08-28 2009-03-12 Panasonic Electric Works Co Ltd Light emitting device
JP2012243922A (en) * 2011-05-19 2012-12-10 Mitsubishi Electric Corp Light-emitting device and method for manufacturing light-emitting device
JP2015050366A (en) * 2013-09-03 2015-03-16 ウシオ電機株式会社 Semiconductor laser device
JP2019149469A (en) * 2018-02-27 2019-09-05 トヨタ自動車株式会社 Semiconductor module
JP2019153749A (en) * 2018-03-06 2019-09-12 トヨタ自動車株式会社 Semiconductor device

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Effective date: 19990204