JPH05206807A - Multiple signal waveform generator - Google Patents

Abstract

(57) [Summary] [Purpose] To provide a multi-signal waveform generation device capable of simplifying software processing and significantly shortening software processing time. [Constitution] In the device of the present invention, it is necessary to set the minimum value sum data of a plurality of addition data in the register 2. Sum data is stored in the registers 201 and 202, and carry data is stored in the registers 203 and 204. The registers 201 and 203 and 202 and 204 respectively form register pairs A and B, and the carry flag can be set and reset by one instruction of the CPU 4, so that the software processing can be simplified and the software processing time can be greatly shortened. it can.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device which uses a CPU to generate a plurality of signal waveforms such as PWM waveforms.

[0002]

Related Art The inventor of the present invention has proposed a signal waveform generation device that includes one counter, one digital comparator, and one comparison register, and uses a CPU to simultaneously generate a plurality of PWM waveforms. Part of this proposal is Japanese Patent Application No. 3
It has been filed as No. 129123. Since these are not known technologies, they will be described as "related technology examples". (Related Technology Example 1) Since the basic of generation of a plurality of signal waveforms is the generation of one signal waveform, the generation of one signal waveform will be described first in Related Technology Example 1.

FIG. 4 is a block diagram of a "signal waveform generating apparatus" which is a first related art example. In the figure, 1 is a self-propelled n
A binary counter (hereafter called a counter) composed of bits (generally an integral multiple of nibbles), 2 is a counter 1
It is a register (or accumulator) configured with the same bit length (register length) as. A digital comparator 5 compares the values of the corresponding LSBs of the counter 1 and the register 2 for each bit of the MSB and outputs a coincidence output "1" when the values of all the bits are coincident. The coincidence output is output to the signal line 10 and is supplied to the T input terminal of a T flip-flop (hereinafter referred to as TFF) 6. At the same time, it is supplied to the interrupt input terminal of the CPU 4. Reference numeral 3 denotes a ROM 1, which has a structure in which the CPU 4 can access the data and the execution program. CPU4
The output signal of the register 2 can be input through the signal line 9, and the operation output terminal is connected to the signal input terminal of the register 2 through the signal line 12. The system clock is also supplied to the clock signal input terminals of the counter 1 and the CPU 4 through the signal line 7, and also to the digital comparator 5 for synchronization. Further, the control signal input terminal of the counter 1 is connected to the control signal output terminal of the CPU 4 through the signal line 13.

Next, the operation will be described with reference to the flowchart of FIG. When the CPU 4 is in the system operable state (see S1), PWM control information, for example, data in the L level period of the signal waveform to be generated is read from the ROM 1 and 3 (S2) and set in the register 2 (S).
3). Then, the CPU 4 sends a count start signal to the counter 1 through the signal line 13 (S4). Counter 1
Is a binary up counter, the digital comparator 5 counts up in synchronization with the system clock input through the signal line 7, and when the value of each bit matches all corresponding bit values of the register 2. The coincidence is detected (S6, YES), and the signal "1" is output on the signal line 10. In this case, the CPU 4 sends a clear signal to the TFF 6 through the signal line 14 and resets it in advance. As a result, the logical state of the output signal of the TFF 6 (hereinafter referred to as state) is inverted (S7), and the output terminal 1
The signal state of 1 changes from "L" to "H". At the same time, the signal "1" on the signal line 10 becomes an interrupt signal and is applied to the interrupt signal input terminal of the CPU 4. CPU
4 detects the interrupt signal (S8), and ROM1 / 3
Then, the data in the "H" level period of the newly generated signal is taken out (S9), and the sum of it and the data in the "L" level period on the register 2 read by the signal line 9 are taken,
The result is reset in the register 2 (S10). At that time, the Japanese carry data is cut off. Then, the value of each bit of the counter 1 and the register 2 is compared (S11, S1
2) When all the values of the respective bits match, the output signal of the TFF 6 is inverted (S13), the CPU 4 is interrupted (S14), and the data of the next "L" level period is read from the ROM 1.3 (S15). ), And the sum of it and the data in the "H" level period on the register 2 is taken and reset to the register 2 (S16). And the above S5-S1
By repeating the operation of 6, it is possible to obtain one desired signal waveform at the output terminal 11. The bit length of the counter 1 is such that a clock having a cycle longer than one cycle of the generated signal waveform can be generated.

(Related Art Example 2) FIG. 6 is a block diagram of a "multi-signal waveform generating apparatus" which is an example 2 of related art. In this example, RAM 100, selector 101, TFF 102, 10
3 is different from the related art example 1 in that two signal waveforms are provided.

Description of the same parts of the circuit operation will be omitted, and different parts will be described. The output line 10 of the digital comparator 5 is connected not only to the input terminal of the CPU 4 but also to the signal input terminal of the selector 101. Selector 1
The signal select terminal 01 is connected to the CPU through the signal line 104.
4 select signal output terminal. One of the output terminals of the selector 101 is connected to the T input terminal of the TFF 102 and the other is connected to the T input terminal of the TFF 103. The outputs of the TFFs 102 and 103 are output terminals 1 respectively.
It is supplied to 05 and 106. In addition, the TFF 102,
The reset terminal of 103 is connected to the CPU 4 via the signal line 14. The RAM 100 is connected to the CPU 4 via a bus and has a structure in which the CPU 4 can read and write at arbitrary timing. Since the other circuits are the same as those in FIG. 4, the description thereof will be omitted.

Next, the operation will be described with reference to FIG. After the system is reset (S21), the CPU 4 fetches the initial data of each signal waveform from the ROM 1.3,
Set to AM100. The CPU 4 takes out the minimum value (S22, S23) (now consider it as the output waveform data of the TFF 102) and sets it in the register 2 (S).
24). At that timing, the CPU 4 replaces the selector 101 with the signal line 104 and switches the signal line 10 to the TFF 10.
It operates so as to connect to the T input terminal 2 (S25). Then, the counting of the counter 1 is started (S26), the values of the respective bits of the counter 1 and the register 2 are compared (S27),
When the values of all bits match and the match signal is output from the counter 1 to the signal line 10 (S28, YES), TFF1
The signal state of 02 is inverted (S29), and at the same time, the signal is input to the CPU 4 as an interrupt signal. CP interrupt
When U4 detects (S30), CPU4 fetches the data of register 2 through signal line 9,
The next data on the FF 102 side is added and set in the RAM 100 (S31, S32). And CPU4 is RAM1
The minimum value data in 00 is selected (S33, S34), set in the register 2 (S24), and the above-described operations of S24- are continued again. In that case, the selector 101 is always switched so as to select the TFF corresponding to the minimum value data set in the register 2. Note that the counting of the counter of the counter 1 in (S26) is a process that is valid only in the first cycle after the operation starts.

The signal waveform that can be created has a cycle that can be generated by the counter 1 that is always prepared. Further, the plurality of waveforms are limited to those having a signal waveform having a relationship that the outputs are not inverted at the same time.

Incidentally, in order to cope with the case where a plurality of signal waveforms are simultaneously output inversion, the following configuration may be adopted. The basic operation is as described above, but this is the case where a plurality of data values in the RAM 100 have the same value. In that case, the selector 101 outputs all signals to the T signal input terminals of the TFF corresponding to the plurality of data. It suffices to have a function such that the signal of the line 10 is supplied. The instruction is executed by the CPU 4 through the signal line 104. If a carry occurs in S32, it is necessary to always take the carry information (carry data) into consideration to obtain the minimum value. Specifically, the carry value may be held in the RAM 100 and the minimum value may be calculated including it. (When setting to the register 2, the carry information is only the chisell sum data.) In this way, two arbitrary signals can be easily used while using one set of counter, register and digital comparator. Waveforms can be generated. By the same method, it is possible to generate n arbitrary signal waveforms.

(Related Art Example 3) A block diagram of Related Art Example 3 is shown in FIG. In this example, the basic circuit and the operation are similar to those of the related art example 2, and therefore the description will be omitted and only different parts will be described.

In FIG. 8, the output terminal 10 of the device is shown.
5, 106 are connected to the control signal input terminal of the CPU 4 or the access signal input terminal of the ROM 2.16 through the signal lines 107, 108. In addition, ROM2 ・ 16,
When an access signal is received from the CPU 4 on the signal lines 107 and 108, it is newly added as an accessible ROM so that the CPU 4 can take out ROM information corresponding to each access signal.

Next, the operation will be described. In this example, when the signal lines 107 and 108 are “H”, the CPU is hardware-based.
4 can access only the data of ROM1 and 3,
When it is "L", it operates so that only the data in the ROM2, 16 can be accessed. Therefore, when the CPU 4 detects the coincidence output, RO is surely output when the output terminal is "H" even if the CPU 4 does not store the past control information of the CPU 4.
When the output-only "L" level information of each of M1 and 3 is accessed, and when the output terminal is "L", ROM2.1
6 to access the output-only "H" level information.

Incidentally, only the initialization is done by a hardware C
It is assumed that the PU 4 has a structure in which the “L” level information of the ROM 1 and 3 can be accessed even when the output terminal is “L”. The CPU 4 also outputs the output terminals 105 and 106.
It is also possible to internally count the number of changes in the level and change the ROM data according to the counting condition.

According to this example, the program can be easily created, and the adverse effects such as malfunction of the TFF can be minimized.

(Related Art Example 4) FIG. 9 is a block diagram of Related Art Example 4, and FIG. 10 is a flowchart showing its operation. Since this example is configured such that the comparator 17, the signal sources 19-1 and 19-2, and the reference power supply 20 are added to the related art example 3, only parts different from those of the related art example 3 will be described. However, the description of common parts will be omitted. The output terminal of the comparator 17 is the signal line 18
Is connected to the control signal input terminal of the CPU 4 through.
Further, the + signal input terminal is connected to the output terminal of the reference power supply Vref-20 whose one end is grounded, and the-signal input terminal is connected to the signal output terminal of the signal source Vin-19-1 / 19-2. Has been done. In particular, 17 is a chopper type comparator, and the CPU 4 is a signal source 19-1 / 19-
2. The reference power source 20 can be switched in a time division manner.

Next, the operation will be described. The operation is TF
Since the process up to reading the output data (referred to as α) of F102 and 103 is the same as that of the related art example 3, the description thereof will be omitted, and the procedure thereafter will be described. After reading the α data, the CPU 4 reads the comparison result (hereinafter referred to as β) between the voltage Vin of the signal source 19-1 and the voltage Vref of the reference power source 20 through the signal line 18 (S51). When the signal (M1) output to the output terminal 105 is used as a PWM signal for controlling the switching power supply, the CPU 4 operates 19-1.
Is switched to the power supply to be controlled, and 20 is controlled to the control reference voltage. If the “H” level time of the signal waveform output to the output terminal 105 becomes long, the signal source 1
Assuming that the voltage of 9-1 increases, if the voltage Vin of the signal source 19-1 becomes higher than the voltage Vref of the comparison reference power source 20, "H" of the signal waveform output to the output terminal 105.
Since the level time is shortened and the signal waveform in the direction of decreasing the voltage Vin of the signal source 19-1 is output to the output terminal 105, it is possible to perform control by negative feedback.

The CPU 4 reads the signal β on the signal line 18 after reading the data α of the output terminal 105, and when α is "L" (S53, YES), when β is "L" (S54, YES). ), The on-width data in the ROM 2 selected by α is read from the ROM 2, and the data obtained by adding 1 to the data and the data in the register 2 is written to the RAM 100 (S55). When α is “L” and β is “H” (S54, NO), the CPU 4 reads the ON width data in the ROM 2 selected by α and adds the data and the data of the register 2 from the data. The data obtained by subtracting 1 is written in the RAM 100 (S5
9). The minimum value in the RAM 100 is determined (S56), and only the sum data excluding the carry data having the minimum value is set in the register 2. The routine again enters the coincidence determination routine for the value of the counter 1 and the value of the register 2. When α is “H”,
The CPU 4 reads the ROM data of the ROM 1 selected by α, and the sum of the data and the data of the register 2 is written to the RAM 100 (S58).
Determine the minimum value of

The CPU 4 can also control the TFF 103 in the same manner by changing the signal source 19-1 to the signal source 19-2 and changing the value of the voltage Vref of the reference power source 20. Further, the same method can be applied to the extension of three or more signal waveforms. The counter start in S45 is a process that is effective only in the first cycle immediately after the start of operation.

Since it operates as described above, a. By using the device, it is possible to easily include a plurality of PWM control circuits having a constant off width. (Multiple PWM with constant frequency
It goes without saying that the control circuit can be easily made by the same method. ) B. Since the soft judgment is used for the control, there is a merit that when a problem occurs in the control, the control method can be easily changed to deal with the problem.

Specifically, in order to reduce the loop stability and the ripple content, when α is “L”, the amount of increase / decrease from the sum of the data in ROM 2 and the data in register 2 is set to a value other than 1. It is easy to change.

(Related Art Example 5) FIG. 11 is a block diagram of Related Art Example 5, and FIG. 12 is a flow chart showing its operation. In this example, the counter 2 is different from the related technology example 4.
1 is added. Since the basic is related art example 3, description of common parts will be omitted and different parts will be described. In the present case, the counter 21 has the TFF 102.
The case of counting the output of the
4 can be easily switched by using the signal line 22 to count the output of the TFF 103. The counter 21 is configured to input the output signal of the output terminal 105 to its clock input terminal through the signal line 107.

The counting status (hereinafter referred to as γ)
The CPU 4 is configured so that it can be read through the signal line 23. At the same time, the signal line 108 is also the counter 2
It is connected to the signal input terminal 1 and can be read by a command from the CPU 4. At the same time, the CPU 4 can set the counter 21 to an arbitrary initial state through the signal line 22.

Next, the operation will be described. At the time of initialization, the CPU 4 writes necessary control information to the counter 21 through the signal line 22, for example, whether the counter 21 is an up counter or a down counter. The counter 21 operates to count up or down each time the data output to the output terminal 105 falls. CPU4
Based on the control information, ROM1 / 3 or ROM2
The amount of value to be added or subtracted to the sum of the data of 16 and the data of register 2 can be freely set.

[0024]

As described above, in the related art example, all arithmetic operations of data for generating the PWM waveform are performed by the CPU's ALU (Arithmetic and Logic Un).
There is the following problem because the processing is performed by software using the arithmetic function that is basically included in it). a. When a carry occurs in the addition operation, it is necessary to save the information for size comparison.

B. The size calculation when a carry occurs becomes very complicated, and the number of software steps increases.

C. When an interrupt occurs during calculation from the above b or the like and a calculation result at the next timing is requested,
In some cases, the calculation result cannot be prepared depending on the generated waveform.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a multi-signal waveform generating apparatus capable of simplifying the soft processing and greatly shortening the soft processing time. ..

[0028]

According to the present invention, in order to achieve the above-mentioned object, a signal waveform generator is provided with the following (1) and (2).
Configure as follows.

(1) A multi-signal waveform generator having the following components a to h. a. A counter that counts predetermined clock pulses. b. A register for setting data relating to one output signal of a plurality of output signals of the device. c. A comparator that compares the counter and the register and outputs a coincidence output. d. An adder that adds new required data of the output signal related to the data set in the register among the plurality of output signals of the device and the data set in the register every time the comparator outputs a coincidence output. e. A plurality of storage means for individually storing a pair of sum data and carry data which is the output of the adder. f. Judging means for judging the minimum value from a plurality of pairs of sum data and carry data stored in the plurality of storage means. g. Setting means for setting, in the register, sum data concerning the minimum value determined by the determining means each time the comparator outputs a coincidence output. h. Output inverting means for inverting the state of the output signal relating to the data set in the register among the plurality of output signals of the device each time the comparator outputs a coincidence output.

(2) The multiple signal waveform generator according to (1), further comprising a reset circuit for detecting that all of the carry data are stored in the plurality of storage means and erasing all of the carry data.

[0031]

With the configurations (1) and (2), the addition data is stored as a pair of sum data and carry data.
The minimum value can be easily determined by software. In the configuration of (2), further, when the carry data is stored in all of the plurality of storage means, the carry data is erased by the reset circuit, so that the process by software becomes simple.

[0032]

EXAMPLES The present invention will be described in detail below with reference to examples. (Embodiment 1) FIG. 1 is a block diagram of a "plurality of signal waveform generators" according to Embodiment 1. In FIG. In the present embodiment, for simplification of description, an example of generating two signal waveforms is described, but generation of three or more signal waveforms can be easily implemented by expanding the present embodiment.

The basic structure and operation of this embodiment are as follows.
Since it is the same as the related art example described above, the description thereof is omitted, and here, the description will be focused on the periphery of the register used in the calculation and the processing relating to the magnitude comparison.

As shown in FIG. 1, in the configuration of the related art example,
Further, dedicated registers A and B for storing addition data are added. The register A is composed of registers 201 and 203, and the register B is composed of registers 202 and 204. The registers 201 and 202 are registers that store sum data obtained by removing carry data from addition data, and the registers 203 and 204 are registers that store carry data of addition data. Registers A and B are hereinafter referred to as "register pairs".
A bus line 205 connects the I / O port of the CPU 4 and the I / O terminals of the registers 201 to 204. C
The PU 4 has a structure for transferring the sum data and the carry data of the addition result through the bus line 205.

Reference numerals 206 and 207 are signal lines for selecting and controlling the register pairs A and B, respectively. Reference numeral 208 denotes a data reading bus for the registers 201 and 202. A carry flag data bus 209 is a data bus for reading carry data on different registers 203 and 204 with one instruction.

Next, the operation will be described. CPU4 A
The LU unit 215 has a transfer instruction for a dedicated register, and has a CP
When U4 executes the instruction, the gate that is not opened by a normal transfer instruction is opened, so that not only the information of the accumulator 2 but also the output of the carry flag register that stores the carry information generated as the operation result is transferred to the bus 205 at the same time. To be done. When the data is the information of the register pair A, the data on the bus 205 is transferred to the registers 201 and 203 by the control signal on the signal line 206, and when the data is the information of the register pair B, ,
The data on the bus 205 is transferred to the register 202 and the register 204 by the control signal on the signal line 207. Next, a case where the CPU 4 reads out those data will be described. At the time of reading, the registers 201 and 20
The information of 2 is read by the CPU 4 from the bus line 208, and the information of the registers 203 and 204 is the bus line 209.
Therefore, it can be read by a carry information read command. Further, the ALU unit 215 has a carry flag control-dedicated command, and the CPU 4 uses this command to control the bus line 20.
5. The carry flag can be arbitrarily set by one instruction through the signal lines 206 and 207.

The actual operation is as follows. CPU4
Replaces what was used as the temporary storage area of the RAM 100 in the related art example with the registers 201 to 204, and H data,
The sum operation of L data is executed, and each time an interrupt signal is output to the signal line 10, the size of the value of the register pair A and B including the carry data is judged, and the small sum data is registered in the register 2 To generate a PWM waveform.

In the technique of the related art example, since the carry register is attached to the arithmetic unit and normally one, the carry information generated during the sum operation is taken out from the carry register each time, and copied to the memory such as RAM. I had to save and put it.

On the other hand, in this embodiment, the register (A
CC) 2 and the carry flag information generated as a result of the operation on the register 2 are simultaneously stored in one of the pair of register pairs 201 and 203 or 202 and 204 at a time. Instructions are prepared and can be saved with one instruction.

Further, when comparing the sizes, the CPU 4 can judge the state of the flag through the signal bus 209 with one instruction of the carry flag reference instruction.

With such an instruction and hardware configuration,
Extracting the minimum value data is much easier than the related art example.

The specific operation of this size comparison will be described below. The CPU 4 determines the carry flag, and when the flagged and non-flagged flags are mixed, only the values of register pairs that are not flagged are compared with each other. It becomes the setting data of the register 2 of. All flags are "0"
Alternatively, when the value is "1", the data of all the register pairs are compared with each other, and the minimum sum data becomes the data for the setting of the next register 2. Both the related technology example and this embodiment can be executed by the control procedure shown in FIG. 2, but the specific method is different.

That is, in the step S102, in the present embodiment, the information can be read by one instruction of the carry information read instruction, and can be determined by the data compare instruction. In this operation, there is no concern that the number of instructions will increase even if the number of PWM waveforms generated increases. On the other hand, in the related art example, the number of output signal waveforms × (save + fetch) times of CPU operation is required. Similarly, in this embodiment, the same instruction as in S101 can be executed in S102. As a result of S102, when the process proceeds to S106, the CPU 4 can reset all carry flags with one instruction of the carry flag control dedicated instruction.

S103, S104, and S105 are processed by the same procedure as the related art example. As described above, according to the present embodiment, since the carry flag processing can be easily executed by the command as compared with the related art example, the program can be easily created, the number of steps can be shortened, and the execution time can be shortened. There is an advantage. As a result, higher frequency PW
There is a merit that an M waveform can be generated.

(Embodiment 2) This embodiment is an example in which the carry flag reset of S106 of FIG. 2 is realized by a hardware circuit in contrast to the embodiment 1, and the reset circuit is shown in FIG. The other parts are similar to those of the first embodiment, and therefore omitted.
Explain the different hard parts. 301 in Example 1
Since the logic circuits No. to 305 are added, the connection of this circuit will be described first.

In FIG. 3, 301 is a two-input NOR gate, one input terminal of which is connected to the signal line 206 and the other input terminal of which is connected to the signal line 207, the output terminals of which are 303,
RS composed of 3-input and 2-input NOR gate 304
It is connected to a reset input terminal of a flip-flop (hereinafter referred to as FF). The-terminal of the SET signal input terminal of the FF is connected to the output terminal of the 2-input AND gate 302. The other-terminal is connected to 14 signal lines. One of the input terminals of the 2-input AND gate 302 is
It is connected to the Q output terminal of the register (D type flip-flop) 203, and the other end is connected to the Q output terminal of the register (D type flip-flop) 204. The output terminal of the 3-input NOR gate 303 is connected to the input terminal of the inverter 305, and the output terminal of the inverter 305 is connected to the reset terminals of the registers 203 and 204.

Next, the operation will be described. Signal line 1
4, a reset signal is sent in advance, 203, 20
Consider the condition that 4 is reset beforehand.

Normally, the flag information on the signal lines 205-1 and 205-2 are set in the registers 203 and 204, respectively, in synchronization with the set signals on the signal lines 206 and 207, respectively. When the outputs of the registers 203 and 204 are both set in the FF, the output of the AND gate 302 is set to "1", and the information is set to the inverter 305.
Through the reset terminals of the registers 203 and 204, and the flag outputs thereof are reset together. Also FF
Is reset by the output signal of the NOR gate 301 when the data set signals of the registers 203 and 204 are set to the “L” level after the flag setting is completed,
The state of 3,204 flags can be reset. In addition,
The flags of the registers 203 and 204 are reset only when the flags of the registers 203 and 204 are both set or when the reset signal is sent out on the 14 signal line.

As described above, according to the present embodiment, when all the carry flags are set, it is not necessary to determine the state of the flag and reset the flag by software, and a higher frequency arbitrary pulse can be generated by software. Become.

[0050]

As described above, according to the present invention,
Since a plurality of storage means (register pairs) for individually storing the added data in pairs of sum data and carry data are used, software processing for setting and resetting the carry flag can be simplified, and the invention of claim 2 Then, the carry flag state determination and its resetting are performed by hardware, so that the software processing is simplified.

Therefore, the soft processing time can be greatly shortened and a higher frequency signal waveform can be generated.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment.

FIG. 2 is a flowchart for determining a minimum value.

FIG. 3 is a block diagram of a second embodiment.

FIG. 4 is a block diagram of Related Art Example 1

FIG. 5 is a flowchart of related technology example 1.

FIG. 6 is a block diagram of Related Art Example 2

FIG. 7 is a flowchart of Related Technology Example 2

FIG. 8 is a block diagram of Related Art Example 3

FIG. 9 is a block diagram of a related technology example 4.

FIG. 10 is a flowchart of Related Technology Example 4.

FIG. 11 is a block diagram of a related technology example 5.

FIG. 12 is a flowchart of Related Art Example 5.

[Explanation of symbols]

 1 Counter 2 Register (ACC) 4 CPU 5 Digital Comparator 101 Selector 102, 103 TFF (201, 203), (202, 204) Register 215 ALU Unit

Claims (2)

[Claims] 1. A multi-signal waveform generation apparatus comprising the following components a to h. a. A counter that counts predetermined clock pulses. b. A register for setting data relating to one output signal of a plurality of output signals of the device. c. A comparator that compares the counter and the register and outputs a coincidence output. d. An adder that adds new required data of the output signal related to the data set in the register among the plurality of output signals of the device and the data set in the register every time the comparator outputs a coincidence output. e. A plurality of storage means for individually storing a pair of sum data and carry data which is the output of the adder. f. Judging means for judging the minimum value from a plurality of pairs of sum data and carry data stored in the plurality of storage means. g. Setting means for setting, in the register, sum data concerning the minimum value determined by the determining means each time the comparator outputs a coincidence output. h. Output inverting means for inverting the state of the output signal relating to the data set in the register among the plurality of output signals of the device each time the comparator outputs a coincidence output. 2. The multi-signal waveform generation apparatus according to claim 1, further comprising a reset circuit that detects that all of the carry data is stored in the plurality of storage means and erases all of the carry data.