JPH05206836A - BiCMIS circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] A BiCMIS circuit capable of obtaining a full-amplitude output voltage from the ground voltage to the power supply voltage as an output voltage while maintaining the low power consumption and high driving capability which are the characteristics of the BiCMIS circuit. I will provide a. [Structure] A partial circuit including a logic circuit composed of a CMIS circuit (inverter in FIG. 1), an NPN bipolar transistor 5 having an output terminal (node N) of the inverter connected to a base, and an NMOSFET 4 of the inverter. A circuit connected between the output terminal 2 and the contact terminal 8 (N
A BiCMIS circuit having a MOSFET 6) is provided with a circuit (PMOSFET 9) having the same configuration as a partial circuit including the PMOSFET 3 of the inverter, a power supply terminal 7 and an output terminal
BiCMIS circuit connected between.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a BiCMIS circuit, and more particularly to a BiCMIS circuit in which a bipolar transistor and a CMIS transistor are combined in a basic circuit.

[0002]

2. Description of the Related Art A BiCMIS circuit that combines a bipolar transistor and a CMIS transistor in a basic circuit is a C
The power consumption can be as low as that of a MIS circuit, and the high speed performance can be achieved as that of a bipolar circuit.

FIG. 5 is a circuit diagram of an example of a conventional BiCMIS circuit of this type. This BiCMIS circuit is based on IEICE TRANSACTI
ONS on Electronics), E74
Vol. 1, No. 1, January 1991, pp. 119-129, "Prospect for chip architecture in the sub-half micron ULSI era (" Prospect for ").
the ChipArchitecture in
Sub-Half-Micron ULSIra ")
Is described in a paper entitled. That is, as shown in FIG. 5, in the NPN bipolar transistor 5, the collector is connected to the power supply terminal 7, the emitter is connected to the output terminal 2, and the base is connected to the drain of the PMOSFET 3. PMO
The SFET 3 has a drain connected to the base of the NPN bipolar transistor 5 and the drain of the NMOSFET 4, a source connected to the power supply terminal 7, and a gate connected to the input terminal 1. The source of the NMOSFET 4 is the ground terminal 8
In addition, the gate is connected to the input terminal 1. NMOSF
In ET6, the drain is connected to the output terminal 2, the source is connected to the ground terminal 8, and the gate is connected to the input terminal 1. By this connection, CMO is achieved in PMOSFET 3 and NMOSFET 4.
An S inverter is formed, and the load is driven by the NPN bipolar transistor 5 and the NMOSFET 6.

The operation of this circuit will be described below. As shown in FIG. 2, when the level of the input voltage to the input terminal 1 is switched to the low level, the PMOSFET 3 is turned on and the node N is charged to the power supply voltage V _CC . Therefore, the NPN bipolar transistor 5 becomes conductive, and the level of the output voltage rises from the low level potential to near the power supply voltage V _{CC as} shown by the broken line in the figure. However in this case, the output voltage is completely does not rise up to the power supply voltage V _CC, N from the power supply voltage V _CC
The voltage rises only up to the voltage (V _CC -V _BE ) lowered by the built-in voltage V _BE between the base and emitter of the PN transistor 5. On the other hand, when the input level is switched to the high level, the NMOSFET 6 is turned on, and the output level drops to the ground potential as shown in FIG.

[0005]

However, BiC
When the dynamic circuit is driven by using the MIS circuit, as the output voltage, the high level voltage is the power supply voltage V _CC.
It is desirable to reach up to. That is, for example, in the case of a circuit that stores electric charge in a capacitor through an NMISFET as a dynamic circuit, it is necessary to apply as high a voltage as possible to the gate of the NMISFET to increase the write voltage when writing electric charge. Therefore, in the above-mentioned conventional BiCMIS circuit, the amplitude of the output voltage is in the range from 0 V to (V _CC -V _BE ), and therefore, there is a drawback that the write voltage is reduced by V _BE when the dynamic circuit is written. there were.

Further, as the MISFET is miniaturized, it becomes necessary to lower the power supply voltage V _{CC in} order to maintain the reliability of the device. A method of lowering the threshold voltage V _{th of the} MISFET is used in order to prevent a decrease in operation speed resulting from a decrease in the operation voltage that occurs as a result and to maintain high speed. For example, when V _CC = 3 (V), PMIS
The _{Vth of the} FET and the NMISFET are set to -0.5V and 0.5V, respectively. Since the built-in voltage V _BE is usually about 0.7V, the output voltage of the BiCMIS circuit shown in FIG. 5 is 2.3V at the high level and 0V at the low level. When this output signal is applied to the input terminal 1, since the high level of the input signal is 2.3V, the PMISFET 3 having _Vth of -0.5V does not become completely non-conductive and the source
A small amount of current flows between the drains, and PMISFET3 and N
There is also a drawback that the current consumption of the inverter composed of the MISFET 4 increases.

An object of the present invention is to provide a BiCMIS circuit capable of obtaining a full-amplitude output voltage from the ground voltage to the power supply voltage V _CC as its output voltage while maintaining the feature of low power consumption and high driving capability. To provide.

[0008]

A BiCMIS circuit of the present invention comprises a logic circuit composed of a CMIS circuit, an NPN having a base connected to an output terminal of the logic circuit, a collector connected to a power supply terminal, and an emitter connected to an output terminal. Bipolar CM in which a partial circuit composed of a bipolar transistor and NMISFET of the logic circuit is connected between an output terminal and a ground terminal.
In the IS circuit, a partial circuit including the PMISFET of the logic circuit is connected between the power supply terminal and the output terminal.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an optimum embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of the first embodiment of the present invention. Referring to FIG. 1, this embodiment has a configuration in which a PMOSFET 9 is added to the conventional BiCMIS circuit shown in FIG. The PMOSFET 9 has a source connected to the power supply terminal 7, a gate connected to the input terminal 1, and a drain connected to the output terminal 2.

The operation of the BiCMIS circuit of this embodiment will be described below. FIG. 2 shows Bi according to the present embodiment and the related art.
It is a figure which shows the input / output voltage characteristic of a CMIS circuit. Referring to FIG. 2, when the level of the input voltage is switched from the high level to the low level in FIG. 1, the PMOSFET 3 is turned on and the voltage at the node N is charged to the power supply voltage V _CC . Therefore, the NPN bipolar transistor 5 becomes conductive,
The output voltage of the output terminal 2 rapidly rises to (V _CC −V _BE ). In the present invention, since the PMOSFET 9 is also in the conductive state, the output voltage will completely rise to the power supply potential V _CC as shown by the solid line in FIG. Next, when the input level is switched from low level to high level, N
The MOSFET 6 is turned on, and the output voltage of the output terminal 2 drops to the ground voltage.

In the BiCMIS circuit of this embodiment,
0 out of all oscillation operations from ground potential to power supply potential V _CC
The voltage swing operation from V to (V _CC -V _BE ) is mainly NP
The high speed operation is performed by the N bipolar transistor 5 and the NMOSFET 6. The subsequent amplitude operation from (V _CC -V _BE ) to the power supply potential V _CC is performed by the added PMOSFET 9
This full voltage amplitude is used for driving dynamic circuits and for circuits requiring low power consumption.

Next, a second embodiment of the present invention will be described. FIG. 3 is a circuit diagram of a BiCMIS circuit according to the second embodiment of the present invention. Referring to FIG. 3, the logic circuit is an inverter in the first embodiment, whereas the logic circuit is a two-input NAND circuit in this embodiment. The 2-input NAND circuit has PMOSFETs 3 connected in parallel.
1 and 32, and MNOSFETs 41 and 42 connected in series. In the embodiment, as the number of input terminals is two, that is, the first input terminal 11 and the second input terminal 12, two PMOSFETs are connected between the power supply terminal 7 and the output terminal 2. PMOSFET 91
And 92 in parallel. Furthermore, output terminal 2
2 connected to the ground terminal 8 and MNOSFET
It is a series circuit of two NMOSFETs 61 and 62. The circuit operation of this embodiment is almost the same as that of the first embodiment, and the operation waveform is similar to that shown in FIG. However, the input voltage is read as the voltage of the slower input signal of the first input signal and the second input signal.

Next, a third embodiment of the present invention will be described. FIG. 4 shows a BiCMIS according to a third embodiment of the present invention.
It is a circuit diagram of a circuit. Referring to FIG. 4, in this embodiment, the logic circuit is a 2-input NOR circuit. 2 input NO
The R circuit includes PMOSFETs 31 and 32 connected in series and NMOSFETs 41 and 42 connected in parallel.
It consists of Then, as the number of input terminals becomes two, that is, the first input terminal 11 and the second input terminal 12, PM connected between the power supply terminal 7 and the output terminal 2 is connected.
The OSFET is a series circuit of two PMOSFETs 91 and 92. Furthermore, the output terminal 2 and the ground terminal 8
NMOSFET connected between and is two NMOS
It is a parallel circuit of FETs 61 and 62. This embodiment operates almost in the same manner as the first embodiment, and the output voltage rises up to the power supply voltage V _CC like the output voltage waveform.

Although the MOSFETs have been described in the above first to third embodiments, the present invention is not limited to this. It is clear that the effect of the present invention can be obtained even in a MISFET using an insulator other than oxide for the gate.

[0015]

As described above, according to the present invention,
As the output circuit of the BiCMIS circuit, it is possible to obtain the full amplitude output voltage from the ground voltage to the power supply voltage V _CC . As a result, the present invention does not deteriorate the retention characteristic of the stored data when driving not only the static circuit but also the dynamic circuit, and increases the current consumption even when the absolute value of V _th of the CMISFET becomes small. There is an effect that a low power consumption BiCMIS circuit can be realized.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

2 is an operation waveform diagram of input / output voltages in the BiCMIS circuit shown in FIG. 1 and the conventional BiCMIS circuit shown in FIG.

FIG. 3 is a circuit diagram of a second embodiment of the present invention.

FIG. 4 is a circuit diagram of a third embodiment of the present invention.

FIG. 5 is a circuit diagram of a BiCMIS circuit according to a conventional technique.

[Explanation of symbols]

 1 Input Terminal 2 Output Terminal 3, 9, 31, 32, 91, 92 PMOSFET 4, 6, 41, 42, 61, 62 NMOSFET 5 NPN Bipolar Transistor 7 Power Supply Terminal 8 Ground Terminal

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical indication H01L 21/331 29/73 7377-4M H01L 29/72

Claims (1)

[Claims] 1. A logic circuit composed of a CMIS circuit; an NPN bipolar transistor having a base connected to an output terminal of the logic circuit, an emitter connected to an output terminal, and a collector connected to a power supply terminal; From the NMISFET of the logic circuit, which is connected between the power supply terminal and the output terminal and is the same as the partial circuit including the PMISFET of the logic circuit, and which is connected between the output terminal and the ground terminal. A BiCMIS circuit having the same partial circuit as the above.