JPH0520785A - Still picture reproducing device - Google Patents

Abstract

(57) [Abstract] [Purpose] To enable more stable demodulation of a reproduced ID signal including noise, jitter, and the like. [Structure] A phase comparator 301 and an up / down counter 302, and a frequency divider 303 or 3 for outputting a 13FH signal.
A digital PLL circuit is constituted by 04. The selection of the frequency divider 303 or 304 is performed by the switch 305, and the frequency divider that does not form the digital PLL circuit forms the phase comparison circuit together with the phase comparator 310. When the phase locked operation between the reproduction ID signal and the output of one frequency divider (13FH signal) is being performed by the digital PLL circuit, the reproduction ID by the phase comparison circuit is used.
The signal and the other frequency divider output (13FH signal) are compared in phase, and the switch 305 is switched every 2H.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a still picture reproducing apparatus, and more particularly to demodulation of an ID signal recorded at the same time as a video signal by a still video camera and containing information such as date.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram of a conventionally known recording / reproducing integrated still video camera. In the figure, 101 is a lens for forming an image of a subject on a sensor, 102 is a lens shutter for performing exposure control, 103 is a photoelectric conversion sensor, and 104 is a photoelectrically converted analog video signal converted into a digital signal. Convert to A /
D converter, 105 is a digital signal processing circuit (hereinafter referred to as “DSP”) that performs video signal processing, 106 is a D / A converter that converts a digital video signal into an analog signal, 1
Reference numeral 07 is a modulation circuit for recording (hereinafter referred to as “MOD”), 108 is a recording / reproducing amplifier (hereinafter referred to as “REC / PR”).
E ”), 109 is a disk drive, 110 is a driver for driving a lens shutter, 111 is a sensor 10
3, A / D converter 104, DSP 105 and D / A
A synchronization signal generator (hereinafter referred to as "SSG") that supplies a timing signal to the converter 106, 112 is a driver that drives the disk drive 109, 113 is a system controller that controls the entire camera, 114 is a first switch (SW1) , 115 is the second switch (SW
2), 116 is an ID signal demodulation circuit (ID gate array (IDGA)) for demodulating an ID signal, 117 is an encoder for generating a composite video signal, 118 is a demodulation circuit for reproduction (hereinafter referred to as “DEMOD”), 119 Is recording (REC), playback (PLAY), and off (OFF)
Is a mode switch for switching.

When the mode switch 119 is in the reproduction mode, the still video camera starts the reproduction operation. At this time, the image signal read from the disk drive 109 is input to the DEMOD 118 via the REC / PRE 108 and demodulated by the DEMOD 118. The demodulated signal is digitized by the A / D converter 104 and converted into DS.
After being processed by the P105, it is converted into an analog signal by the D / A converter 106, converted into a composite video signal by the encoder 117 and output to a monitor (not shown), and at the same time, the ID signal is demodulated by the REC / PRE 108 from the ID signal. It enters the circuit 116, is demodulated, and is displayed on the screen as information such as the date together with the reproduced image. The ID signal is obtained by performing differential phase shift keying modulation on information such as the recorded date and time, and recording it on the disc together with the video signal.

Next, FIG. 7 shows a conventional ID signal demodulation circuit 11
6 shows the configuration of No. 6. 201 is the master clock 14.318MH
z (= 910FH, where FH is the frequency of the horizontal sync signal HD) is divided into 1/70 and 13F for phase comparison with the reproduction ID signal (hereinafter referred to as "PBID")
It is a frequency divider that produces an H signal (reference signal). 202 is an exclusive OR circuit (hereinafter referred to as “E”) for phase comparison.
X-OR "), 203 is an 11-bit binary counter that counts up when the output of the EX-OR 202 is at the Hi level (high level), and 204 is an ID from the horizontal synchronization signal (HD) and the vertical synchronization signal (VD). It is a timing generation circuit that generates a timing signal for demodulation. 205 is the most significant bit (MS
The shift register for fetching B), 206 is the shift register 205, and after shifting by 8 bits, the system controller 1
13 is a data latch for reading data.

PB output from REC / PRE 108
The ID signal enters the frequency divider 201. Here, FIG. 8 (a)
The reset signal (Reset) is generated at the timing shown in (1), and at this timing, the frequency divider 201 matches the phase of the 13FH signal generated by dividing the PBID signal and the 910FH signal by 70 (dividing to 1/70).

In this way, the PBI is generated by the reset signal generated every 2H section (a period corresponding to two cycles of the HD signal).
Phase alignment of the D signal and the 13FH signal is performed. Then, the EX-OR 202 compares the phase of the 13FH signal generated in the next 2H section and the PBID signal (FIG. 8).
(B)).

While the output of the EX-OR 202 is at a high level (while the phase is different), the counter 203 counts up. Then, when it is sufficiently counted up and the most significant bit (MSB) = 1, it is taken into the shift register 205 at the data switching timing (Data in FIG. 8C). Then, the shift register 205
When 8 pieces of data are taken in, the data latch circuit 20
Latched at 6. At the same time, the timing generation circuit 204 sends an interrupt signal (IN
T) is generated and the data latched by the data latch circuit 206 is read into the system controller 113.

[0008]

However, in the above-mentioned conventional example, the reset operation in the generation of the 13FH signal as the reference signal for phase comparison is performed only once in the 2H section, and noise and jitter of the PBID signal are generated. However, there is a problem that the ID demodulation is weak and stable.

The present invention has been made in view of this point, and an object thereof is to provide a still picture reproducing apparatus capable of more stable demodulation of a reproduction ID signal containing noise, jitter, and the like.

[0010]

In order to achieve the above object, the present invention provides a still picture reproducing apparatus provided with a demodulation circuit for demodulating a differential phase shift keying ID signal, wherein the demodulation circuit has a digital phase. A lock loop circuit is included, and the demodulation operation is performed by switching the phase lock operation between the ID signal and the reference signal and the phase comparison operation.

[0011]

Operation: Phase lock operation between the ID signal and the reference signal, and I
While switching the phase comparison operation of the D signal and the reference signal,
The ID signal is demodulated.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an ID signal demodulation circuit of a still picture reproducing apparatus according to an embodiment of the present invention. In addition,
The overall configuration of this device is the same as the conventional one in FIG.
The circuit of FIG. 1 is used as the ID signal demodulation circuit 116 of FIG.

In FIG. 1, 301 is a reproduction ID signal (P
It is a phase comparator (PHASE DETECT) that performs a phase comparison between the BID) and the 13FH signal. Reference numeral 302 is an up / down counter that counts according to the output of the phase comparator 301. 303 is an up / down counter 30
4.0909MHz depending on carry and borrow output of 2
This is a frequency divider whose frequency division ratio is (260 FH). That is, when the carry is standing, the division by 19 is selected (the input signal is divided into 1/19), and when the borrow is standing, the division by 21 is selected (the input signal is divided by 21). Of 1), and when neither carry nor borrow is standing, the division of 20 is selected (the input signal is divided into 1/20). Also, the timing generator 3
Depending on the switching signal from 08, 20 frequency division may be selected regardless of the carry and borrow signals. Like the frequency divider 303, 304 divides the 260FH signal to 13F.
It is a frequency divider that generates an H signal.

A switching circuit 305 switches between the 13FH signal supplied to the phase comparator 301 and the 13FH signal supplied to the phase comparator 310 according to the switching signal from the timing generator 308. That is, when the switching signal from the timing generator 308 is low level, the terminals A and B and terminals C and D are connected respectively, and when the switching signal is high level, the terminals A and C and terminals B and D are respectively connected. It 306 is a phase comparator 3
A 9-bit binary counter that operates using the signal of 10 as an enable signal, 307 is a shift register that captures the output of the counter 306, and 309 is a shift register 307.
After 8 shifts, the system controller (11 in FIG.
3)), data latch for taking in data, 31
Reference numeral 0 is a phase comparator composed of an EX-OR circuit.

A phase comparator 301 constituting a digital PLL circuit of the ID signal demodulating circuit configured as described above,
The operations of the up / down counter 302 and the frequency divider 303 will be described with reference to the timing chart of FIG. Further, at this time, the switching circuit 305 outputs the 13FH to the phase comparator 301.
It is assumed that 13FH1 is selected for input as shown in FIG. As shown in FIG. 2, the output PHOUT of the phase comparator 301 is set at the rising edge of the PBID signal and reset at the rising edge of the 13FH1 signal.
This operation is realized, for example, by the configuration shown in FIG. Here, the up / down counter 302 has a PH
When OUT = H (high level), the count-up operation is performed, and when PHOUT = L (low level), the count-down operation is performed. In this embodiment, the up / down counter 3
02 has a 5-bit configuration, and the initial value is 10000B. The phase relationship between the PBID signal and the 13FH1 signal is shown in FIG.
In the states shown in (a) and (b), since PHOUT is at a low level for a longer time than at a high level ((c) in the figure), the up-down counter 302 has a count-up time. The time during which the countdown operation is performed becomes longer and a borrow occurs (BORROW becomes a high level ((d) in the figure). In response to this borrow output, the frequency divider 303 receives 2 by the selection circuit (SELECT).
One frequency division is selected ((a) in FIG. 2 (f)). Subsequently, the up-down counter 302 is reset to the initial value of 10000B when a borrow or carry occurs once. Then, when neither carry nor borrow is input to the frequency divider 303, 20 frequency division is selected ((b) in FIG.

In this way, the up / down counter 3
Every time a borrow output is output from 02, the frequency divider 303 outputs 2
Divide by 1 is selected, the phase of 13FH1 changes, and PHO
The high level period and the low level period of the UT approach in the same direction. When the PBID signal and the 13FH1 signal are out of phase by 180 ° (phase inversion state), PHO
The high level period and the low level period of the UT become equal to each other, and the phase lock state is set ((c) in FIG.

The digital PLL circuit operates as described above.

Next, the operation of the entire ID signal demodulation circuit will be described with reference to FIGS. It is assumed that the phase of the PBID signal has changed in (a) of FIG. At this time, since the switching signal ((c) in the figure) generated from the timing generator 308 is at a high level, the switching circuit 305 has the terminal A
Is connected to the terminal C, and the terminal B is connected to the terminal D. Therefore, the phase comparator 301 is supplied with the 13FH2 signal output from the frequency divider 304, and the phase comparator 310 is supplied with the 13FH1 signal output from the frequency divider 303.

In the PLL operation, the phase comparator 30
1, the digital PLL circuit including the up / down counter 302 and the frequency divider 304 operates as described with reference to FIG. 2, and the 13FH2 signal and the PBID signal are phase locked.

On the other hand, in the phase comparison operation, the frequency divider 3
The output 13FH1 signal of 03 and the PBID signal are compared in phase by the phase comparator 310. Then, in the part before (A) not shown, the 13FH1 signal completes the PLL operation and is locked in phase with the PBID signal. Therefore, in (a), since the phase of the PBID signal is inverted from that of the 13FH1 signal, the output of the phase comparator 310 becomes high level, and the counter 306 can count. Since the counter 306 is a 9-bit binary counter, the MSB of the counter 306 is 256.
High level after counting. Therefore, the MSB in FIG. 4 (f) is at a high level near the middle of the 2H period in (a). As a result, the phase inversion in (a) of the PBID signal is detected, and the signal is shifted to the shift register 307.
Are latched by (Data (0) in the same figure (g)).

Next, in the 2H period of (a), 13FH
The two signals are the phase comparator 301 and the up / down counter 30.
2 and the frequency divider 304 perform the PLL operation,
Phase locked to the ID signal. Then, in (b), the switching signal of the timing generator 308 ((c) in the figure) becomes low level, and the PBID signal and 13FH2
The signals are phase compared in phase comparator 310. Here, since the phases of the both are inverted with respect to each other, the counter 306 is in the enabled (countable) state.
Then, as in (a), the MSB becomes high level and is latched by the shift register 307 ((g) in the figure, Dat
a1).

Further, in (c), as in (a),
Phase comparison between the PBID signal and the 13FH1 signal is performed. At this time as well, since the phase is inverted as in (a) and (b), the high level of the MSB is latched in the shift register 307 ((g) in the figure, Data2). Then, in the next 2H period, since the phase is not inverted, the output of the phase comparator 310 becomes low level, and the counter 306 is in the disabled (count operation prohibited) state. Therefore, the MSB of the counter 306 maintains a low level,
Latched in the shift register 307 ((g) in the figure, D
ata3). In this way, 1 bit every 2H period
Data is latched in the shift register 307 one by one (Data 4 to 7 in FIGS. 4 and 5 (g)). When 8-bit data is latched in the shift register 307, L
The timing signal is output from the timing generator 308 to the data latch 309 ((d) in FIG. 5 (h)),
Data of 8 bits is collectively latched by the data latch 309.

Then, the timing generator 30
The INT signal from 8 is the system controller (11 in FIG. 6).
The system controller, which is output to (3) ((e) in FIG. 5I) and receives the signal, reads the 8-bit data latched by the data latch 309 via the data bus.

By repeating the above operation, the system controller reads the demodulated ID data in 8-bit units.

As described above, according to this embodiment, 13F
While one of the two frequency dividers 303 and 304 that outputs the H signal (13FH1 and 13FH2) performs the PLL operation, the output of the other frequency divider and the reproduction I
During the period in which the D signal is phase-compared and the other frequency divider performs the PLL operation, the output of the one frequency divider and the reproduction ID signal are phase-compared, so that noise, jitter, etc. are included. More stable demodulation of the reproduction ID signal becomes possible.

In the above-described embodiment, the phase inversion and non-inversion are detected by the high / low level of the MSB of the binary counter 306, but the present invention is not limited to this, and the MSB changes from 0 to 1. By setting a value larger than the value (100000000B for a 9-bit counter) as the detection threshold level, the PBID signal has noise and is not phase-inverted.
Even if the output of the phase comparator 310 is at the high level for a sufficiently long period and the counter is in the enable state, it is possible to prevent malfunction and further stabilize against noise.

Further, the detection threshold level may be set from the system controller.

[0029]

As described above in detail, according to the present invention, I
Since the ID signal is demodulated while switching the phase lock operation of the D signal and the reference signal and the phase comparison operation of the ID signal and the reference signal, more stable demodulation of the ID signal including noise, jitter, etc. It will be possible.

[Brief description of drawings]

FIG. 1 is an ID of a still image reproducing device according to an embodiment of the present invention.
It is a block diagram of a signal demodulation circuit.

FIG. 2 is a timing diagram for explaining the operation of the circuit of FIG.

3 is a block diagram showing a configuration of a phase comparator (301) in FIG.

4 is a timing diagram for explaining the operation of the circuit of FIG.

5 is a timing diagram for explaining the operation of the circuit of FIG.

FIG. 6 is a block diagram of a recording / playback integrated still video camera.

7 is a block diagram showing a configuration of an ID signal demodulation circuit in FIG.

FIG. 8 is a timing chart for explaining the operation of the circuit of FIG.

[Description of Reference Signs] 301 phase comparator 302 up / down counter 303, 304 frequency divider 305 switching circuit 306 counter 307 shift register 308 timing generator 309 data latch 310 phase comparator

Claims (1)

Claim: What is claimed is: 1. A still picture reproducing apparatus comprising a demodulation circuit for demodulating an ID signal subjected to differential phase shift keying modulation, wherein the demodulation circuit includes a digital phase lock loop circuit.
A still picture reproducing apparatus characterized by performing a demodulation operation by switching between a phase lock operation of a D signal and a reference signal and a phase comparison operation.