JPH05211180A - Charge transfer device - Google Patents

Abstract

(57) [Abstract] [Purpose] To realize a charge transfer device suitable for high-speed driving, in which noise generated internally is small and reset operation such as FDA is not required. A CCD channel 3 formed in a surface layer of a p-type well 2 on an n-type silicon substrate 1, a charge transfer electrode 7 and an output gate electrode provided on the CCD channel 3 via a gate insulating film 8. 6 and a reset drain 4 provided adjacent to the output end of the CCD channel 3, and the load resistance R is provided to the reset drain 4.
By applying a voltage via L, a high electric field that causes collision ionization is applied between the output end of the CCD channel 3 and the reset drain 4 during the signal charge reading operation,
The signal charge flowing from the channel 3 to the reset drain 4 is amplified, and the amplified current amplified by impact ionization and flowing to the reset drain 4 is converted into a voltage and taken out.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge transfer device used in a solid-state image pickup device or the like, and more particularly to a charge transfer device with improved signal charge detecting means.

[0002]

2. Description of the Related Art A CCD (charge coupled device) has an excellent feature that an analog signal can be transferred with low noise.
Currently, it is widely used in solid-state imaging devices. FIG.
Is a buried channel CCD with a conventionally known floating diffusion amplifier (FDA).
3 is a diagram showing an example of a cross section of an output portion in FIG. Also,
FIG. 19 shows an example of the voltage applied to each terminal shown in FIG.
0 indicates the state of the potential at each time point of t ₁ to t ₅ shown in FIG. The method of manufacturing the CCD and the principle of detecting the signal charge will be briefly described below.

As shown in FIG. 18, an n-type silicon substrate 1
After the p-type well 2, the n-type buried channel 3 and the gate insulating film 8 are formed thereon, the output gate (OG) electrode 6, the charge transfer electrode 7, and the reset gate (RG) electrode 11 are formed on the first layer and the first layer. It is installed by dividing the two-layer polycrystalline silicon film. Then, n ^{+ of} the floating diffusion portion (FD) 10 and the reset drain (RD) 4
A p ⁺ layer of the layer and the well contact 5 (which is also in contact with a channel stop not shown in the drawing) is formed.

In the example shown in FIG. 18, since an example of driving using two-phase clock pulses is considered, 3-channel
The impurity concentration of the region shown by 2 is made smaller than the concentration of the region of 3-1.

This CCD stores / transfers an electron mass generated by injection or light from a diffusion layer (not shown) to a potential well having a high potential formed in the channel 3 below the transfer electrode 7, and the amount of charge in the FD 10 is increased. Is converted into a voltage and then output through a two-stage source follower. Specifically, the signal charge is detected as follows by the change in the applied voltage shown in FIG. 19 and the potential shown in FIG.

During the period of t = t ₁ and t ₂ , the RG electrode 11 is turned on / off to initialize the potential of the FD 10 with the potential V _RD of the _RD 4 (reset operation). When φ ₁ becomes L level at t = t ₃ , the signal charge Q _SIG accumulated in the potential well immediately below the charge transfer electrode 7-1 is pushed out and FD
Inflow to 10. At this time, when the capacitance of the _{FD 10} is C _FD , the potential change of the _{FD 10} is ΔV _FD = Q _SIG / Q _FD , and the signal charge amount is converted into a voltage change and detected. After that, the RG electrode 11 is turned on again during the period of t = t ₄ and t _5.
/ OFF to perform the reset operation. (The accumulated signal charge Q _SIG is discharged to RD4.) By repeating this,
The signal charges sequentially carried are detected as a voltage change of the FD 10.

This structure has a simple manufacturing method and is widely used at present. However, there is a problem in that the S / N of the signal before amplification is deteriorated because the fluctuation of the potential due to thermal noise occurs when the FD potential is initialized. This fluctuation of the potential is expressed by <ΔQ ² > = kTC _FD
Therefore, it is called kTC noise.

In order to avoid this defect, F immediately after initialization is set.
There is a signal processing method (double sampling method) that takes a difference between the potential of the D portion and the potential when the signal charge is detected, but there is a problem that the high frequency noise component is folded back to the low frequency side.
S / N deterioration cannot be completely suppressed. Also,
When driving at high speed, such as in a high definition television (HDTV), it is difficult to generate sampling timing.

[0009]

As described above, the conventional F
In the method of detecting signal charge in CCD using DA,
There is a problem that the kTC noise cannot be completely removed, and the high-speed driving imposes a heavy load on the external circuit.

The present invention has been made in consideration of the above circumstances, and an object thereof is to eliminate kTC noise,
An object of the present invention is to provide a charge transfer device including a highly sensitive charge detection unit suitable for high-speed driving.

[0011]

The essence of the present invention is to provide a region to which a high electric field is applied before the signal charge reaches the drain diffusion layer for detecting / discharging the signal charge via the charge transfer portion. The signal charges injected into this region are amplified by impact ionization and then converted into a voltage for output.

That is, according to the present invention (claim 1), in a charge transfer device for transferring and reading out signal charges in one direction, a plurality of charge transfers are performed on a charge transfer channel formed on the surface of a semiconductor substrate via an insulating film. A charge transfer section including a portion where electrodes are arranged, a signal charge detection section that detects the signal charge transferred by the charge transfer section, and a high electric field region that causes impact ionization in a part of the charge transfer section, Means for amplifying electric charges by impact ionization in a high electric field region.

According to the present invention (claim 2), in a charge transfer device for transferring and reading out signal charges in one direction, a plurality of charge transfers are performed via an insulating film on a charge transfer channel formed on the surface of a semiconductor substrate. The partial charge transfer section in which the electrodes are arranged, the drain diffusion layer provided adjacent to the output end of the charge transfer section for detecting and discharging the signal charge, and the charge transfer section of the charge transfer section during the signal charge read operation A means for amplifying the signal charges flowing from the charge transfer section to the drain diffusion layer by applying a high electric field that causes collision ionization between the output end and the drain diffusion layer, and an amplification current amplified by the collision ionization and flowing in the drain diffusion layer are provided. And a means for detecting.

The present invention (Claim 3) includes (Claim 2).
In the above charge transfer device, the drain diffusion layer is provided in self-alignment with the output gate electrode at the output end of the charge transfer section.

[0015]

According to the present invention (Claims 1 and 2), the signal charge from the charge transfer unit is directly flown to the drain diffusion layer without requiring the FD unit for temporarily storing the charge for signal charge detection. Therefore, the signal charge is completely discharged, and kTC noise does not exist in principle. Further, since the reset operation for detecting the signal charge is not necessary, the reset pulse becomes unnecessary, which is suitable for high speed driving.

Further, according to the present invention (claim 3), the region where the potential barrier is likely to occur is completely covered with the output gate electrode and is easily controlled by the output gate electrode, so that the potential at the output end of the channel is increased. The barrier does not occur, and thus the afterimage can be prevented from occurring.

[0017]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a plan view showing a schematic structure of a charge-coupled device according to a first embodiment of the present invention, and FIG. 2 is an arrow A in FIG.
It is a -A 'sectional view. p-type well 2 on n-type silicon 1
To form an n-type embedded CC in the surface layer of the p-type well 2.
After forming the D channel 3 and the channel stop layer 5, for example, a silicon oxide film (SiO 2) is formed as the gate insulating film 8.
₂ film) is formed. Next, the output gate (OG) electrode 6 and the charge transfer electrode 7 are provided by dividing the first and second polycrystalline silicon by etching, for example. Then, the n ⁺ layer of the reset drain (RD) 4 is formed.

At this time, it is desirable that the distance L between the channel end and RD4 be equal to or less than the channel depth d _ch and the depth d _{RD of} RD4. This is to prevent a barrier from being generated in the potential in the vicinity of the channel end even if a large voltage is not applied to RD4 (even a practically applied voltage). Although not shown in FIG. 1, a light-shielding film is provided on this via an insulating film.

The transfer of the signal charge in this embodiment is performed by two-phase clock pulses φ ₁ and φ _{2 as} shown in FIG. In FIG. 3, the voltages V _RD , the substrate bias V _SUB and O applied to the RD 4 are shown together with the clocks φ ₁ and φ _2.
The applied voltage φ _OG to the G electrode 6 is shown. A DC voltage V _RD is applied to RD4 via a load resistor R _L.

Next, the principle of charge detection in this embodiment will be described. FIG. 4 is a schematic diagram showing the state of the potential at the times t ₁ and t ₂ shown in FIG. At t = t ₁ , the signal charge existing immediately below the transfer electrode 7-1 is t
When the potential of φ ₁ drops at = t ₂ , it flows into the region between the RD 4 and the channel 3 where a high electric field is applied. At this time, if the electric field is sufficiently large, the signal charge that has flowed in is used as a seed current to cause collision ionization and the current is multiplied. The signal charge can be detected by converting this current into a voltage by the load resistance R _L.

Since this charge detector amplifies the signal before taking it out as a voltage, it has the characteristics that the noise generated inside is small and the reset operation unlike FDA is not required. Therefore, the reset pulse does not jump into the output and it is not necessary to newly generate a pulse with a different timing, which is suitable for high-speed driving.

According to the experiments conducted by the present inventors, d _ch =
When 0.6 μm, d _RD = 0.8 μm, and L = 0.8 μm, it was confirmed that if V _RD is 15 V or more, it is possible to multiply the signal charge by the impact ionization. Furthermore, it was confirmed that the detection sensitivity was sufficiently high.

As described above, according to this embodiment, the RD4 is provided adjacent to the output end of the CCD channel.
Since a high electric field is applied to the CD channel 3 to detect the current flowing in the RD 4, it is possible to amplify and detect the signal charge by impact ionization. Further, in this case, since the signal is amplified before being taken out as a voltage, a reset operation like FDA is not required, and thus it is suitable for high speed driving with less noise.

FIG. 5 is a plan view showing a schematic configuration of the second embodiment of the present invention. Since the manufacturing method and operation are the same as those in the first embodiment, only the differences from the first embodiment will be described here.

In the signal charge detector according to the present invention, since the pn junction of RD4 is reverse biased, p
The reverse current of the n-junction contributes to the noise generated by the detector. To suppress this, one method is to reduce the bonding area of RD4. Therefore, in this embodiment, RD
By reducing the width W _RD of 4, the reverse current is suppressed. Further, the channel width W _E at the output end is made narrower than the channel width W _ch at the transfer portion so that the signal current flows evenly in the vicinity of RD4.

With such a structure, the same effects as those of the first embodiment can be obtained, and since the factors causing the noise are reduced, a signal having a higher S / N ratio can be obtained. It becomes possible to detect.

FIG. 6 is a plan view showing the schematic construction of the third embodiment of the present invention. Since the manufacturing method and operation are the same as those in the first embodiment, only the differences from the first embodiment will be described here.

In this embodiment, the channel width W _E at the output end is
_Is wider than the channel width W _ch of the transfer part. That is,
W _E ≧ W _ch . Therefore, the two-dimensional effect of the channel stop potential is weakened, and the potential barrier is less likely to occur at the channel end. That is, since the central portion of the output end is sufficiently separated from the channel stop layer 5, even if potential barriers exist on both sides, the potential barrier hardly occurs in the central portion. Therefore, from the CCD channel 3 to the RD without the influence of the potential barrier.
It becomes possible to flow the signal charges to the signal line 4.

FIG. 7 is a plan view showing the schematic construction of the fourth embodiment of the present invention. Since the manufacturing method and operation are the same as those in the first embodiment, only the differences from the first embodiment will be described here.

[0031] In this embodiment, to expand the distance between the n ⁺ layer and p ⁺ layer of the channel stop 5 RD4, thereby reducing the reverse current. Also in this case, as in the second embodiment, it is possible to reduce the cause of noise and improve the S / N ratio.

FIG. 8 is a sectional view showing the schematic construction of the fifth embodiment of the present invention. Since the manufacturing method and operation are the same as those in the first embodiment, only the differences from the first embodiment will be described here.

In this embodiment, a region to which a high electric field for causing impact ionization is applied uses the i layer 9 instead of the reverse biased pn junction. Even with such a configuration, it is possible to multiply and detect signal charges due to impact ionization.

FIG. 9 is a sectional view showing a schematic structure of the sixth embodiment of the present invention. Since the manufacturing method and operation are the same as those in the first embodiment, only the differences from the first embodiment will be described here.

In this embodiment, the bias resistors R ₁ and R _{2 are}
RD4 is connected to the emitter of the transistor whose base potential is fixed by, and the output is taken from the collector of this transistor. In the first to fifth embodiments, since the output voltage is taken out by the resistance, the output voltage is fed back to the potential of the RD section 4, and the multiplication factor of impact ionization changes depending on the magnitude of the signal charge. On the other hand, in this embodiment, this feedback can be suppressed.

FIG. 10 is a sectional view showing the schematic arrangement of the seventh embodiment of the present invention. Since the manufacturing method and operation are the same as those in the first embodiment, only the differences from the first embodiment will be described here.

In this embodiment, a MOS transistor is used instead of the bipolar transistor of the sixth embodiment, and the feedback of the output voltage can be suppressed as in the sixth embodiment.

Next, another embodiment of the present invention will be described. FIG. 11 shows the configuration of the main part of the charge transfer device according to the above-described embodiments and the potential state at the end of the charge transfer part. In the structure in which the transfer electrode is not arranged in the charge transfer portion between the channel output end and the drain as shown in FIG. 11A, a potential barrier is likely to occur at the channel output end as shown in FIG. 11B. Such a potential barrier becomes a cause of an afterimage. Therefore, in the following examples, the occurrence of this potential barrier is prevented.

FIG. 12 is a plan view showing a schematic structure of an eighth embodiment of the present invention, and FIG. 13 is a sectional view taken along the line BB 'in FIG. The basic structure is the same as that of FIGS. 1 and 2, but in this embodiment, the OG electrode 6 extends to the RD 4. Specifically, the n ⁺ layer of the RD 4 is formed by diffusing the OG electrode 6 as a mask, that is, the RD 4 is formed in self-alignment with the OG electrode 6.

The signal charge transfer in this embodiment is performed by the two-layer clock pulses φ ₁ and φ ₂ as in the first embodiment (see FIG. 3). The charge detection principle is similar to that of the first embodiment (see FIG. 4). Therefore, the same effect as that of the first embodiment can be obtained. Furthermore, since the OG electrode 6 extends to RD4, there is no potential barrier at the channel end as shown in FIG. 11B, and no signal charge remains. Therefore, it is possible to reliably prevent the occurrence of an afterimage. In order to prevent the potential barrier from being generated at the channel end, it is not always necessary to connect the OG electrode 6 and the RD.
4 does not need to be formed in a self-aligned manner, and may be formed so that the end portion of the OG electrode 16 overlaps RD4.

FIGS. 14A and 14B are for explaining the ninth embodiment of the present invention. FIG. 14A is a plan view and FIG. 14B is a sectional view taken along the line CC ′ of FIG. 14A. The basic structure is similar to that of the eighth embodiment, but in this embodiment, R for discharging the signal charge is used.
D4 is provided on the side surface of the channel end. Therefore, the width W of the path through which the current flows can be freely designed. Further, as shown in FIG. 15, the RD 4 may be provided so as to surround the channel end portion.

FIG. 16 is a plan view showing the schematic construction of the tenth embodiment of the present invention, and FIG. 17 is a sectional view taken along the line DD 'in FIG. In this embodiment, n-type silicon is used for the substrate 1, and the p-type well 2 and the gate insulating film 8 are made of, for example, SiO 2.
After forming ₂ , the part 6-1 of the OG electrode 6 is, for example,
It is installed by dividing the polycrystalline silicon of. In addition, the n-type buried channel 3 and RD4 have n ⁺
The layer, the p ⁺ layer of the channel stop 5, is formed in self-alignment with the OG 6-1. At the same time, the p ⁺ layer of the well contact 9 is also formed.

Then, the remaining portion 6-2 of the OG electrode 6 is
The charge transfer electrode 7 is provided, for example, by dividing the second and third polycrystalline silicon by etching. further,
Although omitted in FIG. 14, a light-shielding film is provided on top of this to complete the process. In this embodiment, 6-1 and 6-2 are connected so that the same potential can be applied, but different potentials can be applied independently without such a connection. The operation is similar to that of the first embodiment.

The present invention is not limited to the above embodiments. In the embodiment, the resistor is used to convert the signal current into the voltage, but an active load may be used. Further, p-type silicon may be used as the silicon substrate 1, and in this case, the p-type well 2 is unnecessary. In addition, various modifications can be made without departing from the scope of the present invention.

[0045]

As described in detail above, the present invention (claim 1,
According to 2), a region to which a high electric field is applied is provided while the signal charge reaches the drain diffusion layer for detecting / discharging the signal charge via the charge transfer portion, and is injected into this region. Since the signal charge is amplified by impact ionization and then converted into a voltage and output, a noise transfer that is small inside is realized, and a charge transfer device suitable for high-speed driving that does not require a reset operation like FDA is realized. It becomes possible to do. Furthermore, according to the present invention (claim 3), in addition to the above effects, it is possible to reliably prevent the occurrence of an afterimage due to the potential barrier at the end of the charge transfer portion.

[Brief description of drawings]

FIG. 1 is a plan view showing a schematic configuration of a charge transfer device according to a first embodiment of the present invention.

FIG. 2 is a sectional view taken along the line AA ′ of FIG.

FIG. 3 is a schematic diagram showing an applied voltage waveform in the first embodiment.

FIG. 4 is a schematic diagram showing potential states at times t ₁ and t ₂ in the _first embodiment.

FIG. 5 is a plan view showing a schematic configuration of a second embodiment.

FIG. 6 is a plan view showing a schematic configuration of a third embodiment.

FIG. 7 is a plan view showing a schematic configuration of a fourth embodiment.

FIG. 8 is a sectional view showing a schematic configuration of a fifth embodiment.

FIG. 9 is a sectional view showing a schematic configuration of a sixth embodiment.

FIG. 10 is a sectional view showing a schematic configuration of a seventh embodiment.

FIG. 11 is a schematic diagram for explaining improvements in the eighth to tenth embodiments.

FIG. 12 is a plan view showing a schematic configuration of an eighth embodiment.

13 is a sectional view taken along the line BB ′ of FIG.

FIG. 14 is a plan view and a sectional view for explaining a ninth embodiment.

FIG. 15 is a plan view showing a modification of the ninth embodiment.

FIG. 16 is a plan view showing a schematic configuration of a tenth embodiment.

17 is a cross-sectional view taken along the line DD ′ of FIG.

FIG. 18 is a cross-sectional view showing a schematic configuration of a charge coupled device having a conventional FDA.

FIG. 19 is a schematic diagram showing an applied voltage waveform in a conventional device.

FIG. 20 is a schematic diagram showing a potential state in a conventional device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... N-type silicon substrate, 2 ... P-type well, 3 ... N-type embedded CCD channel, 4 ... Reset drain (RD), 5 ... Channel stop, 6 ... Output gate (OG) electrode, 7 ... Charge transfer electrode, 8 ... gate insulating film, 9 ... well contact.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H04N 5/335 Z 4228-5C

Claims (3)

[Claims] 1. A charge transfer part including a part in which a plurality of charge transfer electrodes are arranged via an insulating film on a charge transfer channel formed on a surface of a semiconductor substrate, and a signal charge transferred by the charge transfer part is detected. And a means for amplifying the signal charges by the impact ionization in the high electric field region. And a charge transfer device. 2. A charge transfer section including a portion in which a plurality of charge transfer electrodes are arranged on an electric charge transfer channel formed on the surface of a semiconductor substrate with an insulating film interposed between the charge transfer section and an output end of the charge transfer section. A high electric field that causes collision ionization is applied between the drain diffusion layer for detecting and discharging the signal charge and the output end of the charge transfer channel and the drain diffusion layer during the signal charge reading operation, and the charge transfer is performed. A charge transfer device comprising means for amplifying a signal charge flowing from the portion to the drain diffusion layer, and means for detecting an amplified current amplified by the impact ionization and flowing to the drain diffusion layer. 3. A charge transfer section including a portion in which a plurality of charge transfer electrodes are arranged on an electric charge transfer channel formed on a surface of a semiconductor substrate with an insulating film interposed between the charge transfer section and an output end of the charge transfer section. A high electric field that causes collision ionization is applied between the drain diffusion layer for detecting and discharging the signal charge and the output end of the charge transfer channel and the drain diffusion layer during the signal charge reading operation, and the charge transfer is performed. Section for amplifying a signal charge flowing to the drain diffusion layer, and means for detecting an amplified current amplified by the impact ionization and flowing to the drain diffusion layer.
A charge transfer device, which is provided in self-alignment with an output gate electrode at an output end of the charge transfer unit.