JPH0521376A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) [Abstract] [Purpose] An object is to obtain a semiconductor device which can be miniaturized and which is highly integrated. A step of forming a conductive layer on a main surface of a semiconductor substrate, a step of forming an isolation oxide film on the main surface of the semiconductor substrate for separating the conductive layer from other conductive layers,
Forming an interlayer insulating film on the semiconductor substrate including the isolation oxide film, and selectively etching the interlayer insulating film using a mask, thereby exposing a part of the surface of the conductive layer The method further includes a step of forming a connection hole, and a step of forming a wiring layer for electrically connecting to the conductive layer via the connection hole on the semiconductor substrate.
Prior to etching the interlayer insulating film, a protective film for protecting the isolation oxide film is formed on the isolation oxide film so that the isolation oxide film is not etched during the etching even when the mask is displaced. It is characterized by

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a method of manufacturing a semiconductor device, and more specifically, it enables miniaturization, improvement in integration degree, and simplification of process. The present invention relates to a method for manufacturing a semiconductor device, which is improved so that

[0002]

11 to 15 are sectional views showing steps of forming a contact in an interlayer insulating film and further forming an aluminum wiring in manufacturing a conventional semiconductor device.

Referring to FIG. 11, p type conductive layer 1 is formed on the main surface of a silicon substrate. On the main surface of the p-type conductive layer 1,
A p-type isolation 2 and an isolation oxide film 3 (silicon thermal oxide film) for separating active elements are formed.
The isolation oxide film 3 is formed by the LOCOS method. After that, an n-type impurity such as arsenic ion is ion-implanted with an energy of 60 KeV in an amount of 2 × 10 ¹⁵ cm ⁻² . Then, heat treatment is performed at 900 ° C. for 30 minutes in an oxygen atmosphere. Thereby, n-type diffusion layer 4 is formed on the main surface of p-type conductive layer 1.

Referring to FIG. 12, a chemical vapor deposition method (C) is performed on a semiconductor substrate including isolation oxide film 3 under reduced pressure.
The interlayer insulating film 5 (silicon oxide film) is formed by the VD method).
For example, 250 nm is deposited. A photoresist film 9 is formed on the interlayer insulating film 5, and an opening 9a is formed in the photoresist film 9 at a portion corresponding to a contact hole to be formed later by a well-known photolithography method.

Referring to FIG. 13, with the photoresist film 9 as a mask, the interlayer insulating film 5 is over-etched by about 40% with respect to the film thickness, using a Freon-based gas such as trifluoromethane. The reason for performing overetching is as follows. That is, the film thickness of the interlayer insulating film 5 formed by the CVD method has a fluctuation of about 10%, and in-plane non-uniformity of about 10% is also caused by etching itself using a Freon-based gas. This is because the etching rate is non-uniform due to the film quality of the interlayer insulating film 5. In addition, it is necessary to consider the nonuniformity of the etching rate of the etching apparatus itself for each process.

By this over-etching, the contact hole 10 is formed in the interlayer insulating film 5. After forming the contact hole 10, n-type impurity ions such as phosphorus ions having a large thermal diffusion coefficient are implanted into the contact hole 10 at 1 × 10 ¹⁴ cm ⁻² .

Referring to FIG. 14, after removing photoresist film 9, heat treatment is performed at 900 ° C. in a nitrogen atmosphere for 20 minutes. As a result, the phosphorus ions that were previously implanted are activated and diffused, and the second n-type impurity diffusion layer 13 becomes p-type.
It is formed in the mold conductive layer 1. Second n-type impurity diffusion layer 1
The reason for forming 3 will be described later.

Referring to FIG. 15, an alloy in which a small amount of silicon is mixed with aluminum is provided on the entire upper surface of the silicon substrate.
For example, it is deposited to a thickness of 1 μm by a sputtering method.
After that, this is selectively etched by a photolithography method to form an aluminum wiring layer 11 electrically connected to the n-type diffusion layer 4 through the contact hole 10.

FIG. 16 is a plan view of the semiconductor device manufactured as described above. 12, FIG. 13 and FIG.
6, the distance 1 between AA in the figure is the distance between the sidewall of the contact hole 10 and the end of the isolation oxide film 3.

Considering the overlay accuracy by the photolithography method, the distance l of AA is set to about 0.2 μm.

[0011]

The problems of the conventional method of manufacturing a semiconductor device will be described below.

FIG. 17 shows A in FIG. 12 and FIG.
It is the figure which pointed out the problem when the misalignment occurs when the setting of −A is set to 0 μm. Referring to FIG. 17, when a misalignment of 0.2 μm occurs in the photolithography method, in forming contact hole 10, 40% overetching of interlayer insulating film 5 (the etching rate for the silicon oxide film is 50 nm / Min) is used to etch the isolation oxide film 3 by about 100 nm in the thickness direction, and a part of the p-type isolation layer 2 is exposed in the contact hole 10 ( 10c shows the exposed portion). As a result, there is a problem that a junction leak and a failure of the junction breakdown voltage occur.

However, as described above, referring to FIGS. 14 and 18, when the second n-type impurity diffusion layer 13 is formed, the p-type isolation layer 2 is contacted with the contact at the photolithography step. Not exposed in hole 10. In such a case, even if the aluminum wiring layer 11 is formed, problems such as junction leak and junction breakdown voltage do not occur.

However, in this case, the effective element isolation interval is not the distance BB between the n-type impurity diffusion layers 4 and 4, but the end of the second n-type impurity diffusion layer 13 and the n-type impurity diffusion. It is the distance C-C to the edge of the layer 4. Therefore, when the BB distance is 0.8 μm and the element isolation capability is sufficient, the contact hole 10 is 0.2 μm.
If they are formed deviated from each other, the isolation oxide film 3 is also etched, and as a result, the effective isolation width C-C becomes 0.6 μm, and element isolation may become impossible.

As described above, according to the conventional method, referring to FIG. 13, the side wall of contact hole 10 and isolation oxide film 3 are formed.
It is not possible to reduce the distance A-A from the end of the. As a result, there is a problem that the semiconductor device cannot be miniaturized and improvement in the degree of integration cannot be expected. Further, in order to prevent abnormal junction leak and junction breakdown voltage failure, the ion implantation step shown in FIG. 13 and the heat treatment step at 900 ° C. shown in FIG. 14 are required, which causes a problem that the manufacturing step becomes complicated. ..
Further, in manufacturing a semiconductor device composed of a MOS transistor having a fine gate length, there is a problem that a margin cannot be expanded by reducing heat treatment.

The present invention has been made in order to solve the above-mentioned problems, and has been improved so that it can be miniaturized, the degree of integration can be improved, and the process can be simplified. Another object is to provide a method for manufacturing a semiconductor device.

[0017]

A method of manufacturing a semiconductor device according to the present invention includes a step of forming a conductive layer on a main surface of a semiconductor substrate, and a step of forming the conductive layer on the main surface of the semiconductor substrate with another conductive layer. A step of forming an isolation oxide film for separating from the above, a step of forming an interlayer insulating film on the semiconductor substrate including the isolation oxide film, and a step of selectively etching the interlayer insulating film using a mask, A step of forming a connection hole exposing a part of the surface of the conductive layer, and a step of forming a wiring layer for electrically connecting to the conductive layer through the connection hole on the semiconductor substrate. , Is provided. Then, in order to solve the above problems, prior to the etching of the interlayer insulating film, the isolation oxide film is not etched on the isolation oxide film so that the isolation oxide film is not etched during the etching even when the mask is displaced. It is characterized in that a protective film for protecting the oxide film is formed.

[0018]

According to the method of manufacturing the semiconductor device of the present invention,
Prior to etching the interlayer insulating film, a protective film for protecting the isolation oxide film is formed on the isolation oxide film so that the isolation oxide film is not etched during etching even if the mask is displaced. Even if the distance between the side wall and the end of the isolation oxide film is reduced, the isolation oxide film is not etched when the contact hole is formed.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

1 to 5 are process diagrams of a method of manufacturing a semiconductor device according to an embodiment of the present invention, which are shown in cross-sectional views.

Referring to FIG. 1, p-type conductive layer 1 is formed in a silicon substrate. a p-type isolation layer 2 for separating active elements on the main surface of the p-type conductive layer 1;
The isolation oxide film 3 (silicon thermal oxide film) is formed by the LOCOS method. After that, an n-type impurity such as arsenic ion is ion-implanted at an energy of 60 KeV in an amount of 2 × 10 ¹⁵ cm ⁻² , and then heat treatment is performed for 30 minutes in an oxygen atmosphere at 900 ° C. Thereby, n-type diffusion layer 4 is formed on the main surface of p-type conductive layer 1. On the silicon substrate including the isolation oxide film 3, a silicon oxide film is deposited as the interlayer insulating film 5 to a thickness of 100 nm by, for example, the low pressure CVD method.

Referring to FIG. 2, a polycrystalline silicon film 6 is formed on the interlayer insulating film 5 by, for example, a low pressure CVD method.
00 nm is deposited. A photoresist film 7 is formed on the entire surface of the polycrystalline silicon film 6. The photoresist 7 is patterned by photolithography so that the residual pattern remains over the upper portion of the isolation oxide film 2.

Referring to FIGS. 2 and 3, the polycrystalline silicon film 6 is selectively removed using a photoresist film 7 as a mask and a Freon-based gas, for example, a mixed gas of carbon tetrafluoride and oxygen. To etch. As a result, the protective film 6 made of polycrystalline silicon covers the upper portion of the isolation oxide film and protects the isolation oxide film 3 from etching in a later step.
a is formed.

Referring to FIG. 3, a silicon oxide film 8 as an insulating layer is formed on the interlayer insulating film 5 so as to cover the protective film 6a.
Is deposited to a thickness of 150 nm by, for example, a low pressure CVD method. A photoresist film 9 is formed on the silicon oxide film 8. The photoresist film 9 is patterned by a photolithography method so that an opening is formed in a portion where a contact hole is to be formed.

Referring to FIGS. 3 and 4, the photoresist film 9 is used as a mask and a Freon-based gas such as methane trifluoride is used to form a silicon oxide film 8 (also a part of the interlayer insulating film). And the interlayer insulating film 5 are simultaneously etched vertically. The contact hole 10 is formed by this vertical etching. Contact hole 10
Is an opening portion 1 exposing a part of the surface of the n-type diffusion layer 4.
0b and an opening portion 10a exposing a part of the surface of the protective film 6a. In etching using methane trifluoride, it is possible to make the etching selection ratio of the silicon oxide film and the polycrystalline silicon film 15 or more by optimizing the gas flow rate and the etching power. Therefore, during the vertical etching, the protective film 6a acts to protect the isolation oxide film 3 from etching, and the isolation oxide film 3 is not etched.

Referring to FIG. 5, an alloy for connecting the n-type diffusion layer 4 and another conductive layer, for example, an alloy in which silicon is added to aluminum is deposited to a thickness of 1 μm on the entire surface of the substrate by a sputtering method. .. By photolithography method,
A desired resist is formed, and this alloy is selectively etched with a chlorine-based gas to form the aluminum wiring layer 11. FIG. 6 is a plan view of the obtained semiconductor device.
Corresponding parts are designated by the same reference numerals, and description thereof will be omitted.

As described above, in the present embodiment, FIG.
Referring to, since the protective film 6a covers the upper portion of the isolation oxide film 3, the isolation oxide film 3 is not etched even if the contact hole 10 is misaligned due to mask misalignment. As a result, the width of element isolation does not become substantially narrow when the contact hole 10 is opened, unlike the conventional case, so that the phenomenon that element isolation cannot be performed does not occur.

Further, referring to FIG. 4, the contact hole 10 corresponds to the p-type isolation layer 2 under the isolation oxide film 3.
Is not exposed, therefore, even if the step of implanting an n-type impurity into the contact hole 10 is not introduced,
It is possible to prevent the occurrence of abnormal leakage between the silicon substrate and the p-type conductive layer 1 and the decrease in junction breakdown voltage.

In the above embodiment, the protective film 6a is a polycrystalline silicon layer to which impurities are not added, but the present invention is not limited to this. That is, it may be a polycrystalline silicon film to which phosphorus is added as an impurity, a so-called phosphorus-doped polycrystalline silicon film. Also,
It may be a so-called phosphorus-deposited polycrystalline silicon film to which phosphorus is added after the film is formed. Furthermore, after the film is formed, arsenic ions, for example, with an energy of 50 KeV,
It may be a polycrystalline silicon film which is made conductive by implanting it in an amount of 2 × 10 ¹⁵ cm ⁻² and then heat treating it at 900 ° C. for 20 minutes. Further, not only the polycrystalline silicon film but also a so-called polycide structure film made of a refractory metal film such as a tungsten silicide film or a molybdenum silicide film or a composite film of a refractory metal film and a polycrystalline silicon film may be used. .. Further, when the contact is etched, the same effect can be obtained even if the silicon nitride film is used as the resistant film. For example, in etching using methane trifluoride, by optimizing the gas flow rate and etching power, the etching selection ratio (with respect to the silicon oxide film) is set to 2 for the tungsten silicide film.
It is possible to set the ratio to 0: 1 and the silicon nitride film to 5: 1.

In the above embodiment, the case where the protective film 6a is formed so as to cover the entire upper surface of the isolation oxide film 3 is illustrated with reference to FIGS. 5 and 6, but as shown in FIG. You may comprise so that the oxide film 3 may be covered only partially. In addition, in FIG. 7, the same reference numerals are given to corresponding parts,
The description is omitted.

FIG. 8 is a plan view of a semiconductor device according to another embodiment of the present invention. In the embodiment shown in FIG.
The protective film 6a was electrically floating. Therefore, only the opening portion 10b of the contact hole 10 on the n-type diffusion layer 4 was involved in the connection with the next wiring layer. On the other hand, in the embodiment shown in FIG. 8, the protective film 6a is separately connected to the n-type diffusion layer 4 through the direct contact hole 12 provided on the n-type diffusion layer 4. Therefore, of the contact hole 10, the open portion 10a on the protective film 6a also participates in the connection with the next aluminum wiring layer. Therefore, the aluminum wiring layer and n
The connection with the mold diffusion layer 4 is performed with lower resistance.

9 and 10 show IX- in FIG.
It is sectional drawing which follows the IX line, and shows the manufacturing method in this part. A p-type conductive layer 1 is formed on a silicon substrate. An n-type diffusion layer 4, p-type isolation layer 2 and isolation oxide film 3 are formed on the main surface of p-type conductive layer 1. An interlayer insulating film 5 is formed on the substrate including the isolation oxide film 3. A photoresist film 30 having an opening at a desired portion is formed on the interlayer insulating film 5. Using the photoresist film 30 as a mask, the interlayer insulating film 5 is selectively etched using, for example, methane trifluoride to open the direct contact hole 12.

Referring to FIGS. 9 and 10, after removing photoresist film 30, a polycrystalline silicon film is deposited on the entire surface and is selectively etched using a photolithography method and a Freon-based gas. As a result, a polycrystalline silicon film 6b, which is an extension of the protective film 6a, is formed. Next, the silicon oxide film 8 is formed on the entire surface. Next, after a predetermined process, the semiconductor device shown in FIG. 8 is obtained.

In the above embodiment, the case where the aluminum wiring is connected to the n-type diffusion layer through the contact hole is shown as an example, but the present invention is not limited to this. Crystalline silicon, refractory metal, and refractory metal polycide can also be used as wiring.

Further, in the above-mentioned embodiment, the case where the contact hole is opened on the n-type impurity layer formed in the p-type conductive layer in the silicon substrate is illustrated, but the present invention is not limited to this. Alternatively, the present invention can be applied to the case where the contact hole is formed on the p-type impurity layer formed in the n-type conductive layer in the silicon substrate.

FIG. 19 is a plan view of a semiconductor device according to still another embodiment of the present invention. Referring to FIG. 19, in this embodiment, the protective film 6 that prevents the direct contact hole 12 from etching the isolation oxide film 3 is
It is used as the gate electrode of a type transistor.

After forming a gate oxide film with a thickness of, for example, 20 nm on the main surface of P type conductive layer 1 separated by isolation oxide film 3, a polycrystalline silicon film with a thickness of, for example, 200 nm is used to form a MOS type transistor. The gate electrode 6 is formed by the photolithography method and the dry etching method. Then, for example, arsenic ions are added at 4 × 10 ¹⁵ c
After the m ⁻² implantation, the source / drain regions 14 are formed by performing a heat treatment at 950 ° C. for 30 minutes. As a result, an n-channel MOS type transistor is formed.

Next, a direct contact hole 12 for connecting the gate electrode 6 of this MOS transistor and the other diffusion layer 15 is opened over these two. After that, the two are connected by, for example, the second polycrystalline silicon film 16. At this time, there is the isolation oxide film 3 near the direct contact hole 12, and the diffusion layer 15 may be formed due to misalignment or process variations.
There is a possibility that the element isolation characteristics of another diffusion layer may deteriorate.
Therefore, the direct contact hole 12 is prevented from etching the isolation oxide film 3a by deforming a part 6a of the gate electrode 6 as shown in the figure.

The direct contact hole 12 that is opened over both the gate electrode 6 and the diffusion layer 15 as in this example is called a shared type direct contact hole.

FIG. 20 is a plan view of a semiconductor device according to still another embodiment of the present invention. Referring to FIG. 20, the diffusion layer 15 and the source / drain region 1 of the MOS transistor are formed by the shared direct contact hole 12.
4 is predicted to deteriorate, the portion 6a of the gate electrode 6 formed of polycrystalline silicon in the vicinity where the direct contact hole 12 is opened is
It deforms along the isolation oxide film 3 as shown in the figure.

In the example shown in FIGS. 19 and 20,
A direct contact hole is opened so that the gate electrode of the MOS transistor and the diffusion layer are exposed at the same time,
Although an example in which the connection is made with polycrystalline silicon is shown, the same effect as that of the embodiment can be obtained even when the connection is made with aluminum wiring after opening the contact hole.

Next, an embodiment in which the present invention is applied to an actual MOS type static RAM will be described.

FIG. 21 is an equivalent circuit diagram of a MOS static RAM with a high resistance as a load. One cell is
Two access transistors 17,18, two driver transistors 19,20, two high resistance loads 21,2
2, bit lines, bit lines 23 and 24, word line 25, high resistance loads 21 and 22, and driver transistor 19,
It is constituted by a flip-flop formed by forming cross-couple wirings 26 and 27 with the node of the inverter formed by 20.

FIG. 22 shows an actual MOS type static R
It is a pattern diagram of AM. It shows up to element isolation, formation of MOS type transistors, formation of shared type direct contact holes, and formation of flip-flops by cross-couple wiring. In FIG. 22, 18
Is an isolation oxide film, 29 is a gate electrode of a driver transistor, 30 is a direct contact hole, 31 is second polycrystalline silicon, 26 and 27 are cross-coupled wiring, 1
Reference numerals 7 and 18 are access transistors, 19 and 20 are driver transistors, and 25 is a word line.

In this cell, a shared direct contact hole 30 for connecting the gate electrodes 29 of the driver transistors 19 and 20 and the source / drain regions of the access transistors 17 and 18 is opened, and then the second polycrystalline silicon is formed. The film 31 forms cross couples 26 and 27.

At this time, the direct contact hole 3
By deforming and protecting a portion 29a of the gate electrode 6 near the opening of 0 along the isolation oxide film 3 as shown in the figure, the direct contact hole 30 is largely opened due to instability in the process. The etching of the isolation oxide film 28 due to misalignment with the gate electrode 29 prevents deterioration of isolation characteristics between transistors.

The present invention is summarized as follows. (1) In the method of manufacturing a semiconductor device according to the claims, the isolation oxide film is formed by a LOCOS method.

(2) In the method of manufacturing a semiconductor device according to the claims, the protective film is formed of polycrystalline silicon.

(3) In the method described in (2) above, the polycrystalline silicon contains impurities.

(4) In the method described in the claims, the protective film is formed of a silicon nitride film.

(5) In the method described in the claims, the protective film is formed of a refractory metal film or a composite film composed of a refractory metal film and a polycrystalline silicon film.

(6) In the method described in the claims, the protective film is formed of a conductive material.

(7) In the method described in the claims, the protective film is formed of a polycide film.

(8) The method as set forth in the claims, wherein a direct contact hole for exposing another portion of the surface of the conductive layer in the interlayer insulating film prior to etching the interlayer insulating film. Is further provided, and the protective film is formed so as to contact the conductive layer through the direct contact hole.

(9) A semiconductor substrate having a main surface, a conductive layer provided on the main surface of the semiconductor substrate, and a conductive layer provided on the main surface of the semiconductor substrate for separating the conductive layer from other conductive layers. Isolation oxide film and an interlayer insulating film provided on the semiconductor substrate including the isolation oxide film, wherein the interlayer insulating film has a connection for exposing a part of a surface of the conductive layer. A wiring layer provided with a hole, further provided on the interlayer insulating film and electrically connected to the conductive layer via the connection hole, and provided on the isolation oxide film, and A semiconductor device comprising: a protective film formed of a material that is not etched under etching conditions for etching an interlayer insulating film and protecting the isolation oxide film from the etching.

[0056]

As described above, according to the method of manufacturing a semiconductor device of the present invention, the isolation oxide film is prevented from being etched during the etching even if the mask is displaced prior to the etching of the interlayer insulating film. Since a protective film for protecting the isolation oxide film is formed on the isolation oxide film, even if the distance between the side wall of the contact hole and the end of the isolation oxide film becomes short, the isolation film is separated at the time of forming the contact hole. The oxide film is not etched. As a result, a semiconductor device that can be miniaturized and has an improved degree of integration can be obtained. Further, the process is simplified, and the heat treatment can be further reduced.

[Brief description of drawings]

FIG. 1 is a sectional view showing a first step of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a sectional view showing a second step of the method for manufacturing a semiconductor device according to the embodiment of the present invention.

FIG. 3 is a sectional view showing a third step of the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 4 is a sectional view showing a fourth step of the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 5 is a cross sectional view showing a fifth step of the method for manufacturing the semiconductor device according to the embodiment of the present invention.

6 is a plan view of the semiconductor device shown in FIG.

FIG. 7 is a plan view of a semiconductor device according to another embodiment of the present invention.

FIG. 8 is a plan view of a semiconductor device according to still another embodiment of the present invention.

9 is a sectional view showing a first step of the method for manufacturing the semiconductor device shown in FIG.

10 is a sectional view showing a second step of the method for manufacturing the semiconductor device shown in FIG.

FIG. 11 is a cross-sectional view showing a first step of a conventional method for manufacturing a semiconductor device.

FIG. 12 is a sectional view showing a second step of the conventional method for manufacturing a semiconductor device.

FIG. 13 is a sectional view showing a third step of the conventional method for manufacturing a semiconductor device.

FIG. 14 is a sectional view showing a fourth step of the conventional method for manufacturing a semiconductor device.

FIG. 15 is a cross-sectional view showing a fifth step of the conventional method for manufacturing a semiconductor device.

16 is a plan view of the semiconductor device shown in FIG.

FIG. 17 is a cross-sectional view showing the problem of the conventional method for manufacturing a semiconductor device.

FIG. 18 is a cross-sectional view showing an improved method for manufacturing a conventional semiconductor device.

FIG. 19 is a plan view of a semiconductor device according to still another embodiment of the present invention.

FIG. 20 is a plan view of a semiconductor device according to still another embodiment of the present invention.

FIG. 21: MOS type static R with high resistance as load
It is an equivalent circuit diagram of AM.

FIG. 22 is a pattern diagram of a MOS static RAM according to still another embodiment of the present invention.

[Explanation of symbols]

 3 Isolation Oxide Film 4 n-Type Diffusion Layer 5 Interlayer Insulation Film 6a Protective Film 10 Contact Hole 11 Aluminum Wiring Layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location // H01L 21/336 29/784

Claims (1)

Claim: What is claimed is: 1. A step of forming a conductive layer on a main surface of a semiconductor substrate, and an isolation oxide film for separating the conductive layer from another conductive layer on the main surface of the semiconductor substrate. A step of forming, an step of forming an interlayer insulating film on the semiconductor substrate including the isolation oxide film, and selectively etching the interlayer insulating film using a mask, thereby, the surface of the conductive layer A semiconductor comprising: a step of forming a connection hole exposing a part thereof; and a step of forming a wiring layer for electrically connecting with the conductive layer through the connection hole on the semiconductor substrate. In the method of manufacturing a device, prior to etching the interlayer insulating film, the isolation oxide film is protected on the isolation oxide film so that the isolation oxide film is not etched during the etching even when the mask is displaced. A method for manufacturing a semiconductor device, which comprises forming a protective film for the semiconductor device.