JPH0521376B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a buffer memory communication system, and more particularly to a buffer memory communication system for mutual communication between a plurality of processors.

(b) Prior Art and Problems FIG. 1 is a block diagram showing an example of a conventional multiprocessor system in which a plurality of processors communicate with each other.

In the figure, LPUa is the local processor, MMa is the main memory of the local processor LPUa, and BUS
−A is the bus of local processor LPUa, LPUn
is a local processor, MMn is a main memory of the local processor LPUn, BUS-N is a bus of the local processor LPUn, CCA is an inter-channel adapter, CTL is a control device, and IOB is an IO buffer.

Data transfer using the conventional CCA method will be explained below with reference to the diagram.

The CCA method is an abbreviation for Channel to Channel Adapter method, and is called an inter-channel transfer method.

Now, when local processor LPUa refers to the contents of main memory MMn of local processor LPUn, the contents of main memory MMn are transferred to main memory MMa through inter-channel adapter CCA.
It is necessary to transfer the data to the main memory MMa and then access the main memory MMa.

For this reason, the local processor is transferred twice: when the inter-channel adapter CCA transfers data to the main memory MMa, and when the local processor LPUa refers to the contents transferred to the main memory MMa via the adapter CCA. LPUa bus
BUS-A had the disadvantage of being accessed.

(c) Object of the Invention The object of the present invention is to eliminate the above-mentioned drawbacks of the prior art and provide an efficient buffer memory communication system in which the bus is used less frequently.

(d) Structure of the Invention According to the present invention, the above object is to provide a multiprocessor system that performs mutual communication between a plurality of processors, which includes a buffer memory for storing communication data between the plurality of processors. , the buffer memory can be arbitrarily switched and connected to the address space of the main memory of each processor, data transfer between the processors is performed via the buffer memory, and a part of the memory address space is This is achieved by providing a buffer memory communication method characterized in that the address space is configured to be alternately used in the own system or in the other system by making attributes changeable by an attribute storage means. .

(e) Embodiment of the Invention FIG. 2 is a block diagram showing an embodiment of the buffer memory communication system according to the present invention.

In the figure, LPUa is the local processor, MMa is the main memory of the local processor LPUa, and BUS
-A is the bus of the local processor LPUa, z is the switch control register, similarly, LPUb is the local processor, and MMb is the local processor LPUb.
main memory, BM is the local processor
The buffer memory of LPUb, BUS-B is the bus of local processor LPUb, and SW is a changeover switch.

FIG. 3 is a block diagram showing another embodiment according to the present invention.

In the figure, LPUc is the local processor, MMc is the main memory of the local processor LPUc, and BUS
-C is the bus of the local processor LPUc, BMb is the buffer memory of the local processor LPUb,
BMc is a buffer memory of the local processor LPUc, SWb is a switch of the local processor LPUb, SWc is a switch of the local processor LPUc, and other symbols and numbers are the same as in FIGS. 1 and 2.

FIG. 4 is a block diagram showing yet another embodiment according to the present invention.

In the figure, z ₀ and z ₁ are switch control registers, respectively.
BMb ₀ and BMb ₁ are local processors LPUb, respectively.
The buffer memories SWb ₀ and SWb ₁ are the switches of the local processor LPUb, BMc ₀ and BMc _1, respectively.
are the buffer memories of the local processor LPUc, and SWb ₀ and SWb ₁ are the buffer memories of the local processor LPUc, respectively.
This is the LPUb switch, and the other symbols and numbers are the same as in FIGS. 1 to 3.

The details of the present invention will be explained below with reference to the drawings.

The method shown in Fig. 2 is the simplest example, in which the main memory MMa of local processor LPUa is transferred from the main memory MMb of local processor LPUb.
When transferring data to the local processor LPUa, the local processor LPUa controls the switch SW using its attribute storage register z, and transfers the buffer memory BM to the bus BUS.
- Connect to the A side, transfer the contents of the specified address of the main memory MMa to the buffer memory BM, and after the transfer is completed, control the switch SW using the attribute storage register z, and connect the buffer memory BM to the bus BUS-B. . local processor
LPUb is activated by a signal from buffer memory BM and transfers the contents of buffer memory BM to its own main memory MMb.

In the case of FIG. 3, a local processor LPUc system is added to the example of FIG. 2. In this case, buffer memory is also allocated to the local processor LPUc.
BMc and switch SWc as local processors
Add it in the same way as LPUb.

In this case, the method of transferring data from local processor LPUa to local processor LPUc is exactly the same as in the case of FIG. 2, and switch SWb and switch SWc are controlled by attribute storage register z.

The method shown in Figure 4 is based on the local processor LPUb.
and local processor LPUc are each provided with two buffer memories BMb ₀ , BMb ₁ and BMc ₀ , BMc ₁ , and switch control registers z ₀ , z ₁ . Switch control register z ₀ is buffer memory
BMb ₀ and BMc ₀ are controlled, and the switch control register z ₁ controls buffer memories BMb ₁ and BMc ₁ .

In this method, in order to transfer data from local processor LPUa to local processor LPUb, buffer memory _{BMb 0 of} local processor LPUb is transferred to the bus under the control of switch control register z0.
When connected to BUS-A, buffer memory BMb ₁ of local processor LPUb is connected to bus BUS-B.
Because it is connected to the local processor LPUb
has the advantage of being directly addressable.

When transferring data from local processor LPUa to local processor LPUc, the buffer memory _BMc0 of local processor LPUc is transferred to the bus by controlling the switch control register _z0 .
When connected to BUS-C, buffer memory _BMc1 of local processor LPUc is connected to bus BUS-A.
It is connected to the.

Also, when transferring data from local processor LPUa to local processor LPUb, if switch control register _z0 is already in use, data can be transferred in the same way using switch control register _z1 . be.

(f) Effects of the Invention As described in detail above, the present invention has the great effect of realizing an efficient buffer memory communication system in which the bus is used less frequently.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a conventional multiprocessor system in which a plurality of processors communicate with each other. FIG. 2 is a block diagram showing an embodiment of the buffer memory communication system according to the present invention. FIG. 3 is a block diagram showing another embodiment according to the present invention. FIG. 4 is a block diagram showing yet another embodiment according to the present invention. In the figure, LPUa is the local processor, MMa is the main memory of the local processor LPUa, and BUS
−A is the bus of local processor LPUa, LPUn
is the local processor, MMn is the main memory of the local processor LPUn, BUS-N is the bus of the local processor LPUn, CCA is the adapter between channels, CTL is the control device, IOB is the IO buffer,
z is the switch control register, LPUb is the local processor, MMb is the local processor LPUb
main memory, BM is the local processor
Buffer memory of LPUb, BUS-B is bus of local processor LPUb, SW is changeover switch,
LPUc is the local processor, MMc is the main memory of the local processor LPUc, BUS-C is the bus of the local processor LPUc, BMb is the buffer memory of the local processor LPUb, BMc is the buffer memory of the local processor LPUc, and SWb is the local processor LPUc. The switch of LPUb, SWc is the switch of the local processor LPUc, z ₀ and z ₁ are the switch control registers, BMb ₀ and BMb ₁ are the buffer memories of the local processor LPUb, and SWb ₀ and SWb ₁ are the buffer memories of the local processor LPUb, respectively.
The switches of LPUb, BMc ₀ and BMc ₁ are the buffer memory of local processor LPUc, SWb ₀ ,
SWb ₁ is a switch for each local processor LPUb.

Claims (1)

[Scope of Claims] 1. In a multiprocessor system that performs mutual communication between a plurality of processors, a buffer memory is provided for storing communication data between the plurality of processors, and the buffer memory is used as a main processor of each processor. The memory address space can be arbitrarily switched and connected, data is transferred between each processor via the buffer memory, and some attributes of the memory address space are changed by an attribute storage means. A buffer memory communication system characterized in that the address space is alternately switched between the own system and the other system. 2 In the above system, by providing a plurality of memories belonging to switchable address spaces and changing the contents of the attribute storage means of each memory, any memory can be alternately used in the own system or in the other system. A buffer memory communication system according to claim 1, characterized in that: 3 In the above system, the memory address space is divided, and attribute storage means is provided for each divided space,
2. The buffer memory communication system according to claim 1, wherein each divided space is alternately used in its own system or in another system by changing the storage contents.