JPH052156B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing device, and particularly to a display device that displays text, still images, moving images, etc. on a display device.

[Conventional technology]

Raster scanning cathode ray tube (CRT)
) is used as a display device to display sentences (text), still images, etc. stored in memory (for example, refresh memory using dynamic memory).
The function of displaying information such as moving images is one of the important functions of an image processing device. Generally, when displaying text or still images on a raster scanning type CRT, the information to be displayed on the screen is edited and stored in refresh memory, and then read out sequentially in synchronization with the CRT's scanning timing. In some cases, a display method is adopted. In this method, the CRT screen is regularly divided into a number of small sections as shown by the dotted lines in Figure 2, each subsection corresponds to one character or one graphic element, and text or still images are stored. It is expressed as a series of characters and graphic elements. Figure 3 shows the central processing unit (hereinafter referred to as CPU)
51, a display address register 54, a refresh memory (hereinafter referred to as video memory) 52 in which display data is edited and stored, and its peripheral circuits.

The display data is sent from the CPU 51 to the video memory 52.
Input/output is performed by specifying the address. The display data written in the video memory 52 is read out in the order specified by the display address register 54, converted into a serial video signal 61 by the display data register 53, and supplied to the CRT. Also, deflection synchronization signals 59 and 6 for horizontal and vertical deflection of the display (CRT) 58 are provided.
0 is generated and sent to the CRT58 along with the video signal. Display is performed by repeating these operations in synchronization with the scanning timing of the CRT.

Recently, in addition to the display of text and still images, video display in which characters and figures are moved to arbitrary positions on the screen and displayed is required for applications such as games. FIG. 4 is a block diagram of a display device applied to such uses. With this display device, for example, when displaying a moving object such as an airplane moving in the sky,
Landscapes on the ground are displayed as still images, and moving objects such as airplanes are displayed as moving images. The portion displaying still images is the portion surrounded by dotted lines in the figure, and has the same configuration and operation as the display device shown in FIG. 3 described above. The attribute memory 112 of the part that displays the moving image stores attribute information of moving image figures, such as what kind of figure to display, and can be rewritten by the CPU 101. The character/figure generator 113 stores display data of moving image figures. During the display period, the match detection circuit 115 extracts a moving image figure to be displayed based on the attribute information at each scanning position in the vertical direction of the scanning line.
The buffer memory 1 reads the display data corresponding to the figure from the character/figure generator 113 and displays it at the horizontal position specified by the attribute information.
14. Next, the contents of the buffer memory 114 are sequentially read out at timings synchronized with the scanning system, and converted into a serial video signal 119 by the display data register 116. The serial video signal 119 is mixed with the still image video signal 111 by a mixer 120, and is supplied to a CRT for display. Display is performed by repeating the above operations.
Generally, the video memory 1 in such a display device
Display data such as 02 is frequently rewritten by the CPU 101 in order to re-edit characters and graphics. In this way, from CPU 101 to video memory 1
When a memory access request for 02 occurs, addressing information from the CPU 101 is supplied to the video memory 102 by the switching device 106. The display data read out from the video memory 102 is taken into the CPU 101, processed, and then stored again at the designated position. Such memory access requests from the CPU occur regardless of the CRT display timing, so if CPU memory access is given unconditional priority, if a memory access request occurs during the display period, the display The display data cannot be read out due to the address specification of the address register 104, which causes an inconvenience.

[Problem that the invention seeks to solve]

In this way, in the conventional display device described above, when the CPU accesses the video memory during the display period, an address different from the display address is supplied to the video memory, causing display disturbances and preventing normal display operation. do not have. Therefore, in conventional display devices, in response to memory access requests from the CPU,
The video memory can only be released during vertical and horizontal blanking periods other than the display period, which does not affect the display. As a result, each time the CPU accesses the video memory for display data processing, it has to wait for several tens of microseconds, resulting in extremely poor operability and the CPU's inherent ability to perform various calculations and control. This has the disadvantage that it is not suitable as a display device where frequent display data processing is required.

Furthermore, since still image display data and video display data must be set independently in separate video memory systems, it is possible, for example, to use part of the still image display data as video display data. I can't. Also, when looking at the system as a whole, the address and data control circuits, parallel
Since it is necessary to configure serial conversion shift registers and the like separately for the still image display system and the moving image display system, the input/output lines become complicated and the circuit scale becomes quite large.

[Purpose of the invention]

The purpose of the present invention is to have no effect on the display at all even when the CPU accesses the video memory.
The CPU can read and write data to the video memory without being influenced by display timing, improving data bus usage efficiency and maximizing display data processing speed and CPU utilization. Another object of the present invention is to make it possible to share the hardware required for a still image display system and a moving image display system as much as possible, and to provide an inexpensive display device.

[Means for solving problems]

The display device of the present invention includes an attribute memory that stores at least video identification information and display position information, and a video memory that stores display data of video and still images.
An editing memory that edits and stores the display data read out from the video memory and generates a display signal to the display device, a display address generation circuit that indicates the display address, and a display address generation circuit that reads the contents of the attribute memory and determines the video display position information. a position detection circuit for detecting that the display address is within the range of , a first addressing means for addressing the video memory based on the display address of the display address generation circuit, and a first addressing means for addressing the video memory based on the display address of the display address generation circuit; It has a second addressing means for originally addressing the video memory, and an access means for the CPU to address the attribute memory or video memory and input/output data, and the output of the position detection circuit and the operation of the CPU. Based on the identification signal, the first and second addressing means and the access means are operated exclusively in a predetermined priority order, and when there is an operation from the central processing unit, the display address generation circuit and the editing memory are operated. It is characterized by suppressing update of the edit address.

〔Example〕

Next, embodiments of the present invention will be described in detail using the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. The video memory 1 stores display data of text, still images, and some moving images equivalent to several CRT screens. Attribute memory 1
9 stores moving image identification information indicating the type of moving image figure to be displayed, display position information specifying the position where it should be displayed, color information, and other attribute information necessary for display. The first editing memory 15 and the second editing memory 16 each have a capacity capable of storing display data necessary for displaying at least one scanning line,
Each scanning line is used alternately for writing and reading. Under the control of the editing memory switching circuit 17, the output of the write address generation circuit 13 is supplied to the editing memory allocated for writing during the scanning period, and the display data read from the video memory 1 is It is converted into optical data that directly corresponds to the display, edited, and stored. Further, the output of the read address generation circuit 14 is supplied as an address to the editing memory allocated for reading, and the data read from this address is loaded into the parallel-to-serial conversion shift register 3 via the data selection circuit 18. be done. An address line 31 for specifying an address and a data input/output line 33 are connected to the attribute memory 19, and an address line 32 and a data input/output line 34 are similarly connected to the video memory 1. Further, a memory write signal 6 for instructing a write operation from the CPU and a memory read signal 7 for instructing a read operation are connected to each memory. When writing display data and attribute information to the video memory 1 and the attribute memory 19, respectively, the address selection circuits 12 and 21 are first switched by the memory access request signal 11, and the value of the address bus 4 of the CPU is written to the address lines 31 and 32. The data input/output lines 33 and 34 are connected to the data bus 5 via the data buffers 27 and 30. The CPU specifies addresses for these lines to the video memory 1 and attribute memory 19, and sends data thereto. When a required number of predetermined display data are written and stored in each memory, memory access for displaying these data is then started. Normally, the address selection circuit 12 is switched so that the output of the display address generation circuit 2 is connected to the address line 32 of the video memory 1. At the same time, the memory read signal 6 is activated, and the display data read from the video memory 1 is written into the edit memory, which is operating for writing during the current scanning period, by the edit memory write signal 226. In the display address generation circuit, each time the display data of the video memory 1 is read, the display address is updated in order to read the next display data, and the video memory 1 is continuously accessed based on the newly generated display address. Further, the edit memory write address generation circuit 13 updates the address every time display data is written, and writes to the edit memory are performed based on the newly created edit memory address. In this way, reading display data,
By repeating writing to the editing memory, still image display data is sequentially stored in the editing memory for writing. On the other hand, the output of the attribute counter 20 is switched to be connected to the address 31 in the attribute memory 19 by the address selection circuit 21 . The attribute counter 20 is reset for each scan and provides an address for sequentially reading the data in the attribute memory 19. The attribute memory 19 identifies the type of figure to be displayed, and outputs moving image identification information used as address information of the video memory 1, vertical display position information (Y), horizontal display position information (X), and the like. Y is input to the subtraction circuit 23 and subtracted from the output (VC) of the vertical line counter 22 (VC-Y→ΔY). Vertical line counter 2
2 indicates the next position to be scanned in the vertical direction, and a value one more than the actual position of the scanning line is entered, and the contents of the vertical line counter 22 are incremented by 1 each time the scanning line advances by one line. It will be counted up. The output (ΔY) of the subtraction circuit 23 is
4, and comparison and detection are performed to see if the value is within a preset range. This is the attribute memory 1 at the next vertical scan position of the scan line.
This is to check whether there is a figure to be displayed in the contents of 9. This operation control is performed by successively reading out the contents of the attribute memory 19 during one scanning period of the scanning line. Subtraction circuit 23 and comparison circuit 2
4, when a figure to be displayed is detected, the position detection signal 25 is activated. The position detection signal 25 is input to the display address generation circuit 2, the address selection circuit 12, the attribute counter 20, and the write address generation circuit 13. Select information and video memory 1
At the same time, updating of the display address of the display address generation circuit 2 is suspended, and the operation of the attribute counter 20 is also stopped.

Next, in the write address generation circuit 13, the update of the write address of the still image display data is suspended, and the horizontal display position information (X) read from the attribute memory 19 at the same time as the video identification information is taken in. The edit memory write address is generated based on the . The video display data read out from the video memory 1 based on the video identification information is edited and stored in the location specified by the address of the editing memory allocated for writing.
be remembered. When writing of the predetermined display data of the detected moving picture figure into the editing memory is completed, the position detection signal 25 is deactivated, and the address selection circuit 12 connects the address line 32 with the output of the display address generation circuit 2 again. Switched to connected. In addition, the display address update, the operation of the attribute counter 20, and the write address generation circuit 1
The update of the writing address of the still image display data in step 3 is restarted, and the still image display data processing is performed again. When a moving image figure to be displayed is detected from the attribute memory 19 in this way, the still image display data and the operation control that is read out from the video memory 1 and continuously edited and stored in the editing memory are temporarily suspended. , the video display data is processed first. In this way, by repeating the reading of still image and video display data to be displayed during the next display period and writing to the editing memory, all the display data for one scanning line is edited and stored in the same editing memory. be done.

On the other hand, consecutive addresses are periodically supplied to the read editing memory from the read address generation circuit 14 in synchronization with the display timing, and data is read out sequentially. The output of the read editing memory is set in the parallel-to-serial conversion shift register 3 under timing control by the load clock 8. This is shifted in accordance with the shift clock 9 and becomes a serial video signal 10, which is supplied to the CRT.
By repeating these series of operations, one scanning line is displayed. When the display for one scanning line is completed, the editing memory switching circuit 17 reads out the contents of the editing memory for writing into the next scanning display.
, the editing memory that was operating for writing is supplied with the editing memory read address, and the editing memory that was operating for reading is supplied with the editing memory write address. Lines begin to be displayed. The display is maintained by repeating the above operations.

Next, during this display operation, drawing the figure,
To process display data such as editing
The operation timing when an access request is issued to the video memory 1 from the CPU will be explained.
FIG. 5 is a timing chart showing the relationship between the address of the video memory, the write address of the editing memory, and the write and read signals of the memory when an access request is made to the video memory 1 during the display period. MC _n-2 and MC _n-1 are normal display cycles, and display addresses or moving image identification information (DADO _-1 , DAD _o ) are supplied to the video memory 1. Also, the edit memory write signal 26 is activated, and the read display data is edited and stored in the edit memory. The cycle of MC _n+1 of MC _n is a video memory access other than display, and the memory access request signal 11 is activated. First, a read address (RDADR) from the CPU is given to the video memory 1 under the control of the address selection circuit 12 . Display data (RDD) is output to the data bus 5 via the data buffer 27 in response to the memory read signal 6, and is taken in and processed by the CPU or a device that processes image information (MC _n ). Then write address (WRADR)
is given to the video memory 1. At the same time, the memory write signal 7 is activated and the processed write display data (WRD) is stored in the video memory (M _n+1 ). When the access request timing by the CPU ends, the output of the display address generation circuit 2 or the output of the attribute memory 19 (DAD _o+1 ) is again supplied to the video memory 1, and the display data (D _o+1 ) is read and written. (MC _n+2 ).

In this way, during the period when the memory access request signal 11 is activated, the display address is
Address information from the CPU is supplied to the video memory 1, and video memory access from the CPU is given priority over access for display. Furthermore, under the control of the memory access request signal 11, updating of the display address of the display address generation circuit 2 and updating of the write address of the editing memory are stopped.
However, the memory access request signal 11 has no effect on the read system of the editing memory.
Therefore, even if a memory access request occurs, the editing memory is read only by CRT scanning (display timing).
This is done continuously in synchronization with the In addition, the number of video memory read cycles required to store one scanning line of display data in the writing editing memory is less than the total number of accesses that occur during one scanning period, and the remaining cycles are all displayed by the CPU. It can be used at the required timing as an access cycle for data processing.

〔Effect of the invention〕

As explained above, the present invention stores still image and moving image display data in the same editing memory, and when a request for editing and storage processing of moving image display data in the editing memory occurs, By temporarily suspending the same processing that is being performed on still image display data and giving priority to video processing, the operation of detecting the video figure to be displayed from the attribute memory can be performed on the still image display data. Since editing and storage processing can be performed in parallel, a large number of moving image figures can be set. Moreover, when a figure to be displayed is detected, the display data for that figure can be processed immediately, so there is no need to temporarily store and store the attribute information of the detected moving image figure until it can be processed. , the circuit configuration of the device is extremely simple. In addition, there is no need to configure control circuits essential for display, such as video memory and parallel-to-serial conversion shift registers, separately for still image display systems and video display systems as in conventional display devices, and This has the effect of realizing a still image and moving image display device using hardware.

Further, according to the present invention, there is provided a device that can immediately stop access for display in response to a video memory access request from the CPU, allow the CPU to control the video memory, and has no effect on the display. realizable. Therefore, the CPU can control the video memory without being aware of display states such as during the display period and during the retrace period. In addition, if the video memory is accessed, waiting until the timing such as the retrace period, when no display disturbance occurs, will almost never occur, and by drastically reducing CPU waiting time, CPU original calculations will not occur. , processing power such as control, and bus usage efficiency can be maximized. Further, although a memory with a capacity capable of storing display data for one scanning line is required as an editing memory, it can be easily realized economically at a relatively low cost due to the remarkable increase in memory integration and price reduction in recent years.
Furthermore, the address supplied to the buffer memory for reading may have a value that changes continuously in synchronization with the display timing;
It can be obtained from the output of counters used in the part that generates the synchronization signals necessary for CRT timing control, and does not require a dedicated control circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention;
Fig. 2 is a diagram showing an example of displaying characters and figures using a conventional display, Fig. 3 is a block diagram of a conventional still image display device, Fig. 4 is a block diagram of a conventional moving image display device, and Fig. 5 is a diagram showing an example of displaying characters and figures using a conventional display. FIG. 2 is a diagram of operation timing in one embodiment of the present invention shown in FIG. 1; 1...Video memory, 2...Display address generation circuit, 3...Parallel-serial conversion shift register, 4...
...Address bus, 5...Data bus, 6...Memory read signal, 7...Memory write signal, 8
...Load clock, 9...Shift clock, 1
0...Serial video signal, 11...Memory access request signal, 12, 21...Address selection circuit, 13
... Write address generation circuit, 14 ... Read address generation circuit, 15, 16 ... Edit memory, 17 ... Edit memory switching circuit, 18 ... Data selection circuit, 19 ... Attribute memory, 20 ... Attribute counter, 22... Vertical line counter, 23
... Subtraction circuit, 24 ... Comparison circuit, 25 ... Position detection signal, 26 ... Edit memory write signal, 2
7, 28, 29, 30...data buffer, 3
1, 32... Address line, 33, 34... Data input/output line, 51, 101... CPU, 5
2,102...Video memory, 53,103,11
6... Display data register, 54, 104...
Display address register, 55, 105...Synchronization signal generator, 56, 106, 118...Switcher,
57,107...Video signal amplifier, 58,108
...CRT, 59,109...Horizontal synchronization signal, 6
0,110...Vertical synchronization signal, 61,111,1
19...Serial video signal, 112...Attribute memory,
113... Character, figure generator, 114... Buffer memory, 115... Match detection circuit, 117...
Address register, 120... mixer.

Claims (1)

[Claims] 1. A first storage device that stores video identification information and display position information, a second storage device that stores video and still image display data, and edits the display data read from the second storage device. , a third storage device that stores information and generates a display signal to a display device; a display address generation circuit that indicates a display address; and a display address generation circuit that reads out the contents of the first storage device so that the display position information of the moving image is within a predetermined range. a position detection circuit for detecting that the display address is the same; a first addressing means for addressing the second storage device based on the display address of the display address generation circuit;
a second addressing means for addressing the second storage device based on the video identification information read from the storage device; and a central processing unit for addressing the first or second storage device. , an access means for inputting and outputting data, and controlling the first and second addressing means and the access means in a predetermined priority order based on the output of the position detection circuit and the operation identification signal of the central processing unit. A display device that operates exclusively and inhibits updating of the edit address of the display address generation circuit and the third storage device when there is an operation from the central processing unit.