JPH0521709A - Semiconductor integrated circuit device and mega cell - Google Patents

Abstract

PURPOSE:To make a chip easier to design and also simplify wiring by using a mega cell to be used in a cell base method, providing a region for supporting external wiring inside the mega cell, and placing transistors over a portion except the mega cell. CONSTITUTION:A basic cell 3 having a mega cell 1 being a large-sized fixed- type layout library and a plurality of transistors is placed on a semiconductor substrate. A wirable region 1a is provided inside the mega cell 1, while a function such as a timer which the mega cell should be equipped with is formed of two function regions 1b, 1c. Since the mega cell has its circuit pattern optimized and a transistor size is designed without waste for each of individual elements, a chip area can be reduced and also excellent characteristics such as operation speed can be obtained. Further since the wirable region 1a is provided inside the mega cell, wiring outside the mega cell is extremely easy, thereby solving a problem such as additional wiring capacity.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and its megacell, and more particularly to an LSI for a specific application having an improved layout system and a megacell mounted therein.

[0002]

2. Description of the Related Art Conventionally, there have been basic LSIs for specific applications as shown in FIGS.

The method shown in FIG. 2 is called a cell-based method, and is a large-scale circuit cell such as a peripheral circuit such as a CPU core or a timer that has already been created (this is called a mega cell).
This is a system in which 1 and a TTL level cell (this is called a macro cell or a standard cell) 2 are combined, and a wiring region is separately provided in addition to the transistor portion.

The method shown in FIG.
A gate-layout type array in which a basic cell 3 having a plurality of transistors is spread over the entire surface, or an SOG (Sea of Sea)
It is called a gate). In general, a gate array is manufactured in advance up to the step of forming a transistor (this is called a master step), and the wiring step and the subsequent steps are changed according to a user's circuit configuration (this is called a slice step) to manufacture a custom LSI. In the case of the SOG method, no wiring region is provided and the entire surface is covered with transistors. Therefore, when forming a mega cell, since wiring is performed using these transistors, it is not a fixed type cell.

[0005]

Although the conventional LSI for a specific application is configured as described above, the problem with the cell-based method shown in FIG. 2 is that the process steps are It becomes longer and the whole LSI development period becomes longer, and the LSI development period becomes longer due to the circuit change.
When the SI is revised, it is necessary to revised all layers.

The problem with the gate array system of FIG. 3 is that the lower the gate usage rate, the larger the chip area (actually the ratio of the chip area to the transistors used) and the higher the cost. Since the megacell is also created by combining macrocells, its shape changes every time automatic placement and routing is performed, and the characteristics of this portion are not fixed, which makes designing difficult.

The present invention solves the problems of the above two methods at the same time, and shortens the development period to reduce the overall development and the chip cost while keeping the chip area at a medium level or less. An object of the present invention is to obtain a semiconductor integrated circuit device that can be fixed and have a characteristic of being easy to design, and can achieve simplification of wiring, and a mega cell mounted therein.

[0008]

In a semiconductor integrated circuit device according to the present invention, a megacell used in a cell-based system is used in a fixed shape, and an area where external wiring can be provided is provided inside the megacell, and the area other than the megacell is provided. The part of is configured to be covered with transistors.

Further, the mega cell according to the present invention is provided with a region in which an external wiring can be wired, and sandwiches this wirable region,
The functional areas that realize a single function are arranged in a plurality of areas.

[0010]

In the present invention, the megacell in the cell base system is used as it is, and an area where external wiring can be wired is provided in the megacell, and the portion corresponding to the macrocell portion and the wiring portion is covered with transistors like SOG. With this configuration, the chip area can be reduced and the development period can be shortened, the cost can be reduced, the cell characteristics can be fixed, and a new layout method that facilitates the design can be established. In addition, wiring can be eliminated by the wirable area provided in the mega cell.

Further, in the present invention, since the area in which the external wiring can be wired is provided inside the megacell, it becomes possible to wire the wiring outside the megacell through the megacell area. Since it is not necessary to make a detour to bypass the wiring, the wiring becomes easy.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a semiconductor integrated circuit device and a mega cell according to an embodiment of the present invention. In the figure, 1 is a megacell which is a large-scale fixed layout library arranged on a semiconductor substrate, 3 is a basic cell having a plurality of transistors, and a region on the semiconductor substrate other than the region where the megacell 1 is arranged, In particular, they are arranged without providing a wiring region.

Reference numeral 1a is a wirable area formed inside the megacell, and 1b and 1c are functional areas of the megacell formed so as to sandwich the wirable area. This is realized by the two areas 1b and 1c.

Next, the operation and effect will be described. The semiconductor integrated circuit device according to this embodiment is a combination of a cell-based megacell and a gate-laying array.

The mega cell is a cell of a large-scale circuit used for a limited purpose such as a CPU, a multiplier, and a timer circuit, and can be realized by a gate array system, but by the gate array system. When realized, the megacells are developed into regularly arranged basic cells, so that the circuit becomes redundant and the cell area becomes large, and a problem occurs such that a load is generated in the elongated wiring and it becomes unsuitable for high-speed operation.

On the other hand, in the present embodiment, the circuit that can be realized by the megacell is mounted on the semiconductor substrate as it is as the original megacell whose pattern shape is fixed. Can be used as is.

That is, the circuit pattern of the original megacell is optimized, and the transistor size and the like are designed without waste for each individual element. Therefore, the original mega cell has a smaller cell area than the case where it is realized by the gate array method, and it is possible to reduce the chip area and obtain excellent characteristics such as operating speed. Advantageously, since the pattern is fixed, the circuit characteristics are also fixed. In addition, the development period can be shortened by using the mega cell registered as the fixed layout library.

Therefore, by mounting the original megacell, it becomes easier to design the portion corresponding to this megacell, as compared with the case where it is configured by the SOG method.
Design mistakes are reduced. The reason is that the SOG method is premised on the use of an automatic placement and routing tool, and when the design is performed by the automatic placement and routing tool, the placement changes each time, and therefore the circuit characteristics may vary.

Further, in the same manner as the mega cell, the basic cell is arranged by the SOG method in the area where the standard cell, which is formed by full custom, is to be formed instead.
The circuit can be completed simply by performing the wiring process, and the development period can be shortened as compared with the cell base in which all the regions on the substrate are fully custom-made. Also, when changing the circuit, it is possible to deal with it promptly by changing only the wiring relationship.

Further, from the above, it is understood that this embodiment has the following extremely useful effects. That is,
Conventionally, in order to implement a required function into an LSI, it has been necessary to decide an implementation method in consideration of advantages and disadvantages of a cell-based method and a gate array method, and this decision depends on a difference in specifications of elements formed by each method. According to the present embodiment, the cell-based method is used for a large cell whose function is required, and the gate array method is used for the other cells. By forming it, it is not necessary to decide the method in the simulation stage, and it can be decided mechanically in the layout stage.

Table 1 summarizes the merits and demerits of the conventional cell-based method, gate array method and this embodiment.

[0022]

[Table 1]

Further, in the above embodiment, since the wirable region 1a is provided inside the mega cell, the wiring outside the mega cell is routed using this region to bypass the region where the mega cell is formed. Wiring becomes unnecessary, and the wiring becomes extremely easy. Further, it is possible to solve the problem that extra wiring capacitance is added due to the long wiring.

Thus, according to the above embodiment, the LSI
When a large-scale circuit such as a CPU, its multiplier, and a timer circuit is to be mounted on the top, mega cells of which characteristic values and cell shapes are determined are arranged, and the other parts are configured by the SOG system. As a result, the LSI chip area can be reduced, the development period can be shortened to reduce the overall cost, and the cell characteristics can be fixed to reduce design mistakes. The effect is that it can be determined mechanically.

In the above embodiment, the mega cell is provided with the wirable region at one location, but it may be provided at two or more locations.

Needless to say, the shape of the wirable area is not limited to the linear shape and may be, for example, an L shape.

Further, in the above-mentioned embodiment, the gates are spread over the regions other than the mega cells provided with the wirable region. However, a normal gate array having a wiring region and other cells are formed. Good.

[0028]

As described above, according to the present invention, the SOG method is provided in which mega cells each having a wirable region inside and having a predetermined characteristic value and cell shape are arranged, and the other portions are covered with transistors all over the surface. Since the semiconductor integrated circuit device is configured with the
The chip area can be reduced, the development period can be shortened, the overall cost can be reduced, and the cell characteristics are fixed, so design mistakes can be reduced and the routing of wiring outside the megacell can be eliminated. effective.

Further, since the area where the external wiring can be wired is provided inside the megacell, the wiring outside the megacell can be wired through the megacell area, and the wiring can be bypassed to the megacell area. Since it is not necessary to do so, the wiring becomes easy, and problems such as extra wiring capacitance can be solved.

[Brief description of drawings]

FIG. 1 is a diagram showing a semiconductor integrated circuit device and a mega cell according to an embodiment of the present invention, FIG. 1 (a) is a diagram showing a cell arrangement pattern thereof, and FIG. 1 (b) is a diagram showing an internal region of the mega cell. is there.

FIG. 2 is a diagram showing a cell arrangement pattern of a conventional semiconductor integrated circuit device.

FIG. 3 is a diagram showing a cell arrangement pattern of another conventional semiconductor integrated circuit device.

[Explanation of symbols]

1 mega cell 1a Wiring area 1b, 1c functional area 2 standard cells 3 basic cells

Claims (2)

[Claims] 1. In an LSI layout system, a large area is constituted by an area in which wiring other than megacells can be wired and a functional area in which a plurality of areas arranged with the wirable area sandwiched therebetween realize a single function. One or more megacells, which are large scale circuit cells, are arranged on a semiconductor substrate, and a gate-layout array formed by laying only transistor groups is arranged in a region excluding the megacell arrangement region on the semiconductor substrate. A semiconductor integrated circuit device characterized by the above. 2. In a mega cell, which is a large-scale circuit cell mounted in a semiconductor integrated circuit device, a single area is provided by a region in which wiring other than the mega cell can be wired and a plurality of regions arranged with the wirable region sandwiched therebetween. A mega cell characterized by having a functional area for realizing a function.