JPH04112574A - Manufacture of master slice integrated circuit - Google Patents

Abstract

PURPOSE:To design an arbitrary circuit scale on a common master wafer by conducting wiring by using a plurality of rectangular regions in which cells composed of elements such as transistors, which are formed on a wafer by dicing lines, are spread. CONSTITUTION:Rectangular regions 3 are formed by using dicing lines 1, and cells 2 consisting of transistors, resistors, etc., are spread all over the whole surfaces in the regions 3. When a desired circuit is realized by a master slice LSI, a logic circuit having an arbitrary scale, input-output pads 4 in the arbitrary number of inputs and outputs, an input protective circuit and input-output buffers are formed in the proper number of the cells, a proper area and proper chip size, by conducting wirings on the cells 2 by using a plurality of the regions 3 on a master wafer, on the whole surface of which said regions 3 are shaped. The LSIs in the arbitrary number of logic gates and inputs and outputs and in chip size can be designed at the stage of slice.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a master slice integrated circuit, and relates to a method for manufacturing a master slice integrated circuit using a laying method that does not require determining the number of inputs and outputs and the number of gates on a master wafer. It is about the method.

[Conventional technology]

A master slice integrated circuit (master slice LSI) using the conventional layout method has an input/output pad, an input protection circuit, and a human output buffer arranged around the chip, and cells consisting of transistors, resistors, etc. are laid out inside the chip. It had become.

Figure 5 shows a master slice L using the conventional laying method.
Indicates SI.

In the figure, an input/output pad 4 and an input protection circuit/human output buffer 5 are placed around the chip, and cells 2 and 2 are placed inside.
It has a structure that covers the entire area.

During the slicing process, internal cells 2 are used as logic gates and wiring areas on the master chip, and input/output pads 4 are used as logic gates and wiring areas.
By wiring the input protection circuit/human output buffer 5, a desired logic LSI is realized.

[Problem to be solved by the invention]

Since the conventional master slice LSI is configured as described above, only the circuits within the range of the number of input/outputs and the number of internal cells specific to the master chip can be configured, and depending on the configuration of the circuit, the number of input/output pads 4. There is a problem that either one or both of the input protection circuit/input/output buffer 5 and the internal cell 2 are left unused and wasted.

Furthermore, in order to realize a circuit having an arbitrary number of inputs/outputs and a number of logic gates using such a master slice LSI,
In order to minimize the unused portion of the master chip, it was necessary to prepare several types of master wafers on which master chips with different scales of input/output numbers and cell numbers were arranged.

The present invention has been made to solve these problems, and aims to provide a method for manufacturing a master slice integrated circuit in which a master wafer formed of cells consisting of transistors, resistors, etc. can be made common to any circuit scale. purpose.

[Means to solve the problem]

The method for manufacturing a master slice integrated circuit according to the present invention involves forming a rectangular area of an appropriate size on a wafer using a dicing line, filling the inside of this rectangular area with cells consisting of elements such as transistors and resistors, and designing a slice. In this process, cells are wired using multiple rectangular areas so that the chip size is appropriate for the number of inputs and outputs and gates of the circuit.

[Effect]

The method for manufacturing a master slice integrated circuit according to the present invention includes:
A rectangular area of an appropriate size was formed on the wafer using dicing lines, and wiring was done using multiple rectangular areas filled with cells consisting of elements such as transistors and resistors, so the number of logic gates and input/output could be reduced. It becomes possible to design on a common master wafer with any appropriate chip size depending on the number of chips.

〔Example〕

Hereinafter, a method for manufacturing a master slice integrated circuit according to an embodiment of the present invention will be described with reference to FIGS. 1 to 4. FIG.

1 and 2 show a method for manufacturing a master slice integrated circuit according to a first embodiment of the present invention.
The figure shows a part of a master wafer, and FIG. 2 shows how cells are wired using a plurality of rectangular areas 3 shown in FIG. 1.

In these figures, 1 is a dicing line, 2 is a cell consisting of a transistor and a resistor, etc., 3 is a rectangular area,
4 is an input/output pad formed on the cell, dicing line l inside the chip is used as a power supply wiring area, and cell 2 is an input protection circuit.

It is used as a human output buffer, internal circuit and wiring area.

Next, the manufacturing process will be explained.

First, as shown in FIG. 1, a rectangular area 3 is formed using a dicing line 1, and cells 2 composed of transistors, resistors, etc. are spread over the entire surface of the rectangular area 3.

Next, when realizing a desired circuit using a master slice LSI, on a master wafer on which a rectangular area 3 with such cells 2 all over the entire surface is formed, as shown in FIG. 2, the rectangular area 3 is By wiring a plurality of cells 2, a logic circuit of any size and an arbitrary number of input/output pads 4. The two-input protection circuit output buffer is formed to have an appropriate number of cells, that is, an appropriate area, in other words, an appropriate chip size.

As a result, it becomes possible to design a chip-sized LSI with any number of logic gates and input/outputs at the slicing stage.

Furthermore, FIGS. 3 and 4 illustrate the second aspect of the present invention. This shows a method of manufacturing a master slice integrated circuit according to a third embodiment, in which the master slice LSI in FIG. 3 has a smaller number of inputs and outputs than the master slice LSI in FIG.
The master slice LSI in the figure is the master slice L in Figure 2.
This is a case where the number of logic gates is large compared to SI.

Even if the number of inputs and outputs of the circuit or the number of logic gates are different in this way, it can be easily designed using a common master wafer by the same method as in the first embodiment.

In the above embodiments, the case where input/output pads are used has been described, but bumps for flip chips may also be used, and the same effect can be achieved in this case as well.

Further, in the above embodiments, the structure inside the cell was not explained, and the transistors constituting the cell can be composed of one or both of bipolar transistors and MOS transistors.

It should be noted that the resistors constituting the cell can similarly be composed of either or both of a diffusion layer resistor and a polysilicon resistor.

〔Effect of the invention〕

As described above, the present invention is formed on a dicing line,
By forming a rectangular area filled with cells inside and further wiring above the cells, input/output pads, input protection circuits, and human output buffers are provided, so the scale of the LSI can be arbitrarily determined at the slice design stage. There are certain effects.

Furthermore, it is sufficient to prepare one type of master wafer for all master slice LSIs, which has the effect of reducing manufacturing costs.

[Brief explanation of drawings]

FIG. 1 is a pattern diagram showing a part of a wafer in which a rectangular area filled with cells formed by dicing lines is formed on the entire surface in the method for manufacturing a master slice integrated circuit according to the first embodiment of the present invention, and FIG. , 3 and 4 show the first embodiment of the present invention. A pattern diagram showing a master slice LSI chip obtained by the method of manufacturing a master slice integrated circuit according to the second and third embodiments, and FIG. 5 shows a master slice LSI chip realized by a master slice LSI using a conventional tiling method. It is a pattern diagram. In the figure, 1 is a dicing line, 2 is a cell, 3 is a rectangular area, and 4 is an input/output pad. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) A master process in which a plurality of rectangular regions of an appropriate size are formed on a master wafer using dicing lines, and cells consisting of elements such as transistors and resistors are spread over the entire surface inside the plurality of rectangular regions; Manufacture of a master slice integrated circuit characterized by using a plurality of rectangular areas filled with cells and slicing the cells to each other so as to have a chip size suitable for the number of inputs and outputs of the circuit and the number of gates. Method.